Digital Logic Design

ESE-118, Spring 2025

Topic 12: Finite State Machines

Instructor:
Peter Milder

Text: 5.5, 5.7, 5.8

©2025 Peter Milder. Please do not post online.

 Plan
¢ Homework: ¢ Labs:
§ HW 7: Tuesday 4/8 § Lab 6: Adders, week of 3/31
§ HW 8: Thursday 4/17 § Lab 7: Mux-Based Logic, week of 4/7
§ “HW 9”: Ungraded questions, provided § Lab 8: Latches and Flip-Flops, week of 4/4
with solutions § Labs 9 and 10: after midterm 2
§ HW 10: After midterm 2

Tue 4/1 Timing of flip-flops and sequential systems Topic 11 5.4, 5.5 Lab 6 HW 6 due
Thu 4/3 Finite state machines Topic 12 5.5, 5.7, 5.8
Tue 4/8 Finite state machines Topic 12 5.5, 5.7, 5.8 Lab 7 HW 7 due
Thu 4/10 Finite state machines Topic 12 5.5, 5.7, 5.8
Tue 4/15 Finite state machines Topic 12 5.5, 5.7, 5.8 Lab 8
Thu 4/17 Registers & Intro to RTL Topic 13 6.1–6.2, 8 HW 8 due
Tue 4/22 Wrap up and review Topic 14
Thu 4/24 Exam 2 (Topics: 8, 10–12, 14)
2
 REVIEW

92
Synchronous Sequential Systems
Chapter 5 Synchronous Sequential Logic
[Modified Fig. 5.2 from Mano & Ciletti]

Inputs Outputs
Combinational
circuit next
state current
Flip-flops
state
Clock
Clock pulses

(a) Block diagram

(b) Timing diagram of clock pulses

FIGURE 5.2
Synchronous clocked sequential circuit 3
Designing Synchronous Sequential Systems
¢ Now we understand:
§ how flip-flops function
§ how flip-flops are used in sequential systems
§ how to write equations/tables that explain how sequential systems work
§ timing of FFs and sequential systems

¢ What’s left?
§ How to design useful sequential systems?
§ Need a framework for reasoning about how systems behave over time: the finite state
machine

4
First, Some Terminology: Register
¢ A register is a group of flip-flops controlled together
§ A flip-flop has 1 input bit and 1 output bit
§ A n-bit register has n FFs, taking n input bits, producing n output bits
§ Example: a 4-bit register
A0 D Q B0

A
4
D Q
4
B
= A1 D Q B1

CLK
A2 D Q B2

this means B is a
4-bit number A3 D Q B3

5
CLK
Finite State Machine (“Moore machine”)
inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state
CLK

¢ State register: N bits that holds state (memory)

¢ Combinational logic computes next state and output
¢ “Finite state” means system has finite number of possible states
à N-bit register can hold up to 2N possible states
¢ This is considered a “Moore style” FSM
(later we will see one another style, almost the same)
6
Reset Input
¢ We also need a special reset input:

inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state R
CLK

reset

¢ The reset is used to initialize the state to its starting point

7
 State Transition Diagram [Moore Machine]
1
¢ Each circle = a state reset
§ Label indicates state name and that state’s
output value
§ E.g., the top-left state has name “A.” à A/10 B/00
When the FSM is in state A, it outputs 10
0
1
¢ Each arrow = a potential transition on 0 0
the next clock edge
§ Label represents the input value that causes C/11
that transition
§ e.g., “if current state is B and input is 1, then
the next state is C”

1
¢ FSM starts in special “reset” state
8
State Table
¢ Information from state transition diagram, but in table form
§ More compact, but not as illustrative
§ Generally: draw transition diagram, then convert to table
1
reset
current input next output
state state
A/10 B/00
A 0 A 10
0
1
A 1 B 10
0 0 B 0 A 00
C/11 B 1 C 00
C 0 A 11
C 1 C 11
1
9
 1
FSM Function reset
1

CLK A/10 B/00

state 0
A B A B C A 1
The state 0 0
updates just output 10 00 10 00 11 10
after the C/11
positive clock
edge input
1
next_state B A B C A A

“My current state is A “My current state is B

therefore my output is 10. therefore my output is 00.
Also, my input is 1 so my Also, my input is 1 so my
next state is B.” next state is C.” 10
How does this relate to logic?
inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state
CLK
state output
current state represents combinational function
1
information stored in reg. that depends on state
next_state
combinational function that
CLK
depends on state and inputs
state A B A B C A

output 10 00 10 00 11 10

input

next_state B A B C A A
11
How does this relate to logic? reset
1

A/10 B/00
inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N 0
current register
1
state 0 0
CLK
C/11

¢ How to actually design the logic? 1

§ From the state transition diagram (or table), we can derive Boolean expressions for next
state logic and output logic
§ One thing missing: “state assignment”
§ Need to map symbolic state names like “A” to binary numbers to store in state register
§ More on this later! But now let’s design some example FSMs

12
FSM Example 1: Detect Sequence 000
¢ Design an FSM with one input and one output that:
§ takes in an input x on each clock cycle
§ looks for a sequence “000” on x
à that is: x was 0 on the last three positive clock edges
§ detect overlapping sequences, e.g., ”0000” will give a 1 for the first “000” and also after
“0000”
§ output: y is 1 when FSM has detected this sequence; 0 otherwise

x
reset 000 detector y
CLK

13
Example 1: Input and Output
¢ Example input (x) and output (y)
¢ Important: the value of x matters on the positive clock edge

CLK

“saw 0” “saw 1” “saw 00” “saw 000”

“saw 00” “saw 0” “saw 000” “saw 1”
14
State Transition Diagram: Step 1
(partial diagram)
¢ Best approach: start with the reset 0
reset state, then fill in the
obvious states and transitions A/0 B/0

¢ Here we can see that 000 will

give us a 1 on the output! 0
§ A good start

D/1 C/0

0
15
State Transition Diagram: Step 2
(partial diagram)
¢ Instead of arbitrary letters (A, B, …), reset 0
let’s use names that mean
something noZero/
saw0/0
0

¢ “saw000” means the FSM saw

three zeros, etc. 0

¢ “noZero” means the most recent

input was not a 0 saw000/
saw00/0
1

0 16
State Transition Diagram: Step 3
(partial diagram)
¢ What happens if we keep getting 0s? reset 0
§ Well, 0000 still means we have seen
three 0s in a row… noZero/
saw0/0
0

¢ So, we stay in saw000

0

saw000/
saw00/0
1
0

0 17
 State Transition Diagram: Step 4
¢ What happens when we get a 1? reset 0
§ Go back to noZero
noZero/
saw0/0
0 1
¢ Are we done?
§ Looks like it! 1
§ Always check that a “0” arrow and a “1”
arrow starts in every state 0
§ Note: if your FSM has n input bits, then 1 1
each state has 2n out-edges
saw000/
saw00/0
1
0

0 18
 State Table
reset 0 current input next output
state state
noZero/
saw0/0 noZero 0 saw0 0
0 1
noZero 1 noZero 0
1
saw0 0 saw00 0
0
saw0 1 noZero 0
1 1
saw00 0 saw000 0
saw000/ saw00 1 noZero 0
saw00/0
1
saw000 0 saw000 1
0
saw000 1 noZero 1

0
19
FSM Example 2: Counter
¢ Output: 2-bit binary number y=y1y0
¢ Two inputs: INCR and DECR (plus reset and clock)
¢ Functionality:
§ when reset, initialize to y=0
§ if INCR is 1 on clock edge, y increases by 1
§ if DECR is 1 on clock edge, y decreases by 1
§ if INCR and DECR are both 0 or 1, y stays the same
¢ Counter values wrap around, e.g. 11+1 à 00
this means y is a
INCR 2-bit number
DECR
counter y
reset 2

CLK
20
 State Transition Diagram: Step 1 output y1y0 = 01
in this state
reset
10
¢ One state for each output value
s0/00 s1/01
¢ Output values labeled as y1y0

¢ Arrows are labeled with (incr, decr) 10

§ E.g. arrow with “10” shows the transition if 10
incr=1 and decr=0

¢ Let’s start with just the incr arrows here s3/11 s2/10

10
take this transition if 21
incr=1 and decr=0
State Transition Diagram: Step 2
¢ Now, let’s add the decrement reset
10
arrows (01)

s0/00 s1/01
¢ Are we done now?
§ Well, I do see two arrows coming out
of each state… 01
§ But here we have 2 input bits, so we 01 01 10
10
need 22=4 transitions
01
¢ We still need arrows for 00 and
s3/11 s2/10
11…

10
22
State Transition Diagram: Step 3
00,11 00,11
¢ If the inputs are 00 or 11, we don’t reset
10
change state

s0/00 s1/01
¢ Arrow labeled “00,11” means
“take this transition if the input is
00 or it is 11” 01
01 01 10
10
01

s3/11 s2/10

10
00,
11
00,11 23
Moore vs. Mealy FSMs
¢ So far, our FSMs have been Moore Machines
§ Another popular style is the Mealy Machine
¢ Only one difference between them:
§ Moore:
inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state
CLK

§ Mealy:

in a Mealy Output outputs

inputs
machine, the Next State Comb. Logic
Comb. Logic
output also current
N N-bit state
register
N

depends on the state

current input
CLK
24
State Diagrams for Mealy Machines
Output outputs
inputs Comb. Logic
Next State
Comb. Logic N N-bit state N
current register
state
CLK

¢ The output of a Mealy machine depends on both the input and the current
state
§ So our state transition diagrams need to indicate the output value on the transition
arrows, not in the states
“If my current state is A and
1/0 my input is 1, then my next
reset
state is B and my output is 0.”

A B 1/1
“If my current state is B and
my input is 1, then my next
0/1 0/0 state is B and my output is 1.” 25
State Tables for Mealy Machines
¢ The output will change based on current state and input:

1/0
reset

A B 1/1

0/1 0/0
current input next output
state state
A 0 A 1
A 1 B 0
B 0 A 0
B 1 B 1 26
Example 3
¢ Build a sequence detector (like example 1) that detects “10” in the input stream
§ Build both Moore and Mealy machines

¢ Moore:
1
1
reset
nothing/
saw1/0
0

0
1 0

0 saw10/1

27
Example 3: Mealy Machine
¢ Mealy machine only needs two
states
1/0
reset
1/0
¢ Why? Because the Mealy
nothing saw1
machine can combine the
Moore Machine’s “saw10” and
0/1
“nothing” states 0/0

¢ Why can we do this? Because

we can now have different
outputs for each transition

28
Example 3: Mealy vs. Moore
¢ Obvious: our Mealy machine has fewer states
§ This is generally true
§ Mealy machines usually need fewer states because they can have more complex output
functions

¢ A less obvious difference:

§ The timing of the Mealy and Moore machines will be slightly different
§ Why? Because the Mealy’s output can react to the input immediately, but the Moore’s
output can only reflect the state
§ (Diagrams next slide)

29
Moore vs. Mealy Timing
Moore Machine Mealy Machine
1
1 1/0
reset reset
nothing/
saw1/0
0 1/0
nothing saw1
0
1 0
0/1
0/0
0 saw10/1

CLK
CLK

x
x

state nothing saw1 nothing

state nothing saw1 saw10
y
y

Moore machine can’t output 1 until Here, Mealy says “Last cycle was 1 and now
30
after state switches to saw10 the input is 0. Therefore I can output 1 now.”
Example 4 (Part 1)
¢ Design a state transition diagram for a Moore-style FSM
with one input x and one output y. (The FSM also has inputs
for a clock and a positive-asserted reset.) Assume that on
each positive clock edge the input x is sampled.

¢ The system detects two different sequences on input x, and

does different things based on which sequence it detects.

¢ (continued on next slide)

31
Example 4 Continued
¢ The sequence 11 represents a “shutdown” command. If the sequence 11 is ever
detected (that is, x was 1 on the two most recent positive clock edges), then the
FSM can never output y = 1. So, if the 11 sequence is detected, then the FSM will
always output y = 0 afterward, regardless of any other inputs that occur later.

¢ If the sequence 11 has never been detected, then the FSM tries to detect the
sequence 001. It will output y = 1 when 001 is detected and y = 0 at all other
times. (Remember, “sequence 001” means that x was 1 on the most recent
positive clock edge, and 0 on the two previous positive clock edges.)

¢ The system should be capable of detecting an overlap between these two

sequences. For example, sequence 0011 would first count as sequence 001, and
then sequence 11.
32
(a) Draw the state transition diagram. Use meaningful names for the state names. (Don’t
just name them A, B, C, etc.)

33
 (b) Complete
omplete the following
the following waveform.
waveform diagram. You may either draw directly on thi
age and include it in your submission, or you can re-draw it.

epeat parts (a) and (b) using a Mealy machine. 34

Example 4 (Continued)
¢ (c) Repeat part (a) using a Mealy machine
¢ (d) Repeat part (b) using your Mealy machine

¢ Try this on your own. I’ll post slides on Brightspace that show the solutions.

35
FSM Implementation
How do we go from this:
1
¢ We understand how to draw a state reset
diagram, and we understand what an
FSM’s hardware looks like A/10 B/00

0
1
¢ But how do we actually implement an 0 0
FSM using combinational logic and
C/11
registers?

¢ Let’s learn the steps To this? 1

using an example inputs
Next State Output
outputs
from earlier
Comb. Logic N N-bit state N Comb. Logic
current register
state
CLK

36
 (a) Circuit diagram (b) Graphic symbol

Quick
FIGURE Note
5.12
Section
About Flip-Flop Types201
5.4 Storage Elements: Flip-Flops
JK flip-flop
¢ Recall (Topic 11) that there are multiple types of flip-flops
hapter 5 Synchronous Sequential Logic
D Flip-Flop JK Flip-Flop T Flip-Flop

J D D Q DJ D T
T

Clk Clk

K Clk Clk Clk Q! KClk Clk Clk

(a) From JK flip-flop (a) Positive-edge (a) Negative-edge

(b) From D flip-flop (c) Graphic symbol

FIGURE
(a) 5.11
FIGURE 5.13
Circuit diagram (b) Graphic symbol
In modern designs, you are unlikely
¢ to ever see anything except D flip-flops
Graphic T
symbol for
flip-flop edge-triggered D flip-flop
¢ We will only discuss building FSMs using D flip-flops
The graphic § symbol forsee
If curious: theexamples
edge-triggered D flip-flop
in book using JK and is shown in Fig. 5.11. It is simi-
T FFs
= 0 (J used
ar to theTsymbol = 0),
= K for thea clock edge
D latch, does for
except not the
change the output. When
arrowhead-like symbol T in 1 (J =ofK = 1),
= front
he lettera Clk,
clockdesignating
edge complements
a dynamic theinput.
output. The
The complementing
dynamic indicatorflip-flop is useful
(>) denotes for design-
the fact 37
ing binary counters.
Step 1: Draw State Diagram
¢ Given the specification, design a state diagram
§ If possible, optimize it by minimizing the number of states

¢ Let’s use this FSM from earlier as an example

(Example 3 Moore machine, “10” detector)
1
1
reset
nothing/
saw1/0
0

0
1 0

0 saw10/1

38
Step 2: State Encoding and Assignment
1
1
reset
¢ Our state diagram uses state names nothing/
saw1/0
0
§ e.g. “nothing, saw1, saw10”
0
1 0
¢ But I can’t store a name in a register!
0 saw10/1
inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state
CLK

¢ Big idea: we need to assign a unique binary number to each state (this is called
state assignment)

¢ State encodings are strategies we can employ to perform state assignment

(more on this later)
39
Step 2 continued
¢ For now, let’s just choose some numbers
§ Later we will discuss different state encoding schemes you can use
1
1
reset
nothing/
saw1/0
0

0
1 0

0 saw10/1

¢ First: How many bits do I need for my states?

§ I have three states… so I need at least 2 bits.

¢ Let’s arbitrarily choose “nothing” = 00; “saw1” = 01; “saw10” = 10.

40
Step 2 Continued
1
reset
1 State Assignment
nothing/
saw1/0
0
nothing 00
0
1 0 saw1 01
saw10 10
0 saw10/1

¢ If my state register is holding 00, this means my system is in state “nothing”, etc.

x
1 Next State Output
Comb. Logic Comb. Logic y
2 2-bit state 2 1
current 2 register
state
CLK

¢ What about if the register is holding 11? Undefined

41
Detailed Hardware Diagram
¢ To illustrate, let’s draw and label:
Q1+ Q1
x D Q

Next State Output

Comb. Logic Comb. Logic y
Q0+ Q0
D Q

CLK

¢ FFs in the middle = 2-bit state register

¢ Q1 and Q0 represent our two-bit state
¢ Q1+ and Q0+ represent our two-bit next state 42
Simplified Drawing
¢ We often omit the feedback lines and just use labels:
Q1+ Q1
x D Q

Q1
Next State Output
Q0 Comb. Logic Comb. Logic y
Q0+ Q0
D Q

implied connections
from Q1 and Q0 on
right of diagram CLK

43
Step 3: Binary-Coded State Table
¢ Previously, our state tables current input next output
state state
used state names:
nothing 0 nothing 0
¢ Now, we can use our state
nothing 1 saw1 0
assignments:
saw1 0 saw10 0
current next
state input state output saw1 1 saw1 0
Q1 Q0 x Q1+ Q0+ y saw10 0 nothing 1
saw10 1 saw1 1
0 0 0 0 0 0
0 0 1 0 1 0 State Assignment
0 1 0 1 0 0 nothing 00
0 1 1 0 1 0 saw1 01
1 0 0 0 0 1 saw10 10
1 0 1 0 1 1
1 1 0 X X X Don’t cares because state 11
1 1 1 X X X isn’t used in this FSM 44
Step 4: Derive and Simplify Boolean Expressions
current next
¢ Use state table to derive Boolean state input state output

expressions for Q1+, Q0+, and y Q1 Q0 x Q1+ Q0+ y

0 0 0 0 0 0
0 0 1 0 1 0
¢ E.g.:
0 1 0 1 0 0
+
Q1 = Q1 · Q0 · x 0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 0 1 1
¢ Can also use minterms 1 1 0 X X X
(also lets us capture don’t cares) 1 1 1 X X X
X
y(Q1 , Q0 , x) = m(4, 5) + d(6, 7)
¢ Can we simplify these expressions? Of course!
45
Step 4 continued:
Q1Q0
¢ Output logic Y: 00 01 11 10
x
0 0 0 X 1 y = Q1
1 0 0 X 1

Q1Q0
Next state logic: Q1+ +
¢
x
00 01 11 10 Q1 = x · Q0
0 0 1 X 0

1 0 0 X 0

Q0+ Q1Q0
00 01 11 10 +
x
0 0 0 X 0
Q0 =x
1 1 1 X 1 46
 y = Q1
Step 5: Draw Circuit Diagram
Q+
1 = x · Q0
¢ Use equations from step 4 Q+
0 =x

x Q1+ Q1
D Q y
Q0

Q0+ Q0
D Q

CLK

¢ What’s missing? Reset! 47

Step 5 continued 1
1
reset
nothing/
¢ What should the FSM do on reset? 0
saw1/0

§ State diagram says go to state “nothing” 0

1 0
§ State assignment tells me state “nothing”
means Q1=0 and Q0=0.
0 saw10/1
§ So: when we reset, we need to clear both FFs:
x Q1+ Q1
D Q y
Q0

Q0+ Q0
D Q

CLK
reset 48
Quick Aside: Reset State
¢ What if we needed to reset to a state with a different encoding?
§ E.g. what if in this FSM, we had to reset to state with code 01?

¢ We would just connect the external reset signal to the set input of the Q0 FF

x
Q1+ Q1 Example where
D Q
we initialize the
Q1 R state to 01
Next State Output
Q0 Comb. Logic Comb. Logic
Q0+ S Q0
D Q

reset CLK
49
Step 6: Check Your Work
¢ Lastly, check that your system works as intended
1
Q1+ Q1 1
x y reset
D Q nothing/
Q0 0
saw1/0

R 0
1 0

Q0+ Q0
D Q 0 saw10/1

CLK
reset

50
Moore vs. Mealy
¢ How would this change with a Mealy machine?
§ Not much!
§ The only real difference: the output logic depends on the input also

1/0
¢ As a quick example, let’s reset
1/0
walk through the Mealy nothing saw1
version of this same example
current next 0/1
0/0 State assignment:
state input state output
”nothing” à Q=0
Q x Q+ y ”saw1” à Q=1
0 0 0 0 Boolean expressions:
0 1 1 0 Q+ = Q · x + Q · x = x
1 0 0 1
y =Q·x
1 1 1 0 51
Mealy Example Circuit Diagram
1/0 State assignment:
reset
1/0 ”nothing” à Q=0
nothing saw1 ”saw1” à Q=1

0/1 Q+ = Q · x + Q · x = x
0/0
y =Q·x

Q+ Q y
x D Q

CLK R

reset
52
Summary: FSM Implementation
How do we go from this:
1
¢ Step 1: Draw State Diagram reset

A/10 B/00
¢ Step 2: State Encoding and Assignment
0
1
¢ Step 3: Draw Binary-Coded State Table 0 0

C/11

¢ Step 4: Derive and Simplify Boolean

Exprs.
1

¢ Step 5: Draw Circuit Diagram

To this?
¢ Step 6: Check inputs
Next State
Comb. Logic N N-bit state N
Output
Comb. Logic outputs
current register
state
CLK

53
Practice Problem
¢ In Example 4 (earlier), we designed this Mealy machine FSM:

¢ Now, implement this FSM, with the

following state encodings:

¢ I will post a PDF with solutions on Piazza after class 54

What Else Can We Do?
¢ State reduction
§ In Step 1, how do we know that our state diagram is the most efficient?
§ Goal: given an FSM’s state diagram, reduce the number of states without changing its input-
output behavior

¢ State encoding and assignment

§ In Step 2, how do I choose my state encoding and assign numbers to each state?
§ Pick a unique binary number for each state
§ Last time, we just chose encoding arbitrarily, but we need to choose more carefully

55
State Reduction
¢ Goal: Given an FSM’s state diagram, reduce the number of states without
changing the FSM’s output
§ That is: the reduced FSM still produces the same output as the original FSM, given the same
input

¢ Why do we care?
§ If we can reduce the states, we can simplify our FSM circuit
§ Fewer states means we can potentially reduce the number of bits in the state register
§ It also can reduce the number of gates in the next state and output logic
§ Surprisingly: this isn’t always true!

56
 State Equivalence 0/0
0/0
a
¢ Two states are equivalent if for every possible 0/0
1/0
input, they have the same output and the same
next state 0/0
0/0
b c
¢ Example: states e and g
1/0
§ If input=0, both output 0 and have next state a 1/0 0/0
§ If input=1, both output 1 and have next state f g d e
§ Therefore, states e and g are equivalent and we can
merge them into a single state (shown on next slide) 1/1 1/1
0/0
f 1/1
¢ Any more? Doesn’t look like it

1/1

FIGURE 5.25 [Figure 5.25 from Mano and Ciletti]

57
State diagram
 232 Chapter 5 Synchronous Sequential Logic
Merged States
us Sequential Logic

0/0 0/0
0/0 0/0
a a
0/0 0/0
1/0 1/0
0/0 0/0
0/0 b c 0/0 b c

1/0 1/0
1/0 0/0 1/0 0/0
g d e g d e

0/0
1/1 1/1
Merge e and
0/0
g 1/1 1/1
0/0
f 1/1
f 1/1

1/1
1/1 58
 232 Chapter 5 Synchronous Sequential Logic
Any More Equivalent States?
0/0
0/0
¢ Perhaps surprisingly… yes: d and f are equivalent a
§ if input=0: next_state = e, output 0 0/0
§ if input=1: next_state = f, output 1 1/0
0/0
0/0 b c
¢ Wait… two slides ago we decided that the only
equivalent states we had were e and g. What 1/0
1/0 0/0
happened? g d e
§ Initially, d’s next state was e and f’s next state was g.
1/1 1/1
§ Now that we merged e and g, this means d and f0/0 are 0/0
also equivalent f 1/1

1/1
59
FIGURE 5.25
 Checking each pair of states for equivalency can be done s
equential Logic a procedure that employs an implication table, which consists
Minimized FSM suspected pair of possible equivalent states. By judicious use
to determine all pairs of equivalent states in a state table.
0/0
0/0
a 0/0
0/0
1/0 a
0/0 0/0
0/0 1/0
0/0 b c
0/0
e b c
1/0
1/0 0/0 1/1 1/0
g 0/0
d e
d 1/0
0/0
1/1 1/1
0/0 Merge d and f
1/1
f 1/1
FIGURE 5.26
Reduced state diagram
1/1 60
Next: State Encoding and Assignment
1
1
reset
¢ Our state diagrams use state names nothing/
saw1/0
0
§ e.g. “nothing, saw1, saw10”
0
1 0
¢ But I can’t store a name in a register!
0 saw10/1

inputs
Next State Output
Comb. Logic Comb. Logic outputs
N N-bit state N
current register
state
CLK

¢ For a circuit with n states, the state encoding must use at least dlog2 (n)e bits
§ Example: n=5 states à dlog2 (5)e = d2.32e =3 bits
§ Put another way: m bits = up to 2m states

61
Binary Encoded State Assignment
¢ “Binary encoded” à simply use a unique binary number for each state. Use as
few bits as possible
00 01
§ One option: simply count up as you go 1
1
through states reset
nothing/
saw1/0
0

0
1 0

¢ But we can pick many different assignments 0 saw10/1

10
§ 00, 01, 10 or 11, 10, 01, or …
§ each choice will result in different next state and output logic
§ how do we pick which to use?

62
One-Hot State Encoding
¢ We don’t always want to use the fewest state bits as possible.

¢ One-Hot State Encoding uses a single bit for each state.

§ E.g.: a 3-bit FSM’s states would be encoded 100, 010, and 001
§ 5-bit: 10000, 01000, 00100, 00010, and 00001
§ At any time, only a single state bit may be 1

¢ Why? It might make the next state and output logic much simpler
§ You only need to include a single bit to check if you are in a given state

¢ Drawback: larger state register! One bit per state

63
Many Choices in State Assignment
¢ There are many ways you can assign encodings to states

¢ Choice can affect the cost of the next state and output logic.

¢ Problem: there are a huge number of possibilities. Ex:

§ Imagine you have a 4-state FSM and you want to assign state encodings 00, 01,
10, and 11 à 4! = 24 possible choices
§ 8-state FSM: 8! = 40,320 choices
§ 32-state FSM: 32! = 2.6 x 1035 choices

¢ If you want the best choice, how do you find it?

§ This is a hard problem!
§ Computer algorithms try to find efficient choices, but there is no way to
guarantee you found the optimal choice for large FSMs
64
So How Do You Pick the Best State Encoding?
¢ Option 1: Trial and error by hand
§ Pick an encoding, write and simplify Boolean equations
§ Slow and tedious! Remember: n-states gives n! choices
§ (Don’t really try all n! options)
¢ Option 2: State Maps
§ State maps are sort of like K-Maps for state encoding
§ Big idea: lets you visualize adjacencies

¢ Option 3: Some simpler heuristics

§ “Minimum bit change” à count how many bits need to change for each state transition
§ Use this to try to find efficient encodings

¢ Option 4: Use a computer

§ Take ESE 382
65