Microelectronics Circuits And Systems Select

Proceedings Of Micro2021 Abhijit Biswas download

https://ebookbell.com/product/microelectronics-circuits-and-
systems-select-proceedings-of-micro2021-abhijit-biswas-50688922

Explore and download more ebooks at ebookbell.com

Here are some recommended products that we believe you will be
interested in. You can click the link to download.

Microelectronics Circuits And Systems Select Proceedings Of 7th

International Conference On Micro2020 Lecture Notes In Electrical
Engineering 755 1st Ed 2021

https://ebookbell.com/product/microelectronics-circuits-and-systems-
select-proceedings-of-7th-international-conference-on-
micro2020-lecture-notes-in-electrical-engineering-755-1st-
ed-2021-34491624

Microelectronic Devices Circuits And Systems Third International

Conference Icmdcs 2022 Vellore India August 1113 2022 Revised Selected
Papers V Arunachalam

https://ebookbell.com/product/microelectronic-devices-circuits-and-
systems-third-international-conference-icmdcs-2022-vellore-india-
august-1113-2022-revised-selected-papers-v-arunachalam-48733948

Microelectronic Devices Circuits And Systems Second International

Conference Icmdcs 2021 Vellore India February 1113 2021 Revised
Selected Papers 1st Edition V Arunachalam Editor

https://ebookbell.com/product/microelectronic-devices-circuits-and-
systems-second-international-conference-icmdcs-2021-vellore-india-
february-1113-2021-revised-selected-papers-1st-edition-v-arunachalam-
editor-33985394

Microelectronic Systems Circuits Systems And Applications 2011 Albert

Heuberger Editor

https://ebookbell.com/product/microelectronic-systems-circuits-
systems-and-applications-2011-albert-heuberger-editor-23460854
Microelectronic Systems Circuits Systems And Applications Albert
Heuberger Gnter Elst Randolf Hanke

https://ebookbell.com/product/microelectronic-systems-circuits-
systems-and-applications-albert-heuberger-gnter-elst-randolf-
hanke-34361238

Microelectronic Devices And Circuits 2006 Electronic Edition Clifton G

Fonstad

https://ebookbell.com/product/microelectronic-devices-and-
circuits-2006-electronic-edition-clifton-g-fonstad-2218790

Microelectronic Circuits Analysis And Design 2nd Edition 2nd Muhammad

H Rashid

https://ebookbell.com/product/microelectronic-circuits-analysis-and-
design-2nd-edition-2nd-muhammad-h-rashid-2394650

Microelectronics Circuit Analysis And Design Fourth Edition 4th Donald

A Neamen

https://ebookbell.com/product/microelectronics-circuit-analysis-and-
design-fourth-edition-4th-donald-a-neamen-2433892

Microelectronic Circuits Theory And Applications Adel S Sedra

https://ebookbell.com/product/microelectronic-circuits-theory-and-
applications-adel-s-sedra-5494228
Lecture Notes in Electrical Engineering 976

Abhijit Biswas
Aminul Islam
Rishu Chaujar
Olga Jaksic Editors

Microelectronics,
Circuits and
Systems
Select Proceedings of Micro2021
Lecture Notes in Electrical Engineering

Volume 976

Series Editors

Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli
Federico II, Naples, Italy
Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán,
Mexico
Bijaya Ketan Panigrahi, Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India
Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, Munich, Germany
Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China
Shanben Chen, Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China
Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore, Singapore,
Singapore
Rüdiger Dillmann, Humanoids and Intelligent Systems Laboratory, Karlsruhe Institute for Technology, Karlsruhe,
Germany
Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China
Gianluigi Ferrari, Università di Parma, Parma, Italy
Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid,
Madrid, Spain
Sandra Hirche, Department of Electrical Engineering and Information Science, Technische Universität München,
Munich, Germany
Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA, USA
Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Janusz Kacprzyk, Systems Research Institute, Polish Academy of Sciences, Warsaw, Poland
Alaa Khamis, German University in Egypt El Tagamoa El Khames, New Cairo City, Egypt
Torsten Kroeger, Stanford University, Stanford, CA, USA
Yong Li, Hunan University, Changsha, Hunan, China
Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA
Ferran Martín, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra, Barcelona,
Spain
Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore
Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany
Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA
Sebastian Möller, Quality and Usability Laboratory, TU Berlin, Berlin, Germany
Subhas Mukhopadhyay, School of Engineering and Advanced Technology, Massey University, Palmerston North,
Manawatu-Wanganui, New Zealand
Cun-Zheng Ning, Electrical Engineering, Arizona State University, Tempe, AZ, USA
Toyoaki Nishida, Graduate School of Informatics, Kyoto University, Kyoto, Japan
Luca Oneto, Department of Informatics, Bioengineering, Robotics and Systems Engineering, University of Genova,
Genova, Genova, Italy
Federica Pascucci, Dipartimento di Ingegneria, Università degli Studi Roma Tre, Roma, Italy
Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China
Gan Woon Seng, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore,
Singapore
Joachim Speidel, Institute of Telecommunications, Universität Stuttgart, Stuttgart, Germany
Germano Veiga, Campus da FEUP, INESC Porto, Porto, Portugal
Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Beijing, China
Walter Zamboni, DIEM—Università degli studi di Salerno, Fisciano, Salerno, Italy
Junjie James Zhang, Charlotte, NC, USA
The book series Lecture Notes in Electrical Engineering (LNEE) publishes the latest
developments in Electrical Engineering—quickly, informally and in high quality.
While original research reported in proceedings and monographs has traditionally
formed the core of LNEE, we also encourage authors to submit books devoted
to supporting student education and professional training in the various fields and
applications areas of electrical engineering. The series cover classical and emerging
topics concerning:
. Communication Engineering, Information Theory and Networks
. Electronics Engineering and Microelectronics
. Signal, Image and Speech Processing
. Wireless and Mobile Communication
. Circuits and Systems
. Energy Systems, Power Electronics and Electrical Machines
. Electro-optical Engineering
. Instrumentation Engineering
. Avionics Engineering
. Control Systems
. Internet-of-Things and Cybersecurity
. Biomedical Devices, MEMS and NEMS

For general information about this book series, comments or suggestions, please
contact [email protected].
To submit a proposal or request further information, please contact the Publishing
Editor in your country:
China
Jasmine Dou, Editor ([email protected])
India, Japan, Rest of Asia
Swati Meherishi, Editorial Director ([email protected])
Southeast Asia, Australia, New Zealand
Ramesh Nath Premnath, Editor ([email protected])
USA, Canada
Michael Luby, Senior Editor ([email protected])
All other Countries
Leontina Di Cecco, Senior Editor ([email protected])
** This series is indexed by EI Compendex and Scopus databases. **
Abhijit Biswas · Aminul Islam · Rishu Chaujar ·
Olga Jaksic
Editors

Microelectronics, Circuits
and Systems
Select Proceedings of Micro2021
Editors
Abhijit Biswas Aminul Islam
Department of Radio Physics Department of Electronics
and Electronics and Communication Engineering
University of Calcutta Birla Institute of Technology
Kolkata, West Bengal, India Ranchi, Jharkhand, India

Rishu Chaujar Olga Jaksic

Department of Engineering Physics Institute of Chemistry, Technology
Delhi Technological University and Metallurgy
New Delhi, India University of Belgrade
Belgrade, Serbia

ISSN 1876-1100 ISSN 1876-1119 (electronic)

Lecture Notes in Electrical Engineering
ISBN 978-981-99-0411-2 ISBN 978-981-99-0412-9 (eBook)
https://doi.org/10.1007/978-981-99-0412-9

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature
Singapore Pte Ltd. 2023
This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether
the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse
of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and
transmission or information storage and retrieval, electronic adaptation, computer software, or by similar
or dissimilar methodology now known or hereafter developed.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication
does not imply, even in the absence of a specific statement, that such names are exempt from the relevant
protective laws and regulations and therefore free for general use.
The publisher, the authors, and the editors are safe to assume that the advice and information in this book
are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or
the editors give a warranty, expressed or implied, with respect to the material contained herein or for any
errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional
claims in published maps and institutional affiliations.

This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd.
The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721,
Singapore
Contents

Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant

12T SRAM Cell for Deep Space Applications . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ravi Teja Yekula, Monalisa Pandey, and Aminul Islam
Majority PFET-Based Radiation Tolerant Static Random Access
Memory Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Monika Rani, G. Sai Namith, Shashank Kumar Dubey, and Aminul Islam
Comparison of Snapback Phenomenon and Physics in Bottom
and Top Body Contact NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pragati Singh, Niladri Pratap Maity, Rudra Sankar Dhar,
and Srimanta Baishya
A Review on Optimal Power Flow Problem . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Naveen Kumar, Ramesh Kumar, and Ram Kumar
A Study on Zn/Cu-Based Pandan Leaf (Pandanus Amaryllifolius)
Electrochemical Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Salman Rahman Rasel, K. A. Khan, Md. Sayed Hossain,
Shahinul Islam, M. Hazrat Ali, and Rajada Khatun
Gate All Around 22 nm SOI Schottky Barrier MOSFET with High
I ON /I OFF Current Ratio for Low-Power Digital and Analog Circuit
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Amit Saxena, R. K. Sharma, Manoj Kumar, and R. S. Gupta
Studies on Synthesis, Characterization, and Monitoring of Ag NPs
for Power Production Using Tomato . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Farhana Islam, K. A. Khan, Md. Sayed Hossain,
Salman Rahman Rasel, and Shirin Akter
Man–Machine Interface in Designing Through Simulation in Solar
Power Development in India . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Shreya Karmakar and Pradip Kumar Sadhu

v
vi Contents

Optical Cryptography Using Reversible Logic Gate . . . . . . . . . . . . . . . . . . . 99

Goutam Kumar Maity, Tarak Nath Bera, Aranya Manna,
Pradip Ghosh, and Subhadipta Mukhopadhyay
Red Spinach-A New and Innovative Power Source . . . . . . . . . . . . . . . . . . . . 113
K. A. Khan, Farhana Islam, Md. Sayed Hossain,
Salman Rahman Rasel, and Md. Ohiduzzaman
Heart Disease Risk Prediction Using Supervised Machine Learning
Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Madhumita Pal, Smita Parija, and Ranjan K. Mohapatra
Implementing Machine Learning Algorithms for Predicting Roof
Fall Statistics in UG Coal Mines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Jitendra Pramanik, Singam Jayanthu, Abhaya Kumar Samal,
and Surendra Kumar Dogra
Synthesis, Characterizations of Silver Nanoparticles (AgNPs)
and Monitoring for Power Production Using Drumstick Leaves . . . . . . . . 145
K. A. Khan, Mohammad Tofazzal Haider, Md. Sayed Hossain,
and Salman Rahman Rasel
Extract of Green Chili—A New Source of Electricity . . . . . . . . . . . . . . . . . . 159
Md. Ohiduzzaman, K. A. Khan, Shahinul Islam, Md. Sayed Hossain,
and Salman Rahman Rasel
Graphene-Based Biosensor: Physics and Technology . . . . . . . . . . . . . . . . . . 171
Rupanwita Das Mahapatra, Sulagna Chaterjee, and Moumita Mukherjee
Graphene Sensors for Application in Defence and Healthcare
Sector: Present Trends and Future Direction . . . . . . . . . . . . . . . . . . . . . . . . . 183
Rupanwita Das Mahapatra, Sulagna Chaterjee, and Moumita Mukherjee
Design and Simulation of a High Power LED Bulbs with Different
Array of Fins in Passive Mode of Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Nitin Namdeo Pawar and Kiran K. Jadhao
An Experimental Investigation of Production of Plastic Fuel
and Blend with Diesel Fuel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Nitin Namdeo Pawar and Kiran K. Jadhao
Bivariate Frequency Analysis of Drought Using Copulas
for Telangana Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Ashutosh Chaturvedi and Gore Vikas Sudam
Influence of AlN Spacer Layer on SiN-Passivated AlGaN/GaN
HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Santashraya Prasad and A. Islam
Contents vii

Design and Analysis of Fractal Type MIMO Radiator

for the Applications of Sub 6-GHz 5G Systems . . . . . . . . . . . . . . . . . . . . . . . 243
K. Vasu Babu, R. Tejaswini, N. Sowjanya, B. Sujitha, T. Vineela,
and B. Durga Prasad
Histopathology Cancer Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Kolluri Paul Wilson, Muntala Srinivasa Reddy,
Suyadevara Chakravarthy Karthik, Venkata Vamsi Kolluru Anudeep,
and Kande Giri Babu
Contingency Analysis Study for a 39 Bus System in a Micro-grid . . . . . . . 263
Dipu Mistry, Bishaljit Paul, and Chandan Kumar Chanda
Applications of Green Energy Storage Systems Using PKL Battery . . . . . 275
K. A. Khan, Md. Sayed Hossain, Salman Rahman Rasel,
and Mehedi Hasan
Comparative and Robustness Study of 3-Bit Adder . . . . . . . . . . . . . . . . . . . 287
Md. Faizan Khan, Subham Chowdhury, Ravi Kumar,
Shashank Kumar Dubey, Santashraya Prasad, and Aminul Islam
Brain Tumor Detection and Classification from MRI Images Using
Cascaded Deep Neural Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Pallavi Priyadarshini, Abdul Kayom Md. Khairuzzaman,
and Priyadarshi Kanungo
Development of Low-Cost Intelligent Alert System
for Underground Coal Mines Using GSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Vijaya Bhasker Reddy, Suneetha Ghatikanti, and Falguni Sarkar
Analysis of an IoT-Based SDN Smart Health Monitoring System . . . . . . . 325
M. Tejeswara Kumar, N. V. R. Vikram G, and Punyaban Patel
Internet of Things in Agriculture Industry: Implementation,
Applications, Challenges and Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Kiran Jot Singh, Divneet Singh Kapoor, Anshul Sharma,
Khushal Thakur, Tanishq Bajaj, Ashwin Tomar, Sparsh Mittal,
Baljap Singh, and Raghav Agarwal
Assessing Dynamic RAM Technology with Contrast Era
of Megabit, Gigabit, and Merged Dynamic RAM/Logic . . . . . . . . . . . . . . . 349
Sanchit Yadav, Ritika Rattan, and Tripti Sharma
Analysis of Computational Complexity in Interference Mitigation
with 3D MIMO Beamforming Techniques in 5G Networks . . . . . . . . . . . . 361
Ashutosh Tripathi and Ranjeet Yadav
Emotion Recognition: A Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Bhavesh Gandhi, Sandeep Saxena, and Pulkit Jain
viii Contents

Smart Shirt: A Leap into Technological Fashion . . . . . . . . . . . . . . . . . . . . . . 381

Alok Barwal and Pulkit Jain
Design of Domino Logic-Based NOR Gate Circuit for Reduction
of Charge Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Saumya Srivastava and Sangeeta Shekhawat
Design of Dynamic Logic Circuit-Based NOR Gate for Low Power . . . . . 399
Saumya Srivastava and Sangeeta Shekhawat
Modeling of MQW Transistor Laser Using Group IV Materials . . . . . . . . 405
Jaspinder Kaur and Rikmantra Basu
Driver Drowsiness Detection Using OpenCV and Machine
Learning Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
K. Radhika, N. V. Krishna Rao, N. Shalini, V. Divya Vani,
and B. Geetavani
The Power Density of PKL, Aloe Vera, Myrobalan, Lemon,
and Tomato Electrochemical Cell—An Observation . . . . . . . . . . . . . . . . . . 423
K. A. Khan, Md. Sayed Hossain, Salman Rahman Rasel,
and Mehedi Hasan
Modeling and Design of FPGA-Based Power Quality Analyzer . . . . . . . . . 433
M. Balasubbareddy, Kondapalli Venkata Sri Ram, and Ravindra Sangu
Design of Hardware Unified Power Quality Conditioner to Mitigate
Sag and Swell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Mallala Balasubbareddy and Ravindra Sangu
Complementing Biometric Authentication System with Cognitive
Skills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
B. Sindhu and B. Kezia Rani
An Interactive Method to Predict Thyroid Disease . . . . . . . . . . . . . . . . . . . . 467
Sai Jyothi Bolla, Kalavathi Alla, and Bhanu Supraja Grandhe
A Brief Study of Designing a 10KWP Grid Connected Photovolatic
System Using PVSYST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Amrita Chanda, Sagar Bera, Ramanuj Bhowmick, and Susovan Dutta
Automatic Plant Watering System Using Moisture Sensor
and Arduino Uno_An Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . 485
Dhanaraju Athina, Kolli Vittal, Swapna Revuri, Kulsum Shireen,
and Karnati Keerthi
Lung Cancer Detection Using Computer-Aided Diagnosis (CAD) . . . . . . 501
Ashok Kumar Nanduri, Jeevan Ratnakar Kondru, M. Rambhupal,
and Nutalapati Ashok
Contents ix

Deep Learning Based Real-Time Object Detection on Jetson Nano

Embedded GPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Pardha Saradhi Mittapalli, M. R. N. Tagore, Pulagam Ammi Reddy,
Giri Babu Kande, and Y. Mallikarjuna Reddy
Density-Based Scanning to Provide Effective Medical Emergency
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Sai Jyothi Bolla, C. M. Suvarna Varma, and G. Shireesha
Phytochemicals as an Active Pharmaceutical Ingredient of Ocimum
Sanctum and Azadirachta Indica:A Theoretical Screening Study . . . . . . . 535
Sourav Patanayak, Grishma Ninave, Moumita Mukherjee,
Jayanta Mukhopadhyay, V. Ragavendran, B. B. Paira,
Sukhendu Samajdar, Saumya Dasgupta, Debosreeta Bose,
and Madhumita Mukhopadhyay
DAAM: WSN Data Aggregation Using Enhanced AI and ML
Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Sanjay Gandhi Gundabatini, Suresh Babu Kolluru,
C. H. Vijayananda Ratnam, and N. Nalini Krupa
Dual-Strip Flag Microstrip Patch Antenna for Millimeter-Wave
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Purnima K. Sharma, Dinesh Sharma, E. Kusuma Kumari,
V. S. D. Rekha, and Vivek Garg
A Cost-Effective Tracking and Health Monitoring System
for Suspected COVID-19 Patient in Quarantine . . . . . . . . . . . . . . . . . . . . . . 569
Jhilam Jana, Sayan Tripathi, Akash Bhattacharya,
Ritesh Sur Chowdhury, Deep Ranjan, and Jaydeb Bhaumik
About the Editors

Abhijit Biswas received his B.Tech., M.Tech., and

Ph.D. (Tech.) degrees from the University of Calcutta. In
1999, he joined the University of Calcutta as a lecturer in
the Department of Radio Physics and Electronics where
he is currently working as a professor. He was asso-
ciated with Jadavpur University as a lecturer in Elec-
tronics Science during 1997–1999 and as a reader in
the Department of Electronics and Telecommunication
Engineering during 2006–2008. His research interests
include semiconductor physics, modeling, simulation,
and characterization of electronic, optoelectronic and
photovoltaic devices and circuits. He has published 81
technical papers in international SCI journals and over
130 papers in international conferences/workshops. He
produced 11 Ph.D. scholars under his supervision and
conducted many research projects funded by Govt. of
India. He received UGC research award during 2012–
2014. He served as a Guest Editor of Microsystem
Technologies, Springer several times, and acted as a
reviewer of a large number of SCI journals including
IEEE Electron Device Letters, IEEE Transactions on
Electron Devices, Superlattices and Microstructures,
Microelectronics Reliability, and many more.

xi
xii About the Editors

Aminul Islam received the B.Tech. in Computer Engi-

neering from IE(I), in 2001, M.Tech. in ECE from BIT,
Mesra, in 2006, and a Ph.D. degree from Aligarh Muslim
University, India, in 2013. Until November 2006, he
was with Indian Air Force. Since November 2006, he
has been in the Department of ECE, BIT, where he is
currently an associate professor. His research interest
area is VLSI/CAD design for emerging technologies.
He has over 276 journal publications, 135 conference
papers, 32 book chapters, and 2 Indian patents published
to his credit.

Rishu Chaujar is presently working as a professor in

the Department of Applied Physics and Associate Dean
(Acad-PG), Delhi Technological University (DTU). Her
doctoral research involves modeling, design, and simula-
tion of Sub-100 nm Grooved Gate/Concave MOSFETs,
FinFETs, Tunnel FETs, Nanowires, HEMT structures
modeling for high-performance sensing, biomedical,
and wireless applications. She has over 305 papers in
various reputed international and national journals and
conferences. She has supervised 7 Ph.D. students, and
08 scholars are currently working with her. She has
supervised several national and international research
projects. She is a reviewer of various reputed inter-
national journals. She is a fellow of IETE, a life
member of NASI, and a member of various international
professional societies.

Olga Jaksic received her Dipl.-Ing. and her Mag. Sci.

degree in electrical engineering from the School of Elec-
trical Engineering, University of Belgrade. She received
her Ph.D. degree in physical chemistry from the Faculty
of Physical Chemistry, University of Belgrade. Since
1993, she has been with the Institute of Chemistry,
Technology and Metallurgy, University of Belgrade,
currently as an associate research professor. She has
been working with noise and fluctuations in MEMS
sensors and their characterization; thermopile devices;
resonant and micro-cantilever-based MEMS structures;
photonic crystals; plasmonics, metamaterials, and 2D
materials. Her main research interests include stochastic
processes and random phenomena. She is a founding
member of the Optical Society of Serbia, a member of
About the Editors xiii

the Society of Physical Chemists of Serbia, an edito-

rial board member of several journals, and a reviewer of
several SCI journals. She authored 135 publications in
journals and conferences of international repute.
Highly Reliable PMOS Pass
Transistor-Based Radiation Tolerant 12T
SRAM Cell for Deep Space Applications

Ravi Teja Yekula, Monalisa Pandey, and Aminul Islam

Abstract This paper proposes a highly reliable PMOS pass transistor-based

radiation-tolerant 12T (PPTRT 12T) SRAM cell for deep-space applications. The
proposed SRAM cell achieves 17.88% improvement in critical charge (QC ), 2.19×
improvement in read static noise margin (RSNM), and 1.24× improvement in read
access time (T RA ) as compared to QUCCE 10T SRAM cell at the expense of marginal
(1.04×) degradation in write access time (T WA ). The read operation of the proposed
circuit is highly stable (read upset proof) because of its higher RSNM. It is also
highly reliable in radiation environments because of its higher QC . The theoretical
design of the proposed SRAM cell has been validated with extensive simulations on
PrimeSim HSPICE using 16-nm high-performance CMOS technology.

Keywords RSNM · Critical charge · Access time · SET · SEU

1 Introduction

Due to technology scaling, there is a decrease in supply voltage and other node capac-
itances for controlling the power consumption in ICs, but it increases the chance of
being vulnerable to the SET (single event transient) which can eventually increase
the probability of single event upset (SEU), which are also known as ‘Soft Errors’
[1–4]. SETs are caused due to Cosmic rays (neutrons), alpha particles originating
from extra-terrestrial rays, and packaging materials, respectively [5]. These particles
can either directly or indirectly ionize (generate electron-hole pairs) the semicon-
ductor materials like silicon substrates used in the ICs. The generated electron/hole
drifts toward the reverse-biased drain diffusion regions of NMOS/PMOS transistors
causing an increase in charge. If this extra charge is gained by the sensitive nodes it
causes voltage transients and if the amplitude and time duration of these transients

R. T. Yekula · M. Pandey · A. Islam (B)

Department of ECE, BIT, Mesra, Ranchi, Jharkhand 835215, India
e-mail: [email protected]
R. T. Yekula
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 1
A. Biswas et al. (eds.), Microelectronics, Circuits and Systems, Lecture Notes in Electrical
Engineering 976, https://doi.org/10.1007/978-981-99-0412-9_1
2 R. T. Yekula et al.

are strong enough they lead to change in the state of the node. This phenomenon is
termed as single event upset or Soft Error [5, 6].
These do not cause permanent damage, hence, they are also regarded as temporary
errors but they can potentially cause a malfunction in the circuit and, hence, protec-
tion is needed against such SET [6]. Aggressive technology scaling has placed the
transistors close to each other and due to the less spacing between transistors, more
than one transistor can be affected in a single event because of charge sharing causing
Single Event Multi-Node Upset (SEMNU), which can easily cause a malfunction in
the circuit. These SEUs are possible in both logic and memory circuits but memory
circuits are more susceptible due to their compact design, dense packing, and lack of
recovery or error masking mechanisms [7]. Various alternate circuits were proposed
in place of the standard 6T SRAM cell to have protection from SEU.
However, a differential read Quarto 10T cell was introduced in [8] which is much
robust to radiation strike compared to 6T SRAM and 1/2 rate ECC protected 6T.
Taking the time penalty also into account Quarto 10T is preferred, but the high write
failure probability is a major concern for Quarto 10T SRAM cells [8]. Therefore,
a write enhanced Quarto 12T SRAM cell was introduced to boost the write ability
compared to the Quarto 10T SRAM but with a tradeoff of large area overhead.
Later, NMOS stacked 10T SRAM cell (NS10T) and PMOS stacked 10T SRAM cell
(PS10T) were introduced but they provide only partial protection against the SEU,
i.e., either a 0–1 or a 1–0 transient is only protected according to whether the NMOS
or PMOS is used in the stacking structure [9].
In view of the above issues, this paper proposes a 12T SRAM cell, which uses
a non-differential read technique to provide a shorter read access time and higher
RSNM (read static noise margin), which makes it read upset tolerant in addition to
single event upset tolerant at the cost of slightly increased write delay.
The rest of the paper is organized as follows. Section 2 briefly describes the
prior work. Section 3 presents the proposed SRAM cell. Section 4 consists of the
simulation of SRAM cells. Section 5 provides the conclusion.

2 Prior Work

The QUCCE 10T SRAM cell proposed in [10] has two storage nodes named Q and
QN in addition to its internal node pair A and B. Each node is present between a
series of PMOS and NMOS transistors as shown in Fig. 1. Both the bit lines, namely
BL and BLB connect the two storage nodes Q and QN via NMOS access transistors
N5 and N6, respectively. These access transistors are controlled through word line
WL which is connected to the gate of these two access transistors. Considering ‘0’
is stored in the cell, the node values are as follows—A is ‘1’, Q is ‘0’, QN is ‘1’, and
B is ‘0’, respectively. With these the hold, read, and write operations are explained
as follows:
Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant 12T … 3

Fig. 1 Quadruple
cross-coupled storage cells
(QUCCE) 10T SRAM cell
[10]

2.1 Hold Operation

In this mode, the WL is grounded making sure the N5 and N6 access transistor are
switched off, the transistors P1, N2, P3, and N4 are in ‘ON’ state and N1, P2, N3,
and P4 are in ‘OFF’ state.

2.2 Read Operation

In this operation, initially both the bit lines BL and BLB are pre-charged to supply
voltage V DD and then WL is made high switching ON the access transistors N5 and
N6 but only N2 is in ON state and N3 is in OFF state, hence, there is a discharge
path only for BL through N5 and N2 leading to a voltage difference between BL
and BLB. With the help of a sense amplifier, read operation is carried out. During
read operation zero storing node, Q gets disturbed from its state due to the voltage
division between the resistance of N5/6 and N2/3. While the discharge of BL a
voltage bump is developed at Q, which should not be high enough to flip the state of
the cell. Hence, the N2/3 should be sized stronger than the N5/6, i.e., the cell ratio
(W N2 /L N2 )/(W N5 /L N5 ) or (W N3 /L N3 )/(W N6 /L N6 ) must be chosen properly to avoid
flipping of the cell and ensure proper read operation.

2.3 Write Operation

In this operation, for writing an opposite value to the already stored value, initially
the bit line associated with the node storing ‘1’ is driven to GND and the other bit
line is driven to V DD . That is, since QN was previously storing ‘1’, hence, the BLB
is grounded and BL is driven to V DD ; then WL is made high switching ON both
the access transistors. Therefore, the QN node storing ‘1’ is pulled down by BLB
4 R. T. Yekula et al.

through transistor N6 such that the potential at QN falls below the threshold voltage
(V th ) of N2 putting it in an OFF state; on the other side the BL tries to pull up the
potential of storage node Q and the cross-coupled structure of N2 and N3 transistors
amplify the difference between Q and QN aiding in flipping the stored voltages. For
this to happen, we should ensure N6 (N5) transistor is stronger compared to the
P3 (P2) so the pull-up ratio (W P2 /L P2 )/(W N5 /L N5 ) or (W P3 /L P3 )/(W N6 /L N6 ) should
be chosen properly. The cross-coupled structure of P1 (P3) and P2 (P4) helps in
amplifying the difference between Q (QN) and A (B) [10]. To pull up the potential
of node, B the P4 should be stronger than the N4 and, hence, the pull-up ratio, i.e.,
(W P4 /L P4 )/(W N4 /L N4 ) or (W P1 /L P1 )/(W N1 /L N1 ) should be chosen adequately. Since
the mobility of holes is lesser than that of free electrons a larger PMOS is required
here for proper write operation this causes more area overhead [10]. After the write
operation, the transistors P2, N3, P4, and N1 are ‘ON’ and the transistors N4, P1,
N2, and P3 are in ‘OFF’ state and, hence, the contents of the nodes are flipped to A
is ‘0’, Q is ‘1’, QN is ‘0’, and B is ‘1’, respectively.

3 Proposed PMOS Pass Transistor-Based Radiation

Tolerant 12T

3.1 Cell Structure and Behavior

The proposed circuit, as shown in Fig. 2, is similar to the QUCCE 10T with the
exception that PMOS transistors (P5 and P6) are used as access transistors instead
of NMOS access transistors (N5 and N6) and a separate NMOS stack containing
two NMOS transistors are used to carry out the read operation separately without
influencing the present state of the cell.
The Hold and Write operations are similar to that of QUCCE 10T SRAM cell as
explained in Sect. 2, only the read operation differs from that of the QUCCE 10T
SRAM and it is as follows:

Fig. 2 PMOS pass transistor-based radiation-tolerant 12T (PPTRT 12T) SRAM cell
Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant 12T … 5

Read Operation is carried out with help of the NMOS stack connected to RBL,
which is pre-charged before the read operation is initiated. To perform read operation,
read line (RL) is activated. The lower NMOS in the stack is already in ON state due to
storage node QN, which has been assumed to hold a ‘1’ previously. Therefore, as soon
as the read line (RL) is raised high the read bit line (RBL) starts discharging through
the NMOS stack, and a sense amplifier (not shown) senses the decrease in RBL
with respect to a reference voltage. The non-differential read operation is completed
once a potential difference between the read bit line (RBL) and the reference voltage
becomes 50-mV because a sense amplifier can decipher the stored content only if
the potential difference is at least 50-mV [10]. The stacked NMOS sizing is done
conveniently as they do not influence the cell and there is no risk of flipping the
contents of the cell [10]. Hence, a higher value of RSNM is achievable, which makes
the cell robust and stable in the presence of noise thereby making the circuit highly
reliable and robust against read upset.

3.2 Cell Sizing

The transistors in a cell are to be sized in such a way that the cell content is not altered
during a read operation and the cell content is flipped during a write operation.
Phrased in a different way—read upset and write failure should not occur due to
sizing problems. Unlike QUCCE 10T, the proposed cell state is not influenced in a
read operation, hence, only write operation is considered for cell sizing. The pull-up
ratio (W P2 /L P2 )/(W P5 /L P5 ) or (W P3 /L P3 )/(W P6 /L P6 ) for a stable write operation is set
as 2 and the pull-up ratio (W P4 /L P4 )/(W N4 /L N4 ) or (W P1 /L P1 )/(W N1 /L N1 ) for ensuring
proper write operation is set to be 2.5. As the read operation does not disturb the
content of the cell, the cell ratio CR (W N2 /L N2 )/(W P5 /L P5 ) or (W P3 /L P3 )/(W P6 /L P6 )
can be taken conveniently.

3.3 SEU Recovery Mechanism

This subsection describes the SEU recovery mechanism of the proposed cell referring
to Fig. 2 and with the nodes A, Q, QN, and B holding the values ‘1’, ‘0’, ‘1’, and ‘0’,
respectively. If node A is affected by a SET, the state of node A is changed from ‘1’ to
‘0’. This immediately switches N4 transistor OFF and P2 to turn ON [10]. Now both
the transistors P2 and N2 are in an ON state causing the node Q present in between
them to be in an unstable state, at the same time since N4 is OFF, node B enters into a
high impedance state so its state ‘0’ is retained. Since the P3 transistor is unaffected
and continues to be in an ON state the node QN retains its state ‘1’. Hence, the node
QN helps the node Q to regain its original state ‘0’ due to the persistent signal at the
gate terminal of transistor N2 and then node Q itself ensures that node A is brought
6 R. T. Yekula et al.

back to its original state ‘1’ as the node Q controls the transistor P1. The analysis is
similar in the case of node QN due to the symmetric cross-coupled structure of the
SRAM cell.
If node Q is affected by a SET, the node Q state is changed from state ‘0’ to ‘1’
which causes transistor N3 to switch ON and transistor P1 to switch OFF immedi-
ately, this causes node QN to be in an unstable state, simultaneously we can notice
that node A is in high impedance state and, hence, it retains its value without any
fluctuation, and in turn, it makes sure that node B’s state is also unchanged.

4 Simulation Results and Discussions of SRAM Cells

4.1 Read Access Time or Read Delay Analysis

The read access time (T RA ) or read delay is calculated during the read operation; it
is estimated as the time from which the WL goes high to the time when BL or BLB
discharges by 50-mV from its pre-charge (V DD ) value; this difference is sufficient for
the sense amplifier to detect a successful read [10]. The estimated (T RA ) is reported
in Table 1, from which we can observe the Read Access Time (T RA ) is less in the case
of the proposed SRAM cell than the QUCCE 10T. This is because the NMOS stack
has been sized conveniently for shorter T RA since the read operation does not affect
the contents of the cell. From Fig. 3, the variation of T RA with respect to variation of
V DD for both the cells has been reported. It can be observed that the proposed PPTRT
12T SRAM cell shows 1.24× shorter read delay compared to QUCCE 10T SRAM
cell at a nominal supply voltage of 0.7 V. The spread (standard deviation) of T RA of
QUCCE 10T SRAM cell is 1.25× wider than that of the proposed cell at nominal
supply voltage 0.7 V. This implies the robustness of the proposed cell against voltage
variation compared to QUCCE 10T SRAM cell.

Table 1 Comparison of read

Cell Std. Dev. of T RA Mean of T RA V DD (mV)
delay and its variation with
(ps) (ps)
V DD
QUCCE10T 61.55 319.2 770
62.11 346.7 735
65.93 376.8 700
63.18 408.9 665
64.22 445.0 630
PPTRT12T 51.29 254.7 770
52.05 278.1 735
52.91 303.8 700
53.95 332.3 665
54.71 363.9 630
Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant 12T … 7

440
QUCCE 10T
420 Proposed 12T

400

380
(ps)

360
RA

340
T

320

300

280

260
640 660 680 700 720 740 760
V DD (mV)

Fig. 3 Variation of read access time (T RA ) or read delay with V DD is plotted for both QUCCE 10T
and the proposed 12T SRAM cells

4.2 Write Access Time or Write Delay Analysis

The write access time (T WA ) or write delay is measured during the write operation. It
can be estimated as the time from when the WL line is activated to the time when the
node Q is flipped from ‘0’ to ‘1’ state [11]. Table 2 shows the comparison between
QUCCE 10T SRAM cell and the proposed PPTRT 12T cell in terms of write access
time (T WA ) and its variation with V DD . From the table, we can observe that the T WA
of the proposed cell is longer compared to QUCCE 10T SRAM cell. This is due to
the use of PMOS access transistors, which have lower drive current due to lower
mobility of holes compared to electrons in NMOS transistors in QUCCE 10T. From
Fig. 4, the variation of T WA with respect to V DD for both QUCCE 10T SRAM cell
and the proposed 12T SRAM cell can be observed.

Table 2 Comparison of write

Cell Std. Dev. of T WA (ps) V DD (mV)
delay and its variation with
V DD QUCCE10T 763.7 770
790.2 735
819.8 700
851.2 665
886.9 630
PPTRT12 802.3 770
831.3 735
851.3 700
885.6 665
8 R. T. Yekula et al.

920 QUCCE 10T

Proposed 12T
900

T WA (ps) 880

860

840

820

800

780

640 660 680 700 720 740 760

V DD (mV)

Fig. 4 Variation of write access time (T WA ) or write delay with V DD is plotted for both QUCCE
10T and the proposed 12T SRAM cells

4.3 Read Stability Analysis

Static noise margin can be defined as the minimum voltage caused by the noise which
is sufficient to flip the contents of the cell [10]. It is the most extensively used design
metric for estimating the stability of the cell. The length of the side of the largest
square that can be fitted into the smallest wing of a butterfly curve gives the RSNM of
the corresponding cell. From Fig. 5, we can observe that the RSNM of the proposed
SRAM cell is higher compared to the QUCCE 10T SRAM cell (RSNM of QUCCE
10T is 80 mV and that of the proposed PPTRT 12T cell is 175 mV). Whereas in
QUCCE 10T SRAM cell the read operation affects the contents of the cell and thus
can reduce the read stability of the cell. Hence, the RSNM of the proposed cell is
2.19× higher compared to that of the QUCCE 10T SRAM cell.

4.4 SEU Robustness Comparison

SEU robustness can be analyzed using a metric called critical charge (QC ), which is
defined as the minimum charge collected at a sensitive node that can cause an upset to
the state of the cell. By using an exponential current source on the LT spice simulation
environment we can create a SET (Single Event Transient) at the sensitive node, and
using (1), we can calculate the charge that is accumulated at the sensitive node due
to the exponential current source [10]. By increasing the current through the current
source, we are increasing the charge induced at the nodes to which this source is
connected; as we increase the current steadily we can find the critical charge (QC )
of the circuit, i.e., by measuring (Q0 ) corresponding to the current which causes the
SEU using (1), where τ α and τ β are rise and fall time delay constants, respectively.
Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant 12T … 9

0.7
QUCCE 10T
0.6 PPTRT 12T

Storage Node QN (V)

0.5
RSNM QUCCE 10T @ 0.7V = 80mV
RSNM PPTRT 12T @ 0.7V = 175mV
0.4

0.3

0.2

0.1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Storage Node Q (V)

Fig. 5 Butterfly curve for estimating RSNM of QUCCE 10T SRAM cell and the proposed 12T
SRAM cell

Q o  −t −t 
I (t) = e τα − e τβ (1)
τα − τβ

The proposed 12T SRAM cell and the QUCCE 10T SRAM cell are robust against
SET (Single Event Transient) until the charge induced by the SET is less than the
critical charge (QC ). From Figs. 6 and 7 we can observe that a 1 → 0 SET at node
QN of both QUCCE 10T SRAM cell and the proposed 12T SRAM cell flip its
stored content. Extensive simulations are done using PrimeSim HSPICE, where an
exponential current source is used for mimicking the SET at node QN. The minimum
charge to flip the contents of the cell, i.e., (critical charge, QC ) in the case of QUCCE
10T SRAM cell is 2.8 pC and the QC in the case of the proposed 12T SRAM cell
is 3.3 pC. These are calculated for the 1 → 0 SET in both circuits. The proposed
PPTRT 12T SRAM cell exhibits 17.88% increase in critical charge (QC ) compared to
QUCCE 10T SRAM cell. This is because the access transistors used in the proposed
cell are PMOS unlike the NMOS transistors used in QUCCE 10T cell. The drain
diffusion regions of PMOS access transistors in PPTRT 12T are not subjected to
reverse-biased conditions, there is only a slight rise in potential beyond ‘1’ at node
QN due to the strike of energetic particle. This positive spike of potential does
not flip the cell content. In the case of QUCCE 10T SRAM cell, strike-generated
electrons are collected by the node QN due to reverse-biased condition at the drain
diffusion regions of N3 and N6 and, hence, a negative spike is generated resulting
in a possibility of SEU.
10 R. T. Yekula et al.

Fig. 6 Flipping of cell

contents due to 1 → 0 SET
at node ‘QN’ for the
QUCCE10T

Fig. 7 Flipping of cell

contents due to 1 → 0 SET
at node ‘QN’ for the
proposed 12T SRAM cell

5 Conclusion

The proposed 12T SRAM cell is more robust against SEU caused by the energetic
particle. It shows shorter read delay and higher read static noise margin (RSNM)
compared to QUCCE 10T SRAM cell. The proposed PPTRT 12T SRAM cell exhibits
a higher critical charge compared to the QUCCE 10T SRAM cell thereby proving
its radiation hardness against energetic particles. The proposed design is, therefore,
an attractive choice as cache memory in the processor for deep-space applications.
Highly Reliable PMOS Pass Transistor-Based Radiation Tolerant 12T … 11

References

1. B. Narasimham, S. Gupta, D. Reed, J.K. Wang, N. Hendrickson, H. Taufique, Scaling trends

and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs, in Proceedings
of IRPS (2018), pp. 4C.1–1–4C.1–4
2. M.T. Bohr, I.A. Young, CMOS scaling trends and beyond. IEEE Micro 37(6), 20–29 (2017)
3. R.C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies. IEEE
Trans. Device Mater. Reliab. 5(3), 305–316 (2005)
4. V. L. Ferlet-Cavrois, W.P. Gouker, Single event transients in digital CMOS—A review. IEEE
Trans. Nucl. Sci. 60(3), 1767–1790 (2013)
5. P.E. Dodd, L.W. Massengill, Basic mechanisms and modeling of single-event upset in digital
microelectronics. IEEE Trans. Device Mater. Reliab. 50(3), 583–602 (2003)
6. D. Krueger, E. Francom, J. Langsdorf, Circuit design for voltage scaling and SER immunity on
a quad-core Itanium processor, in Proceedings of International Solid-State Circuits Conference
(2008), pp. 94–95
7. T. Karnik, P. Hazucha, J. Patel, Characterization of soft errors caused by single event upsets in
CMOS processes. IEEE Trans. Dependable Secure Comput. 1(2), 128–143 (2004)
8. S.M. Jahinuzzaman, D.J. Sachdev, M. Sachdev, A soft error tolerant 10T SRAM bit-cell with
differential read capability. IEEE Trans. Nucl. Sci. 56(6), 3768–3773 (2009)
9. I.S. Jung, Y.B. Kim, F. Lombardi, A novel sort error hardened 10T SRAM cells for low voltage
operation, in Proceedings of IEEE 55th International MWSCAS (2012), pp. 714–717
10. J. Jiang, Y. Xu, W. Zhu, J. Xiao, S. Zou, Quadruple cross-coupled latch-based 10T and 12T
SRAM bit-cell designs for highly reliable terrestrial applications. IEEE Trans. Circuits Syst. I
Regul. Pap. 66(3), 967–977 (2019)
11. J. Guo et al., Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace
applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(5), 991–994 (2018)
Majority PFET-Based Radiation Tolerant
Static Random Access Memory Cell

Monika Rani, G. Sai Namith, Shashank Kumar Dubey, and Aminul Islam

Abstract Our article presents a Majority PFET-based Radiation Tolerant (MPRT)

Static RAM (SRAM) cell. The benefit of using a greater number PFETs is its high
radiation tolerance. The leakage currents in NMOS access transistors increase rapidly
by the radiation bombardment, whereas they are not affected in the case of PMOS
access transistors. The proposed MPRT SRAM cell achieves 1.2× higher value of
QCri (stands for critical charge) in comparison with the We-Quatro SRAM bit cell
under parametric variations of 16-nm CMOS technology. Proposed circuit MPRT
consumes ≈6% lower hold power in comparison with the We-Quatro. It exhibits
higher read stability by showing 1.5× improvement in RSNM. The proposed cell
achieves these improvements at the expense of 1.26× longer read delay and 1.22×
longer write delay at nominal supply voltage.

Keywords Radiation-hardened SRAM · Soft error · We-Quatro · Current

margin · Critical charge · Read static noise margin (RSNM) · Hold power

1 Introduction

Research in radiation hardening covers a broad subject because radiation originates

from various sources that exist all over the universe. Higher density and lower power
in SRAM are in high demand. To satisfy those demands, dimensions of devices
and operating voltages of SRAM are reduced. Cache memory is made up of SRAM,
which covers 90% of the chip area. In standby mode, while performing data retention
operation, SRAM cell consumes static power due to leakage current of the nanoscale
devices. In the nanoscale regime, memory cells of SRAM are more susceptible to
radiation particles because their nodal capacitance is smaller. Less storage node
charge and decreased noise margin make the nanoscale integrated circuits (ICs),

M. Rani · G. Sai Namith · S. K. Dubey · A. Islam (B)

Department of ECE, Birla Institute of Technology, Mesra, Ranchi 835215, India
e-mail: [email protected]
G. Sai Namith
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 13
A. Biswas et al. (eds.), Microelectronics, Circuits and Systems, Lecture Notes in Electrical
Engineering 976, https://doi.org/10.1007/978-981-99-0412-9_2
14 M. Rani et al.

particularly SRAM circuits, tremendously prone to energetic hit-induced SET (stands

for single-event upset) [1, 2]. Packaging materials and intergalactic rays produce
alpha particles and cosmic neutrons which cause SETs. The soft error occurs when
an energetic particle strike causes the cell content to flip. It affects the data state of
memories such as SRAM cells and other sequential elements. This error is known as
‘soft error’ and not hard error or permanent error because due to radiation, the circuit
is not damaged forever. If new data are stored, then cells store them without any
problem. This phenomenon is variously called single-event transient (SET) or SET
single-event upset. There are two types of radiation hardening techniques occurred:
• Radiation Hardening by Process (RHBP): Radiation hardening by process
(RHBP) is a method to harden a device to SEE using certain features in the
fabrication process. This is done by modifying a current fabrication process.
• Radiation Hardening by Design (RHBD): Radiation hardening by design (RHBD)
approach uses common methods through constructing various topologies of tran-
sistor connections inside cells to achieve circuit-level protection. In this paper,
RHBD approach has been adopted for hardening of memory cell to avoid bit
flipping.
To reduce the leakage power, increase the read stability and soft error problems,
many general and radiation-hardened bit cells are presented [3–17]. Results have
illustrated that in the radiation environment standard 6T SRAM cell may not convey
adequate reliability. To deliver high soft error resilience, researchers are strongly
inspired to explore other SRAM cells. The authors in [3] compared 6 T, the Quatro,
and the We-Quatro through parametric variations.
These make the Quatro more favorable than the 6 T. However, in scaled technolo-
gies, Quatro suffers from poor write ability. To address this problem, the author
exhibited different radiation-hardened SRAM cell called as We-Quatro [3]. The
write ability of Quatro is highly affected by the strength of the access pass gate.
For enhancing the write ability, the author in [3] added two more access pass gates in
Quatro to make it We-Quatro. Access pass gates were realized as NMOS transistors.
We present a new Majority PFET-based Radiation Tolerant (MPRT) SRAM cell,
which has 8 PMOS transistors out of 12. After radiation bombardment, leakage
currents and charge sharing in NMOS transistors increase however PMOS transistors
remain almost unaffected. For higher radiation tolerance, PMOS transistors are used
as major devices.
Extensive simulations on SPICE have been carried out to verify our design and its
superiority compared to the previously proposed We-Quatro in [3]. In SRAM design,
the current margin and critical charge should be considered in addition to general
design metrics namely RSNM, etc. Hence, the proposed bit cell’s metrics have been
compared with those of We-Quatro.
The remaining portion of the article is arranged in the following manner. Section 2
briefly describes the previously presented We-Quatro bit cell. Section 3 presents the
proposed MPRT SRAM cell. The values from the simulation are discussed in Sect. 4.
We conclude the article in Sect. 5.
Majority PFET-Based Radiation Tolerant Static Random Access … 15

Fig. 1 Schematic of
writability-enhanced Quatro
(We-Quatro) SRAM cell [3]

2 A Brief of Previously Proposed We-Quatro SRAM Cell

Due to process, voltage, and temperature (PVT) variation in advanced CMOS

technology, Quatro SRAM cell experiences inferior writability so authors go for
proposing We-Quatro which is described in this section. We-Quatro SRAM cell
exhibits SEU tolerance with reasonable silicon area over budget. Figure 1 illustrates
the schematic of the 12T We-Quarto cell [3]. It contains four PMOS transistors spec-
ified as MP1, MP2, MP3, and MP4, four NMOS transistors named as MN1, MN2,
MN3, and MN4, and four NMOS access transistors (MN5, MN6, MN7, and MN8).
Node ‘D’ and ‘A’ are connected to bit line bar (BLB) by two access transistors
(MN7 and MN5), and another two nodes (‘B’ and ‘C’) are attached to the bit line
(BL) via two access devices (MN6 and MN8). NMOS (MN4, MN5, MN6, and MN7)
access transistors have been replaced with PMOS transistors to improve the radiation
hardness of our proposed circuit.
We have followed the transistor sizing strategies of We-Quatro discussed in the
Quatro proposed in [4] for carrying out Monte Carlo simulations. For achieving a
good read static noise margin (RSNM), cell ratio (CR) of 1.5 is maintained, i.e.,
MN1/3–MP5/6 ratio is 1.5 [3]. Pull-up ratio 1 (PR1) = MP1/3–MP5/6) ratio = 1
and pull-up ratio 2 (PR2) = MP2/4 to ratio MN2/4 ratio = 0.67 are maintained for
reliable writing [3].

3 Description of Proposed MPRT SRAM Cell

Figure 2 shows the outline of the MPRT SRAM cell. It also consists of 12 transistors
like We-Quatro. It contains four PMOS transistors specified as MP1, MP2, MP3,
and MP4 and four NMOS transistors named MN1, MN2, MN3, and MN4. There
are four PMOS access transistors specified as MP5, MP6, MP7, and MP8. Access
16 M. Rani et al.

transistors (MP5 and MP7) control the link between BLB and the node ‘A’ and ‘D.’
Access transistors (MP6 and MP8) control the link between BL and the node ‘B’ and
‘C.’ The nodes ‘D’ and ‘C’ are redundant nodes of storage nodes ‘A’ and ‘B.’ In the
case of hold, read, and write operations, there are two kinds of storage possibilities.
For ‘0’ stored bit, the node values are A = 0, B = 1, C = 1, and D = 0. The node
values are A = 1, B = 0, C = 0, and D = 1 for the stored bit of ‘1.’ The analyses of
the nodes (A, B, C, and D) are demonstrated as follows.
Case 1 (A = 0, B = 1, C = 1, and D = 0): Assuming when node A stores ‘0,’
then MN1 and MP1 are ON and OFF, respectively. The Gate of MN1 is attached to
node B. For allowing node A to have a path to discharge to logic ‘0.’ Since node B
is at logic ‘1,’ MN4 is ON pulling node D down to logic ‘0,’ which turns MP2 ON,
raising node C to logic ‘1.’ The Gate of MP1 is attached to node C. Hence, the logic
value at node C is maintained at ‘1’ to cutoff MP1. That is, the nodes A, B, C, and D
maintain their chronological order (0, 1, 1, 0), respectively.
Case 2 (A = 1, B = 0, C = 0, and D = 1): Assuming when node A stores ‘1,’
the path of charging to V DD by the MP1 is available and the path to discharge to
the ground is cutoff. That is, MP1 and MN1 are turned ON and OFF respectively.
The Gate of MP1 is connected to node C. Since the logic value at node C is ‘0,’ it
switches MP1 ON which allows node A to charge to logic ‘1.’ Since node C is logic
‘0,’ MP4 is ON pulling node D up to logic ‘1,’ which turns MP3 OFF and since the
gate of MN3 is connected to node A, it is ON, thereby pulling down node B to logic
‘0,’ The Gate of MN1 is connected to B; hence, it is OFF. So, the logic value of node
A is maintained at ‘1.’ For any ON PMOS, its gate should be ‘0.’ That is, the nodes
A, B, C, and D maintain their chronological order (1, 0, 0, 1), respectively.
The transistor sizing of the proposed MPRT 12T SRAM cell for carrying out
Monte Carlo simulations is as follows. For a fair comparison, the (W/L) of pull-down
devices (MN1, MN3) and (MN2, MN4) are 36 nm/16 nm and 24 nm/16 nm, respec-
tively. W/L of pull-up transistors (MP1, MP3) and (MP2, MP4) are 20 nm/16 nm and

Fig. 2 Proposed majority

PFET-based radiation
tolerant (MPRT) static
random access memory cell
Majority PFET-Based Radiation Tolerant Static Random Access … 17

16 nm/16 nm, respectively. For successful read and write operations, access devices
are made stronger than pull-up devices and weaker in strength than pull-down devices
and for that W/L of access devices (MP5, MP6, MP7, MP8) are 24 nm/16 nm.

3.1 Write and Read Operation

For a write operation, we suppose that node A is ‘0’ and node B is ‘1.’ Both the
bit lines BLB and BL are set to ‘1’ and ‘0,’ respectively. Word line (WL) goes low.
Hence, all four access transistors are ON. In these circumstances, node B is pulled
down by MP6, and node C is pulled down by MP8. They are fighting against the
weaker pull-up devices MP3 and MP2, that is, BL forcibly flip node B and C to ‘0.’
At the same time, the access transistors MP5 and MP7 help to pull up the nodes ‘A’
and ‘D,’ respectively, and the write operation is successfully performed.
In a read operation, both bit lines (BL and BLB) are precharged to V DD . We assume
that A = ‘0,’ B = ‘1,’ C = 1, and D = 0 before read operation. For carrying out read
operation, WL is lowered. MN3 and MP1 are turned OFF, and MN1 and MP3 will
be turned ON. Hence, BLB starts discharging through MP5 and MN1 because it
provides a ground path. On the other hand, BL does not discharge because there is
no conducting path to the ground. Due to discharging, BLB voltage decreases, and
when the voltage difference of both bit lines BLB and BL come to be 50 mV, a sense
amplifier (not shown) which is connected in the middle of bit lines can sense and
decipher the stored content of the cell.

3.2 Error Tolerance Analysis

Assuming that B = ‘1,’ A = ‘0,’ C = ‘1,’ and D = ‘0’ in Fig. 2, in this subsection
we analyze the SEU recovery behavior at the circuit level.
Case 1. (+ve spike at Node A): If drain diffusion region/n-well of OFF transistor
MP1 is hit by an energetic particle, it collects all the strike generated holes or positive
charge, and a positive spike is generated at node A (that is, node A changes from ‘0’
to ‘1’). Consequently, transistors MN2 and MN3 are turned ON. Although, the state
of other transistors cannot affect by a positive transient pulse. As a result, nodes B
and C remain unaffected. We know, C is a redundant node of B so it stores ‘1.’ Node
C affects the MP1. As a result, for an instant of time node, A changes its value but
after sometimes the nodal logic level is recovered.
Case 2. (−ve spike at Node B): When the drain diffusion region of ON transistor
MP3 is hit by an energetic particle, it collects all the strike generated electrons or
negative charge, and a negative spike is generated at node B (that is, node B changes
from ‘1’ to ‘0’). Consequently, transistors MN4 and MN1 are turned OFF. Although,
the state of other transistors cannot affect by a negative transient pulse. As a result,
18 M. Rani et al.

nodes A and D remain unaffected. We know, D is a redundant node of A so it stores

‘0.’ Node D affects the MP3. As a result, for an instant of time node B changes its
value but after sometimes the nodal logic level is recovered.
Case 3. (−ve spike at Node C): When the drain diffusion region of ON transistor
MP2 is hit by an energetic particle, it collects all the strike generated electrons and
negative charge and a negative spike is generated at node C (that is, node C changes
from ‘1’ to ‘0’). Consequently, transistors MP1 and MP4 are turned ON. Although,
the state of other transistors cannot affect by a negative transient pulse. As a result,
nodes A and D remain unaffected. We know, D is a redundant node of A so it stores
‘0.’ Node D affects the MP2. As a result, for an instant of time node C changes its
value but after sometimes the nodal logic level is recovered.
Case 4. (+ve spike at Node D): When the drain diffusion region of OFF transistors
MP4 is hit by an energetic particle, it collects all the strike generated holes or positive
charge, and a positive spike is generated at node D (that is, node D changes from ‘0’
to ‘1’). Consequently, transistors MP2 and MP3 are turned OFF. Although, the state
of other transistors cannot affect by a positive transient pulse. As a result, nodes C
and B remain unaffected. We know, C is a redundant node of B so it stores ‘1.’ Node
C affects the MP4. As a result, for an instant of time node D changes its value but
after sometimes the nodal logic level is recovered.

4 Simulation Results and Discussions

The focus of this work is to achieve a higher critical charge, which signifies improved
radiation hardness of the circuit. We carry out SPICE simulation using a 16-nm PTM
at a nominal voltage of 0.7 V for comparison with We-Quatro.

4.1 Soft Error Robustness

In this paper, soft error robustness is studied by estimating QCrit (critical charge).
To perform the soft error tolerance analysis, the transient injection at the B node is
simulated, by the double-exponential current source. The double-exponential current
is modeled by Jung et al. [5]
  
Q −t −t/
I (t) = e τ f −e τr . (1)
τf − τr

Here, Q = ± ve charge created and by the particle strike, which is collected by

sensitive node, τ f (fall time) = time constant for the collection of charges at the p-n
junction, and τ r (rise time) = time constant for ion-track establishment [5]. τ f and τ r
Majority PFET-Based Radiation Tolerant Static Random Access … 19

are process-dependent. If an energetic particle strikes at or near a sensitive node and

the minimum amount of charge generated and collected for changing cell content is
known as critical charge [6].
 
−τCric/
QCrit = Q 1 − e τ (2)

We determine QCrit using SPICE-based simulation. An exponential current is

injected in the form (1) at node B. We put the value of τr = 10 ns and τf = 15 ns and
delay time = 2 µs. Now, we increase the value of current amplitude until the cell
flips.
After that for evaluating the value of QCrit injected exponential current is integrated
from delay time to τCric until node voltages intersect. It has been observed from Figs. 3
and 4, τCric of MPRT cell is 2.01234 µs and τcric of We-Quatro cell is 2.00997 µs,
respectively. When we enter the value of τCric in (2), the value of QCrit is determined.
QCrit of We-Quatro is 132.7094 fC and Qcrit of MPRT is 158.0576 fC. From the
above value, it is observed that the value of QCrit is approximately 1.2× higher in the
MPRT circuit compared to We-Quatro.
This observation shows that cell become more radiation hardened by using PMOS
access transistors. The reason behind this is the leakage current in the PMOS access

Fig. 3 Non-recovery of the

MPRT cell for an injected
exponential current imitating
at storage node B

Fig. 4 Non-recovery of the

We-Quatro cell for an
injected exponential current
imitating at storage node B
20 M. Rani et al.

transistors do not get affected by the radiation. This is because in the case of PMOS
transistor due to the use of holes as majority charge carriers are slower and carry less
current, whereas in the case of NMOS transistor electrons are used as majority charge
carriers. Since, mobility of electron is higher than holes so it has higher conductivity
hence leading to lower Rds (dynamic resistance). Due to this even small radiation can
energizes NMOS compare to PMOS hence making PMOS as an access transistor
makes our circuit more radiation hardened.

4.2 Analysis of Read Access Time (TRA ) and Write Access

Time (TWA )

The T RA is evaluated from the moment when the word line (WL) is activated. It
is evaluated up to when BL/BLB is dropped by 50-mV from V DD . This difference
in potential between BL and BLB can be easily detected with the help of a sense
amplifier, thereby avoiding misread. T RA shows more dependency on the I READ (read
current) flowing via access devices. The bit line capacitance and cell ratio determine
I READ [7].
In the We-Quatro bit cell, NMOS devices are used as access transistors, whereas
in MPRT cell, PMOS devices are used as access transistors. Electrons are more
mobile as compared to holes, that is why the T RA of MPRT cell is longer than the
We-Quatro. Figure 5 depicts the graph of T RA comparison between We-Quatro and
MPRT at different voltage levels. Monte Carlo simulations are run with a sample
size of 3000 for estimation of various design metrics in this work.
The required time for storing ‘0’ or ‘1’ to from the time when WL is activated
to the time when the storage node rises to 90% of its full swing from its initial low
level or when the storage node falls to 10% of its initial high level (that is, its 90%
swing) is known as T WA (write delay or write access time). Figure 6 shows the graph
of T WA comparison between We-Quatro and MPRT at different voltage levels using
3000 sample size during Monte Carlo analysis.

Fig. 5 Read access time

(T RA ) or read delay of
MPRT and We-Quatro
SRAM cell at various V DD
Majority PFET-Based Radiation Tolerant Static Random Access … 21

Fig. 6 Write access time

(T WA ) or write delay of
proposed MPRT and
We-Quatro SRAM cell at
various V DD

4.3 Hold Power Analysis

SRAM bit cells remain mainly in hold mode. For long data retention during hold
mode, the word line (WL) is disabled. BL and BLB are precharged, and the partial
cross-coupled inverters are tightly connected [6]. Hold power has been estimated for
both the cells varying the V DD from 630 to 770 mV. Figure 7 shows the hold power
of MPRT and We-Quatro cell. PMOSFETs exhibit an order of magnitude smaller I G
(gate leakage current) compared to NMOSFETs [8]. Therefore, the proposed design
consumes ≈ 6% lower hold power compared with that of the We-Quatro SRAM bit
cell. Total standby power or hold power is given by
 
PHold = VDD × Isub + Ig + IJN (3)

where leakage current includes subthreshold leakage current (I sub ), the gate leakage
current (I g ), and junction leakage current (I JN ) through device.

Fig. 7 Hold power of

MPRT and We-Quatro cell at
various V DD
22 M. Rani et al.

Fig. 8 Read static noise

margin (RSNM) of the
proposed MPRT and
We-Quatro SRAM cells

4.4 Read Static Noise Margin (RSNM)

Static noise margin (SNM) is the minimum DC noise voltage that is required to
change the cell content [5]. It measures the stability of the cell. Figure 8 shows the
butterfly curve of RSNM. The stability of the SRAM bit cell during read mode is
determined by RSNM. The side length of the biggest square that can be inscribed
in the smaller wing of the butterfly curve is used to estimate the noise margin [9].
To estimate the noise margin initially bit lines are precharged in both bit cells. WL
is biased at supply voltage in the We-Quatro cell and in the case of MPRT, WL is
biased to the ground. Two voltage sources N1 and N2 are connected to the gate of
MN3 and MN1 to introduce the DC noise at both storage nodes A and B. N1 and
N2 voltages are swept from 0 V to V DD to calculate the voltages of storage nodes.
Estimated voltage values are used to plot the butterfly curve.
The critical strategy of our design to improve read stability (RSNM) is to decide
the cell ratio (CR) by properly sizing the access devices and the pull-down devices.
The proper dimensioning has resulted in 1.5× higher read SNM of our design in
comparison with that the existing We-Quatro bit cell.

5 Conclusion

This paper presented a new SRAM cell that is more radiation-hardened than the
We-Quatro SRAM cell. Although the We-Quatro SRAM bit cell is one of the good
radiation-hardened SRAM bit cells, by proper design and sizing of the FETs, we
could achieve improved results compared with the We-Quatro SRAM bit cell. In
addition, we compare Read Time and Write Time of MPRT and We-Quatro through
Majority PFET-Based Radiation Tolerant Static Random Access … 23

appropriate simulations. The proposed MPRT design shows improvement in critical

charge, RSNM, and standby power.

References

1. Y.S. Dhillon, A.U. Diril, A. Chatterjee, A.D. Singh, Analysis and optimization of nanometer
CMOS circuits for soft-error tolerance. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
14(5), 514–524 (2006)
2. R. Baumann, Soft errors in advanced computer systems. IEEE Des. Test Comput. 22(3), 258–
326 (2005)
3. L.D. Trang Dang, J.S. Kim, I.J. Chang, We-Quatro: Radiation-hardened SRAM cell with
parametric process variation tolerance. IEEE Trans. Nucl. Sci. 64(9), 2489–2496 (2017)
4. S.M. Jahinuzzaman, D.J. Rennie, M. Sachdev, A soft error tolerant 10T SRAM bit-cell with
differential read capability. IEEE Trans. Nucl. Sci. 56(6), 3768–3773 (2009)
5. I.-S. Jung, Y.-B. Kim, F. Lombardi, A novel sort error hardened 10T SRAM cells for low voltage
operation, in 2012 IEEE 55th International Midwest Symposium on Circuits and Systems
(MWSCAS) (2012)
6. S. Ahmad, N. Alam, M. Hasan, Pseudo differential multi-cell upset immune robust SRAM cell
for ultra-low power applications. AEU-Int. J. Electron. Commun. 83, 366–375 (2018)
7. J. Jiang, Y. Xu, W. Zhu, J. Xiao, S. Zou, Quadruple cross-coupled latch-based 10T and 12T
SRAM bit-cell designs for highly reliable terrestrial applications. IEEE Trans. Circuits Syst. I
Regul. Pap. 1–11 (2018)
8. W. Zhang, L. Li, J. Hu, Design techniques of p-type CMOS circuits for gate leakage reduction
in deep submicron ICs, in 52nd Midwest Symposium on Circuits and Systems—MWSCAS 2009
(2009), pp. 551–554
9. S. Pal, A. Islam, 9-T SRAM cell for reliable ultralow-power applications and solving multibit
soft-error issue. IEEE Trans. Device Mater. Reliab. 16(2), 172–182 (2016)
10. L.D. Trang Dang, M. Kang, J. Kim, I.-J. Chang, Studying the variation effects of radiation
hardened Quatro SRAM bit-cell. IEEE Trans. Nucl. Sci. 63(4), 2399–2401 (2016)
11. L.D. Trang Dang, D. Seo, J. Han, J. Kim, I.-J. Chang, A 28mn FDSOI 4KB radiation-hardened
12T SRAM macro with 0.6 ~ 1V wide dynamic voltage scaling for space applications, in
Proceedings of 2018 Asian Solid-State Circuits Conference (A-SSCC) (2018), pp. 133–134
12. R.C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies. IEEE
Trans. Device Mater. Reliab. 5(3), 305–316 (2005)
13. A. Islam, M. Hasan, Variability aware low leakage reliable SRAM cell design technique.
Microelectron. Reliab. 52(6), 1247–1252 (2012)
14. A. Islam, M. Hasan, Leakage Characterization of 10T SRAM Cell. IEEE Trans. Electron
Devices 59(3), 631–638 (2012)
15. S. Pal, A. Islam, Variation tolerant differential 8T SRAM cell for ultralow power applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4), 549–558 (2016)
16. A. Islam, M. Hasan, T. Arslan, Variation resilient subthreshold SRAM cell design technique.
Int. J. Electron. 99(9), 1223–1237 (2012)
17. A. Islam, M. Hasan, A technique to mitigate impact of process, voltage and temperature
variations on design metrics of SRAM Cell. Microelectron. Reliab. 52(2), 405–411 (2012)
Comparison of Snapback Phenomenon
and Physics in Bottom and Top Body
Contact NMOS

Pragati Singh, Niladri Pratap Maity, Rudra Sankar Dhar,

and Srimanta Baishya

Abstract This paper compares the features and physics of snapback involved in
2D NMOS structures having body/substrate contact at bottom and adjacent to source
under the application of high current ramp at drain and zero gate voltage. We analyzes
the S-shaped current–voltage characteristics of two structures for understanding the
snapback phenomenon and operational window of compact memory devices. This
work also evaluates the carrier electrostatics involving the electron–hole carrier build
up and ambipolar current flow in the body of the structures. We also investigate the
formation of memory cell in the body of NMOS under zero gate bias and ramp of
high current stress at drain terminal due to bipolar turn.

Keywords ZRAM · Snapback · SOIFED-RAM · TRAM

1 Introduction

As we are entering into modern era of nanoscale semiconductor industry, the memory
has become one of the crucial elements for high performance integrated circuits.
Scaling of MOSFET has reached to saturation having gigantic advancements, while
semiconductor-based memories are still facing severe challenges in scaling. In stan-
dard DRAM cell, bulky capacitor accounts for considerable area which is very tough
for designer to shrink the size. The newly introduced zero capacitor RAM (ZRAM)
has only a transistor, and it does not have any capacitor that’s why it shows 1T/0C
unlike the standard DRAM cell which is having one transistor and one capacitor
shown by 1T/1C DRAM cell. Silicon on insulator (SOI)-based multi-gate device is
used for designing of snapback-based memories having bipolar transistor formed in

P. Singh (B) · R. S. Dhar

National Institute of Technology Mizoram, Aizawl 796012, India
e-mail: [email protected]; [email protected]
N. P. Maity
Mizoram University, Aizawl, Mizoram 796004, India
S. Baishya
National Institute of Technology, Silchar, Assam 788010, India

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 25
A. Biswas et al. (eds.), Microelectronics, Circuits and Systems, Lecture Notes in Electrical
Engineering 976, https://doi.org/10.1007/978-981-99-0412-9_3
26 P. Singh et al.

body of the FET [1]. Impact ionization takes place as the drain voltage increases,
which results in generation of the majority carriers. In p-type substrate, holes moves
toward the body, and minority electrons get collected by the drain as the drain voltage
increases to cause the breakdown near the drain–body depletion region. The modi-
fied threshold voltage due to the storage of the charges provides bistability to bipolar
transistor having two states (high and low current). The ZRAM scalability has been
shown in multi-gate with 10 nm thin body [2], and it also expresses the two states of
the memory cell for bipolar transistor formed in the body of the device.
The advancement in vertical gate all around, double gate junction-less, thyristor
RAM (TRAM), silicon on insulator field effect diode RAM (SOIFED-RAM) and
zero-ionization, zero-swing FET (Z2FET) RAM has led the future generation of
the ZRAM [3–6]. Memories based on charge storage have reached to a limit of
scalability. Therefore, the concept of new memory technologies has been introduced.
These new memory technologies must have the smaller size, longer retention time,
higher performance, lower operating voltage and of course the simple structure. So far
TRAM, SOIFED-RAM and Z2FET-RAM have been analyzed to form the compact
capacitor-less snapback-based memory having better retention time and lower power
dissipation [4–7]. TRAM exhibits two stable states due to fast gate switching, and it
relies on the majority carrier concentration in the gated structure. The majority carrier
concentration due to high and low switching of the gate decides the high and low
current states in the thyristor-based RAM. Accumulation of holes (majority carriers)
in p-base thyristor shows high current level, whereas depletion of holes shows low
current level [7]. As per the newer studies, TRAM- and SOI-based FED-RAM’s high
and low current levels defined by the depletion and accumulation of majority carries
[5], which is the opposite of the previously believed studies.
The Z 2 FET-RAM is also a snapback-based memory shown by the S-shaped
hysteresis characteristics, and its high and low states are governed by the high and
low drain voltage [8]. Double gate junction-less device has also been analyzed for
bipolar snapback-based memories [9]. Previously, studied capacitor-less memories
were designed by thyristor or SOI. Insights of TRAM, SOIFED-RAM, Z2FET-RAM
and all other snapback-based memories show that the clearer conception can be
developed for the apprehension of the low and high states of the memory depending
on the carrier electrostatics. Structure of the device and switching conditions also
play an important role to decide the memory states of capacitor-less RAM cells
depending on carrier concentrations. However, bulk MOS has not been introduced in
the designing of capacitor-less memories prominently. Therefore, a better insight is
needed in designing of capacitor-less memory cell using different structures of bulk
MOS.
This research is applicable for non-planar devices like FinFets, multi-gate struc-
tures and gate all around structures (GAA). Double gate junction-less transistor and
vertical transistors are also applicable for the snapback. However, we are looking in
to the bulk NMOS as there is no comparison has been done for bottom body contact
NMOS and side body contact NMOS. Most importantly, we found many untouched
facts in this research which have never been explored in any of the research so far.
However, we are intended to do more research using the non-planar device in the field
Comparison of Snapback Phenomenon and Physics in Bottom and Top … 27

of snapback to design capacitor-less memory cells. We are more concern about bulk
oriented ZRAM as bulk technology is still formidable in the field of semiconductor
memory. These devices present new concept of capacitor-less memory as compared
to the existing 1T-DRAM.
Drain current increases rapidly due to increase in drain to source voltage. Increase
in the drain current causes onset of avalanche multiplication, wherein newly gener-
ated carriers can participate in generating more carriers causing breakdown. Hole
current is significantly increasing in substrate causing voltage drop across the resis-
tance of the substrate to forward bias the source–substrate pn junction. Due to
forward biasing of source–substrate pn junction, electrons are injected from source
to substrate giving rise to parasitic bipolar turn on. The effect of the bipolar action
shown in I D –V D characteristic (Fig. 1) is termed as snapback. In general, MOSFETs
are not operated in the snapback region, whereas it can be used at input/output of
the chips to provide ESD (electro-static discharge) protection [10]. MOS transistors
under zero gate bias are prominently used as ESD protection devices. Behavior of
snapback phenomenon is explained under zero gate bias, but carrier electrostatics
are missing [11, 12]. Gate Grounded NMOS (GGNMOS) under high current applied
at the drain terminal shows the I–V characteristic of the device in Fig. 1. Snapback
phenomenon in these devices are dependent on bipolar turn on in the body of the
device [13, 14]. Explanation of the carrier electrostatics is not clearly understood
in the previous studies. Formation of the memory cell in the body of the device
relies on snapback characteristics, and its retention time is dependent on parameters
(Fig. 1) like (V t1 , I t1 ), V h and (V t2 , I t2 ) [15–19]. These parameters are the prominent
candidates for transforming in to the circuit models. In this paper, snapback-based
capacitor-less memory using two structures of bulk MOS has been presented. We
further emphasized on analysis of snapback in top and bottom body contact bulk
MOS. The formation of the memory cells using the parameters like (V t1 , I t1 ), V h
and (V t2 , I t2 ) in bulk MOS has also been focused.

Fig. 1 Bipolar formation inside the body of NMOS under zero gate bias and stress of high current
ramp at drain showing the snapback in I–V characteristics
28 P. Singh et al.

2 Device Structures and Simulation Setup

Figure 1 shows bipolar formation in the body of NMOS at zero gate bias and high
current ramp at the drain terminal. The device simulation setup uses well calibrated
mobility model and hydrodynamic transport model. In order to capture the accu-
rate results, Fermi–Dirac model, high field saturation, avalanche generation models
and Shockley–Read–Hall recombination/generation are included for MOS operating
biases. In this paper, two structures have been simulated. Structure one has the body
contact at the bottom (Fig. 2), and the structure two has the body contact at the top
adjacent to the source contact (Fig. 3). In the both of the structures, gate terminal
is grounded, and a high current ramp has been applied at the drain terminal. In the
top body contact structure, depth of the substrate is 10 times of the gap between
midpoint of source and body contact to have better analysis of flow lines and carrier
electrostatics. The device characteristics are simulated using Sentaurus two dimen-
sional (2D) Technology Computer Aided Design (TCAD) using its default parame-
ters available in the simulator. Here, we performed 2D transient device simulations
on device structures and examined the mechanism of snapback by applying the zero
gate voltage and high current at the drain terminal.
The schematic of GGNMOS under applied high current bias at the drain is shown
in Fig. 1. This structure is the basic building block of the capacitor-less snapback-
based memories having formed BJT in the body of the structure. The drain voltage–
current characteristics have also been shown, which form the memory cell.

Fig. 2 Contour of hole

current density for bottom
body contact GGNMOS
structure
Comparison of Snapback Phenomenon and Physics in Bottom and Top … 29

Fig. 3 Contour of hole

current density and flow lines
of hole current for side body
contact GGNMOS structure

3 Results and Discussions

Substrate, source and drain terminals represent base, emitter and collector of BJT
formed in the body of GGNMOS under stress of high current at drain terminal
(Fig. 1). High voltage appears at drain terminal due to applied current ramp causes
impact ionization, which results in generation of the carriers. I–V characteristics
show (V t1 , I t1 ) as first snapback point. The generated carriers act as initiating current
as they flow in to the substrate (base), which results in bipolar transistor turn on [20].
Subsequently, collector to base voltage deceases to V h (holding voltage) due to flow
of initiating current in the base (shown in Fig. 1). The bipolar action ceases to exist
due to decrease in collector voltage caused by collector–emitter current.
The bottom body contact structures shown in Fig. 2 provide the storage of the
node, whereas top body structures shown in Fig. 3 govern the sensing of the current
presenting the two states of the memory cell formed in body of the structures. The
majority carrier holes are generated due to band to band tunneling or impact ionization
in MOS transistor [21, 22]. The generated holes stay in top body structure under zero
gate bias. Under these conditions, the vertical field under grounded gate is screened
due to majority carriers, and it has less effect on minority carriers. Current I t1 (shown
in Fig. 1) flowing through the p-substrate of the bottom body structure reads state
“1” and reads state “0” under depleted hole condition (Figs. 2 and 4), whereas in the
top body contact structure, the picture is exactly opposite [23]. In top body structure,
30 P. Singh et al.

buildup of electrons (absence of holes) represents state “1” and depletion of electron
(presence of holes) represents state “0” (Figs. 4 and 5).
The important differences between bulk and SOI-based capacitor-less memory
also between the top and bottom body bulk MOS structures are as follows:
1. Drain current flows due to majority carrier (holes) in bottom body contact,
whereas current flow is determined by electrons in top body contact GGNMOS
structure.

Fig. 4 Contour of electron

current density for bottom
body contact GGNMOS
structure

Fig. 5 Contour of electron

current density and flow
lines of the electron current
for side body contact
GGNMOS structure
Comparison of Snapback Phenomenon and Physics in Bottom and Top … 31

2. Flow of holes and electron determines the state of the memory cells.
3. Buildup of holes takes place in p-substrate bottom body contact, whereas
electrons buildup in p-substrate top body contact structure.
4. Bulk MOS can be utilized for the formation of the memory cells. Buried oxide
is not necessary.
5. Coupling of carriers plays an important role as both electron and hole presence
are crucial in determining the memory states due to bipolar turn on in the body.
Equation (1) shows the relation between the carrier generation/recombination due
to impact ionization and current gain of the device, which is manifested in Figs. 2,
3, 4 and 5.

α·M =1 (1)

Current gain α and impact ionization multiplication factor “M” maintain the
balance between formation of BJT in the body of the MOS and carrier generation–
recombination.

4 Conclusion

In this paper, the memory cell formation inside the body of the bulk MOS structure
has been explained. We found that high and low level of memory states are dependent
on BJT formed inside the MOS. We examined majority carrier (holes) accumulates in
NMOS (bottom body) structure which decides the high level of the memory cell and
absence of the holes relates to the low state of memory cell. We also demonstrated the
memory states relating to the minority carrier (electron) in the top body bulk MOS
structure. The memory state dependency related to carrier electrostatics is exactly
opposite in bottom and top body contact MOS.

Acknowledgements Authors would like to thank Special Manpower Development Program for
chip to system design (SMDP-C2SD) sponsored by Ministry of Electronics and Information Tech-
nology (MeiTy) Govt. of India and National Institute of Technology Mizoram, India, for providing
the machine and tools required to simulate the devices and carry out the research work.

References

1. S. Okhonin, M. Nagoga, E. Carman, R. Beffa and E. Faraoni, New generation of Z-RAM. In

2007 IEEE International Electron Devices Meeting, Washington, DC, USA, (2007) pp. 925–
928. https://doi.org/10.1109/IEDM.2007.4419103
2. V. Sverdlov, S. Selberherr, Scalability of a second generation Z-RAM Cell: A computational
study. In Proceedings of the International Conference on Computational & Experimental
Engineering and Sciences (ICCES) (2010) (pp. 232–247). http://hdl.handle.net/20.500.12708/
71386
32 P. Singh et al.

3. M. G. Ertosun, H. Cho, P. Kapur, K.C. Saraswat, A nanoscale vertical double-gate single-

transistor capacitorless DRAM. In IEEE Electron Device Letters 29(6), 615–617 (2008). https://
doi.org/10.1109/LED.2008.922969
4. D. Resnati et al., Modeling of dynamic operation of T-RAM cells. In IEEE Transactions on
Electron Devices 62(6), 1905–1911 (2015). https://doi.org/10.1109/TED.2015.2421556
5. A. Z. Badwan, Q. Li, D. E. Ioannou, On the nature of the memory mechanism of gated-thyristor
dynamic-RAM cells. In IEEE Journal of the Electron Devices Society 3(6), 468–471 (2015).
https://doi.org/10.1109/JEDS.2015.2480377
6. S. Cristoloveanu, K. Lee, M. Parihar, H. El Dirani, J. Lacord, S. Martinie, C. Le Royer,
J.C. Barbe, X. Mescot, P. Fonteneau, P. Galy, F. Gamiz, C. Navarro, B. Cheng, M. Duan, F.
Adamu-Lema, A. Asenov, Y. Taur, Y. Xu, Y.T. Kim, J. Wan, M. Bawedin, Solid-State Electron.
143, 10 (2018). Extended papers selected from EUROSOI-ULIS 2017 conference. https://
doi.org/10.1016/j.sse.2017.11.012. https://www.sciencedirect.com/science/article/pii/S00381
10117306512
7. H. Mulaosmanovic et al., Working principles of a DRAM cell based on gated-thyristor bista-
bility. In IEEE Electron Device Letters 35(9), 921–923 (2014). https://doi.org/10.1109/LED.
2014.2336674
8. J. Wan, C. Le Royer, A. Zaslavsky and S. Cristoloveanu, A compact capacitor-less high-speed
DRAM using field effect-controlled charge regeneration. In IEEE Electron Device Letters
33(2), 179–181 (2012). https://doi.org/10.1109/LED.2011.2176908
9. M. Parihar, D. Ghosh, G. Armstrong, A. Kranti, Bipolar snapback in junctionless transistors
for capacitorless dynamic random access memory. Appl. Phys. Lett. 101 (2012). https://doi.
org/10.1063/1.4773055
10. Y. Tsividis, C. McAndrew, Operation and modeling of the mos transistor, 3(5), 283–285 (2011)
11. C. Duvvury and G. Boselli, ESD and latch-up reliability for nanometer CMOS technologies,
IEDM Technical Digest. In IEEE International Electron Devices Meeting, San Francisco, CA,
USA (2004) pp. 933–936. https://doi.org/10.1109/IEDM.2004.1419337
12. C. Duvvury et al., Efficient npn operation in high voltage NMOSFET for ESD robustness. In
Proceedings of International Electron Devices Meeting, Washington, DC, USA (1995) pp. 345–
348. https://doi.org/10.1109/IEDM.1995.499211
13. M. Shrivastava, J. Schneider, M. S. Baghini, H. Gossner and V. R. Rao, On the failure mechanism
and current instabilities in RESURF type DeNMOS device under ESD conditions, In 2010 IEEE
International Reliability Physics Symposium, Anaheim, CA, USA (2010) pp. 841–845. https://
doi.org/10.1109/IRPS.2010.5488723
14. M. Shrivastava, H. Gossner, M. S. Baghini and V. Ramgopal Rao, Part II: On the three-
dimensional filamentation and failure modeling of STI type DeNMOS device under various
ESD conditions. In IEEE Transactions on Electron Devices 57(9), 2243–2250 (2010). https://
doi.org/10.1109/TED.2010.2055278
15. Vassilev, V. and Groeseneken, G. and Bock, K. and Maes, H.E., A compact MOSFET break-
down model for optimization of gate coupled ESD protection circuits. In Solid-State Device
Research Conference, Proceeding of the 29th European (1999)
16. S. Reggiani, E. Gnani, M. Rudan, G. Baccarani, S. Bychikhin, J. Kuzmik, D. Pogany, E. Gornik,
M. Denison, N. Jensen, G. Groos, and M. Stecher, A new numerical and experimental analysis
tool for ESD devices by means of the transient interferometric technique. Electron. Device.
Lett. IEEE, 26, 916–918, (2005)
17. M. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner, Analysis and
compact modeling of lateral DMOS power devices under ESD stress conditions. In Electrical
Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396),
Orlando, FL, USA, (1999) pp. 1–10. https://doi.org/10.1109/EOSESD.1999.818983
18. C. Diaz, S.-M. Kang, and C. Duvvury, Circuit-level electrothermal simulation of electrical over-
stress failures in advanced MOS I/O protection devices. Comput. Aided. Des. Integr. Circuits.
Syst. IEEE Trans. 13, 482–493 (1994)
19. R. W. Dutton, Bipolar transistor modeling of avalanche generation for computer circuit simu-
lation. In IEEE Transactions on Electron Devices, 22(6), 334–338 (1975). https://doi.org/10.
1109/T-ED.1975.18132
Comparison of Snapback Phenomenon and Physics in Bottom and Top … 33

20. P. Singh, R. S. Dhar and S. Baishya, Features of snapback in compact memory devices for
high performance integrated circuits. In 2021 Devices for Integrated Circuit (DevIC), Kalyani,
India, (2021) pp. 397–400. https://doi.org/10.1109/DevIC50843.2021.9455880
21. R. Ranica et al., A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI
device for high density embedded memories. IEDM Technical Digest. IEEE. Inter. Electron.
Devices. Meet. San Francisco, CA, USA, (2004) pp. 277–280. https://doi.org/10.1109/IEDM.
2004.1419131
22. E. Yoshida and T. Tanaka, A capacitorless 1T-DRAM technology using gate-induced drain-
leakage (GIDL) current for low-power and high-speed embedded memory. In IEEE Trans-
actions on Electron Devices, 53(4), 692–697 (2006). https://doi.org/10.1109/TED.2006.
870283
23. R. Ranica et al., A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI
device for high density embedded memories. IEDM Technical Digest. IEEE. Inter. Electron.
Devices. Meet. 2004., San Francisco, CA, USA, (2004) pp. 277–280. https://doi.org/10.1007/
s12633-021-01086-4. https://link.springer.com/article/10.1007/s12633-021-01086-4
A Review on Optimal Power Flow
Problem

Naveen Kumar, Ramesh Kumar, and Ram Kumar

Abstract Operation of power system with systematic planning plays an important

role in the growth of the economy of the country. The optimal power flow has the
utmost duty of maintaining reliable, safe, and finest functioning of the power system.
OPF consists of complicated, non-convex, non-linear, non-constant as well as a multi-
channel problem that contains both discrete and constant variables. Traditionally,
classical optimization methods were used to solve the OPF problem. But with the
incorporation of FACTS devices and deregulation of the power sector, the tradi-
tional concepts and practices are superimposed by economic market management.
Now, different objective functions such as minimization of fuel cost, minimization
of emission, improving voltage profile, enhancement of voltage stability, reducing
active power loss, and minimization of transmission cost have to achieve. Techniques
that are used to solve OPF problems are the arithmetic programming method, analyt-
ical approach, and meta-heuristic optimization algorithm. This work gives focus a
review of different optimization methods used for OPF in power systems.

Keywords Optimal power flow · Objective functions · Constraints · Approaches

for OPF · Merits and demerits of different approaches for OPF solution

1 Introduction

Optimal power flow (OPF) starts from generating plants, transmission lines, and
distribution lines up to the customer’s end in the power system. That is why a power
system network is a very complicated and complex network. For its complex nature,

N. Kumar (B) · R. Kumar

Department of EE, National Institute of Technology, Patna 800005, India
e-mail: [email protected]
R. Kumar
e-mail: [email protected]
R. Kumar
Department of EEE, Katihar Engineering College, Katihar 854109, India

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 35
A. Biswas et al. (eds.), Microelectronics, Circuits and Systems, Lecture Notes in Electrical
Engineering 976, https://doi.org/10.1007/978-981-99-0412-9_4
36 N. Kumar et al.

planning, operation, and management of power systems are a great challenge for oper-
ators. Availability of electrical energy with quality, reliability, security, and economic
to the customers is the prime duty of the operators. The increasing load on generating
plants, establishment of new station and substation, and seasonal and climatic condi-
tion causes variation in load demand. Hence, operator must have to avoid voltage
deviation with proper maintaining voltage throughout the network as well as mini-
mized active power loss in generation, transmission, and distribution network [1, 2].
These objectives can be achieved from OPF by using reactive power compensation
devices as generator voltage setting, shunt capacitor bank, synchronous condenser,
tap changing transformer, and VAR devices while fulfilling a set of physical as well as
operating regularity and irregularity constraints. Optimal power flow (OPF) was for
the first time introduced by Carpentier in 1962 [3]. Later on, OPF was further devel-
oped by Dommel and Tinney [1]. A first survey related to optimal power flow was
presented by Happ [4] and after that IEEE working group [5] given a bibliography
survey of economic security functions in 1981. Carpentier [6] presented a survey
and classified the OPF algorithm according to their solution methodology in 1985.
Chowdhury and Rahman [7] presented a survey on economic dispatch problems in
1990. Momoh et al. [8] presented a review on some selected OPF techniques in 1999.
Pandya and Joshi [9] given a survey on traditional and artificial intelligence optimiza-
tion methods in 2008. This OPF problem is classified into two subcategories. The
first is recognized as economic load dispatch (ELD), and the second is recognized as
optimum reactive power dispatch (ORPD). The subcategories of the OPF problem
are given in Fig. 1.

Minimization of Power Loss

Improvement of Voltage
Optimal Reactive Profile
Power Dispatch
(ORPD)
Enhancement of Voltage
Stability

Optimal Power Minimization of Operating

Flow (OPF) Cost

Minimization of Fuel Cost

Economic Load
Dispatch (ELD)
Minimization of Emission

Fig. 1 Subcategories of optimal power flow

A Review on Optimal Power Flow Problem 37

2 Mathematical Modeling of OPF

The main task of the OPF problem is the solving of complicated and non-continuous
functions by nourishing both equality and inequality constraints. Control variables
for OPF problems are alternator voltage, transformer tapping, and reactive power
delivered by reactors and capacitors.

2.1 Objective Function

Minimization of Fuel Cost

∑
N
| |
F1 = MinFuelcost = α j + β j PG j + γ j PG2 j + |e j sin f j (PGMin
j − PG j )
| (1)
j=1

α j , β j , and γ j are fuel cost coefficient of j th generator, PG j is the power delivered

by j th generator, e j and f j are the fuel cost coefficients of the j th generator due to
the valve point effect.
Minimization of Emission

F2 = MinEmission = ak + bk PGk + ck PGk

2
+ εk (exp(δk ∗ Pk )) (2)

where ak, bk, εk, and δk are the emission coefficients of k th generating unit.
Minimization of Active Power Losses

∑
N
[ ]
F3 = MinPowerLoss = G B (VK )2 + VL2 − 2VK VL cos θKL (3)
B=1

where VK = Voltage of bus K, VL = Voltage of bus L, B = Branch number, N =

Number of lines, G B = Conductance, θKL = Voltage angular difference.
Improvement of Voltage Profile
Regulation of voltage at buses is also an important objective of ORPD. The general
equation for the improvement of voltage profile is given below.
( N )
∑| sp ||
F4 = MinVoltageDeviation = | VMb − VMb (4)
b=1

sp
b = Bus number, VMb = Actual bus voltage, VMb = Specific bus voltage, N = Number
of load bus
38 N. Kumar et al.

Enhancement of Voltage Stability

F5 = Min(L Max ) = Min[Max(L M )] M = 1, 2, 3 . . . . . . , N (5)

| |
| ∑N |
| Vu |
LM = |1 − f uv < {θuv + (δu − δv }|
| Vv |
m=1

f uv = − [Yuv ]−1 [Yuv ]

where L M = Voltage stability indicator, Y = Admittance, θ = Phase angle, N =

Number of buses.
Minimization of Transmission Cost
[ (/ )]
( )
F6 = MinTran Loss = Cgpj Q gj = Cgpj Sgj max − Cgpi Sgj2 max − Q 2gj kgj (6)

A quadratic function

Cgpi Pgk = a Pgk

2
+ b Pgk + c

where Pgk is the active power output of gk and a, b, and c are cost coefficients.

2.2 Constraints

The OPF needs to satisfy with power balance and with system operational limits.
These constraints are divided into two categories, i.e., equality constraints and
inequality constraints.
Equality Constraints
Equality constraints are generally shown by power balance equations which ensure
that total power generation must satisfied total load demands and power loss in
transmission lines.
Active Power Flow Balance Equation
∑
Pgs − PLs − Vs Vk (gsk cos θsk + Bsk sin θsk ) = 0 (7)
k∈Ns
A Review on Optimal Power Flow Problem 39

Reactive Power Flow Balance Equation

∑
Q gs − Q Ls − Vs Vs (gsk sin θsk + Bsk cos θsk ) = 0 (8)
k=Ns

where Bsk is the susceptance.

Inequality Constraints
In OPF, inequality constraints are of two types—control variables and state variables.
The control variables consist of transformer output setting, generator bus voltages,
and shunt capacitors reactive power generation. The state variables include load bus
voltages, PV buses reactive power, flow limit of line, and generation of the active
power of slack bus. These constraints are given as follows:
Load bus voltage magnitude is given by

VsMin ≤ Vs ≤ VsMax , s ∈ Nb (9)

where s = Bus number and Nb = Total number of buses.

PV buses reactive power generation limit is given by

gs ≤ Q gs ≤ Q gs , s ∈ Ng
Q Min Max
(10)

s = Bus number and Ng = Total generators number.

Compensator reactive power output is given by

cj ≤ Q cj ≤ Q cj ,
Q Min j ∈ Nc
Max
(11)

where s = Bus number and Nc = Total capacitors number.

Transformer tap setting is given by

TlMin ≤ Tl ≤ TlMax , l ∈ Nt (12)

where l = Branch number and Nt = Total connection number.

Transmission line power flow limit is given by

S J ≤ S Max
j (13)

where S Max
j = Maximum value of apparent power of jth line.
40 N. Kumar et al.

Fig. 2 Flowchart of optimal power flow problem

3 Formulation of OPF Problem

The OPF problem aims to set up a network with proper planning at minimum cost
for satisfying desired objectives. First of all, it is required to define system data, allo-
cation of generators, and reactive power sources [10]. After that control variables are
optimized to find out certain objective functions considering equality and inequality
constraints. Control variables include terminal voltages of generator bus, reactive
power generation of VAR sources, and transformer tapping [11]. The dependent vari-
ables include voltage magnitude of load bus, active power generation at stack bus,
power flows through transmission lines, and reactive power output of the generators
(Fig. 2).

4 Challenges in OPF

# Due to a large number of constraints and non-linearity, it has become a great

challenge for engineers as well as for mathematicians to get optimum solutions.
# Due to deregulated market of electricity, optimal power flow faces problems
in adjusting the various type of participants of the market, requirements in data
modeling, and processing in real-time.
# Optimum power flow has to face challenges in dealing with time requirements
for external modeling such as loop flow, simultaneous sending, and sensitivity in
using lines.
Random documents with unrelated
content Scribd suggests to you:
suuriin riemuihin nuorelle miehelle liian äkillistä.

Sillä välin, kun kauneudesta säihkyvän kuningattaren astuessa

ohitse otsat kumartuivat ja aseet kavahtivat pystyyn olisi voitu nähdä
muuan ukko, joka ajatuksiinsa kiintyneenä laiminlöi hovisäännön.
Hän näet ei kumartanut eikä luonut katsettaan maahan, vaan kurotti
päätään ja tuijotti kuningattareen ja Taverneyhin. Kun kuningatar
poistui, tunkeutui pieni ukko erilleen jonosta, joka alkoi hajaantua, ja
hänen nähtiin juoksevan niin nopeasti kuin seitsenkymmenvuotisilla
pikku jaloillaan pääsi.
XI

SVEITSILÄISLAMPI

Jokainen tuntee sen pitkulaisen neliön, joka kesällä on merivihreä

ja läikehtivä, talvella valkoinen ja rosoinen, ja jolla vielä nykyäänkin
on nimenä Sveitsiläislampi. Pitkin lammen reunoja kulkee käytävä,
jonka lehmukset iloisesti kurottavat punertavia oksiaan aurinkoa
kohti, ja siellä on kaikensäätyisiä ja -ikäisiä kävelijöitä, jotka tahtovat
nauttia reellä ajon ja luistelun katselemisesta.

Naisten puvuissa tulee hälisevästi esille sekaisin vanhan hovin

hieman rasittavaa ylellisyyttä ja uuden kuosin hieman oikullista
luontevuutta. Korkeat hiuslaitteet, nuoria otsia varjostavat harsot,
useimmilla vaatehatut, turkisvaipat ja silkkihameiden laajat
poimureunukset ja toiselta puolen punaiset takit, taivaansiniset
univormut, keltaiset liverit ja suuret, valkoiset kaavut tekevät
yhteensä hyvinkin merkillisen sekamelskan. Sinivalkoiset palvelijat
pistävät tästä joukosta esille kuin uni- ja ruiskukat, joita tuuli
huojuttaa tähkäpäiden tai apilain seassa.

Toisinaan kuuluu kokoontuneen väen taholta ihastuksen huuto,

kun taitava luistelija Saint-Georges on piirtänyt niin täydellisen
ympyrän, ettei mittaustieteilijäkään siinä keksisi mainittavaa virhettä.

Sillaikaa, kun lammen rannoilla on niin paljon katselijoita, että he

lämmittävät toisiaan kosketuksella ja kaukaa näyttävät kirjavalta
matolta, jonka yläpuolella leijailee usvaa, pakkasen puristamaa
hengitystä, tarjoo itse lampi, paksuksi jääkuvastimeksi muuttuneena,
mitä moninaisimman ja varsinkin vaihtelevimman näyn.

Tuolla kiitää kolmen suunnattoman ison paimenkoiran vetämä reki

kuin venäläinen kolmivaljakko pitkin jäätä. Vaakunakoristeisiin
samettiloimiin puetut koirat, päähineinä liehuvia sulkia, ovat sen
näköisiä kuin kummituseläimet Callotin paholaiskuvissa tai Goyan
velhomaalauksissa.

Niiden isäntä, herra de Lauzun, lojuu huolettomasti tiikerinnahoilla

sisustetussa reessä ja painautuu hieman sivulle hengittääkseen
vapaammin, mikä luultavasti ei onnistuisi, jos hän kääntäisi kasvonsa
suoraan tuulta vasten.

Siellä täällä pyrkivät jotkut hiljakseen kulkevat reet muista eroon.

Erääseen näistä reistä astuu nainen, jolla varmaankin kylmän vuoksi
on naamio, ja uljas luistelija, yllään kultanauhuksilla koristettu avara
samettiviitta, nojaa selkämykseen antaakseen parempaa vauhtia
reelle, jota sysää ja samalla ohjaa. Naamioidun naisen ja
avaraviittaisen luistelijan välinen keskustelu on kuiskutusta, eikä
kukaan voi moittia heidän salaista kohtaustaan vapaassa
ulkoilmassa, koko Versaillesin nähtävissä.

Mitä se toisiin kuuluu, mitä he puhuvat, kunhan heidät vain

nähdään, ja mitä he siitä huolivat, että heidät nähdään, kunhan vain
ei heitä kuulla. Ilmeisesti he kaikkien näiden joukossa elävät omaa
eristettyä elämäänsä ja kiitävät muun väen seassa kuin kaksi
muuttolintua. Minne he kulkevat? Siihen tuntemattomaan
maailmaan, jota kaikki sielut etsivät ja jonka nimenä on autuus.

Äkkiä syntyy näiden keijukaisten kesken, jotka enemmän liukuvat

kuin käyvät, suuri hälinä. Se johtuu siitä, että Sveitsiläislammen
rannalle on ilmestynyt kuningatar, että hänet on tunnettu ja
valmistetaan hänelle tilaa, mutta silloin hän viittaa kädellään, että
kaikki jäisivät paikoilleen.

Kajahtaa huuto: eläköön kuningatar! Sitten järjestyvät kiitävät

luistelijat ja työnnettävät reet kuin sähkövoimalla suureksi kehäksi
sen paikan ympärille, jonne ylhäinen tulija on pysähtynyt.

Kaikkien huomio on kiintynyt häneen.

Herrat lähestyvät sulavin liikkein, naiset järjestävät pukujansa

kunnioittavan säädylliseksi, ja jokainen pyrkii melkein yhtymään
aatelismiesten ja ylempien upseerien ryhmiin, jotka kiirehtivät
tervehtimään kuningatarta.

Ylhäisten henkilöiden joukossa, joita yleisö pitää silmällä, on

muuan erittäin huomattava, joka ei seuraa yleistä harrastusta eikä
riennä kuningattaren luo, vaikka on tämän puvun ja seuralaiset
tuntenut, vaan päinvastoin jättää rekensä ja poikkee vastakkaiselle
käytävälle kadoten sinne seurueineen.

Artoisin kreivi, joka nähtiin uljaimpien ja taitavimpien luistelijain

joukossa, oli ensimmäisiä rientämään sinne, missä hänen kälynsä oli.

"Näettekö", sanoi hän hiljaa kuningattarelle, suudellen tämän

kättä, "kuinka veljemme Provencen kreivi teitä karttaa?"
 Ja näin sanoen hän viittasi kuninkaalliseen korkeuteen, joka
harpaten kiirehti kuuraisen vesakon halki kiertoteitse vaunujensa luo.

"Hänen ei tee mieli kuulla nuhteitani", selitti kuningatar.

"Mitä nuhteisiin tulee, joita hän odottanee, koskee se asia minua,

eikä hän senvuoksi teitä vältä."

"No sitten hänellä on omantunnon vaivoja", sanoi kuningatar

hilpeästi.

"Hänellä on toinenkin syy, kälyni."

"Mikä?"

"Sen saatte kuulla. Hän on juuri saanut tietää, että mainio voittaja,
herra de Suffren, saapuu tänä iltana, ja kun se on tärkeä uutinen, ei
hän suo teidän siitä saavan tietoa."

Kuningatar näki ympärillään muutamia uteliaita, joita ei kunnioitus

pitänyt niin loitolla, etteivät olisi kuulleet hänen lankonsa sanoja.

"Herra de Taverney", sanoi hän, "olkaa niin hyvä ja katsokaa, onko

rekeni kunnossa, ja jos isänne on täällä, syleilkää häntä; saatte
minulta lomaa neljännestunniksi."

Nuori mies kumarsi ja riensi joukon puhki toimittamaan

kuningattaren asiaa. Väkijoukko oli myös ymmärtänyt: sillä on joskus
tarkka vaisto; se laajensi kehää, ja kuningatar jäi Artoisin kreivin
kanssa paremmin rauhaan.

"Selittäkää nyt, lankoni", sanoi kuningatar; "mitä etua hänellä siitä

on, etten saisi tietää herra de Suffrenin tulevan."
 "Voi, kälyni, onko mahdollista, että te, nainen, kuningatar ja hänen
vastustajansa, ette heti pääse selville tämän ovelan poliitikon
tarkoituksesta? Herra de Suffren saapuu tänne, eikä hovissa sitä
tiedä kukaan. Herra de Suffren on Intianmeren sankari ja siis
oikeutettu saamaan Versaillesissa komean vastaanoton. No niin, hän
saapuu; kuningas ei tiedä asiasta mitään ja laiminlyö hänet
tietämättään, siis vastoin tahtoaankin, ja te, kälyni, samoin. Mutta
sillä välin Provencen kreivi, joka nyt tietää odottaa herra de
Suffrenia, ottaa herttaisesti vastaan merisankarin, hymyilee hänelle,
hellii häntä, laatii hänelle runonkin ja liittyen läheisesti Intian
sankariin pääsee itsekin tavallaan Ranskan sankariksi."

"Se on selvä asia", myönsi kuningatar.

"Niin päivänselvä!" sanoi kreivi.

"Teiltä unohtuu vain muuan seikka, hyvä viestintuoja."

"Mikä?"

"Kuinka teille on selvinnyt tämä rakkaan veljen ja langon kaunis

suunnitelma?"

"Kuinkako sen tiedän? Samoin kuin kaiken muun, mitä hän

puuhaa. Se on hyvin yksinkertaista: huomattuani Provencen kreivin
urkkivan kaikkea, mitä minä teen, olen palkannut väkeä
ilmoittamaan minulle, mitä hommia hänellä on. Siitä voi olla minulle
hyötyä ja teillekin, kälyni."

"Kiitos liittolaisuudesta, mutta entä kuningas?"

"Kuninkaalle on jo ilmoitettu."
 "Tekö ilmoititte?"

"En suinkaan, vaan meriministeri, jonka lähetin hänen luokseen.

Koko asia ei kuulu minulle; ymmärrättehän, minä olen liian
kevytmielinen, tuhlari, hulluttelija, niin ettei minun sovi sekaantua
näin tärkeisiin asioihin."

"Oliko meriministerikin tietämätön herra de Suffrenin tulosta

Ranskaan?"

"Hyvä käly, olettehan tuntenut kyllin monta ministeriä niinä

neljänätoista vuotena, jolloin olette ollut Ranskan dauphine tai
kuningatar, tietääksenne, etteivät ne herrat koskaan tärkeätä asiaa
tiedä. Tällä kertaa sai ministeri tietonsa minulta ja ihastui."

"Sen kyllä uskon."

"Käsitätte kaiketi, hyvä käly, että se mies on koko ikänsä minulle

kiitollinen, ja hänen kiitollisuuttaan juuri tarvitsenkin."

"Mitä varten?"

"Välittämään lainaa."

"Ai, ai", huudahti kuningatar nauraen, "nyt te pilasitte kauniin

tekonne!"

"Varmaankin te tarvitsette rahaa", sanoi Artoisin kreivi vakavan

näköisenä. "Ranskan pojan kunnian kautta lupaan käytettäväksenne
puolet siitä, mitä saan."

"Pitäkää kaikki", sanoi Marie-Antoinette; "tällä haavaa, Jumalan

kiitos, en tarvitse mitään."
 "Mutta hitto vie, älkää vain kovin myöhään muistuttako minulle
lupaustani."

"Miksi niin?"

"Siksi, että jos kauan viivyttelette, minun voisi käydä

mahdottomaksi pitää sanaani."

"Olkoon niin; minun on siis myös pidettävä huolta siitä, että keksin
jonkin valtiosalaisuuden."

"Mutta te vilustutte, kälyni", sanoi prinssi, "poskenne jo sinertyvät,

sanon teille."

"Tuossahan herra de Taverney jo tuo tänne rekeni."

"Ette siis enää kaipaa seuraani?"

"En."

"Siinä tapauksessa pyydän ajamaan minut pois."

"Miksi? Vai luuletteko ehkä, että jollakin tapaa häiritsette minua?"

"En suinkaan, vaan päinvastoin itse tarvitsen vapauttani."

"Hyvästi siis!"

"Näkemiin, rakas käly!"

"Milloin?"

"Tänä iltana."

"Mitä illalla on?"

 "Ei ole, vaan tulee."

"No mitä sitten tulee?"

"Paljon väkeä kuninkaan pelipöydän ääreen."

"Minkä vuoksi?"

"Senvuoksi, että meriministeri tuo sinne herra de Suffrenin."

"Hyvä on, hyvästi siis iltaan asti!"

Nuori prinssi kumarsi kuningattarelle viehättävän kohteliaasti,

kuten hän osasi, ja hävisi väen joukkoon.

Isä Taverney oli katseillaan seurannut poikaansa, kun tämä poistui

kuningattaren luota pitämään huolta reestä. Mutta pian hänen
katseensa oli palannut kuningattareen. Marie-Antoinetten vilkas
puhelu lankonsa kanssa teki hänet hieman levottomaksi, sillä se
katkaisi kaiken tuttavallisuuden, jota kuningatar juuri oli osoittanut
hänen pojalleen. Hän tyytyikin vain ystävällisesti nyökkäämään
Filipille, kun tämä oli suorittanut reen liikkeellepanoa varten
tarpeelliset valmistukset, ja kun nuori mies noudattaen
kuningattaren käskyä aikoi syleillä isäänsä, jota ei ollut kymmeneen
vuoteen nähnyt, viittasi tämä häntä poistumaan ja sanoi:

"Myöhemmin, myöhemmin, tule sitten, kun virantoimituksesi on

päättynyt. Sitten saadaan puhella."

Filip poistui siis, ja parooni näki hyvillä mielin, että Artoisin kreivi
sanoi jäähyväiset kuningattarelle.
 Tämä istuutui rekeen ja otti Andréen viereensä, ja kun kaksi
kookasta palvelijaa kiirehti työntämään rekeä, sanoi kuningatar:

"Ei, ei, en tahdo kulkea sillä tavoin. Ettekö luistele, herra de

Taverney?"

"Kyllä, madame", vastasi Filip.

"Antakaa luistimet herra upseerille!" käski kuningatar ja kääntyen

Filipin puoleen lisäsi:

"En tiedä, mistä olen saanut päähäni, että te luistelette yhtä hyvin
kuin Saint-Georges."

"Jo monta vuotta sitten", sanoi Andrée, "Filip luisteli vallan

mainiosti."

"Eikä nyt kukaan voi kanssanne kilpailla, vai mitä, herra de

Taverney?"

"Kun teidän majesteetillanne on minuun niin suuri luottamus",

sanoi
Filip, "niin koetan parastani."

Tällöin hän jo oli kiinnittänyt kenkiinsä luistimet, jotka olivat niin

teräviksi hiotut kuin veitset. Nyt hän asettui reen taakse, antoi sille
toisella kädellä vauhtia, ja niin alkoi kulku.

Silloin saatiin katsella merkillistä näytelmää. Kaikkien voimistelijain

kuningas Saint-Georges, komea mulatti, yleisön suosikki, etevin
kaikissa ruumiinharjoituksissa, aavisti itselleen kilpailijaa tästä
nuoresta miehestä, joka uskalsi hänen ohellaan heittäytyä
kilparadalle.
 Hän alkoikin heti liehua kuningattaren reen ympärillä niin
kunnioittavin ja siroin kumarruksin, ettei tottuneinkaan hovimies ollut
Versaillesin parkettilattialla koskaan tervehtinyt viehättävämmin. Hän
piirteli reen ympäri mitä nopeimpia ja säännöllisimpiä kehiä, kietoen
sen perätysten renkailla, jotka ihailtavasti liittyivät toisiinsa, niin että
jokainen uusi kaari kulki reen editse ja hän sitten, jäätyään reen
taakse kehää päättämään, uudella ponnahduksella piirsi eteenpäin
kiitäen soikion ja taas voitti sen matkan, minkä reki oli päässyt
edelle. Kukaan ei edes katseella voinut tätä liikehtimistä seurata
joutumatta ihmettelyn ja hämmästyksen valtaan.

Filip oli tästä jo kiihtynyt ja teki uhkarohkean päätöksen: työnsi

rekeä niin pelottavan nopeasti, että Saint-Georges pari kertaa jäi
suorittamaan ympyriään sen taakse, ehtimättä edelle, ja kun reen
kova vauhti sai monet päästämään kauhun huutoja, jotka olisivat
voineet säikäyttää kuningatarta, sanoi Filip:

"Jos teidän majesteettinne tahtoo, niin pysäytän tai ainakin

hiljennän."

"Ei, ei!" huudahti kuningatar hurjassa innossa, joka oli hänelle

ominainen sekä työssä että huvissa. "En minä pelkää, nopeammin,
ritari, jos voitte, nopeammin!"

"Sitä parempi! Kiitän luvastanne, madame. Pidän kyllä lujasti

kiinni, saatte luottaa minuun."

Ja kun hänen jäntevä kätensä taas tarttui selkämyksen kolmioon,

oli ote niin raju, että koko reki tutisi. Tuntui melkein siltä, kuin hän
olisi sen nostanut suoralla kädellä.
 Sitten hän käytti työntöön toistakin kättään, mitä ei ollut tähän asti
huolinut tehdä, ja kuljetti rekeä edellään, ikäänkuin se olisi ollut vain
leikkikalu hänen rautakourissaan.

Tästä lähtien hän kiiti Saint-Georgesin ympyrien halki vielä

suuremmissa kehissä, niin että reki liikkui kuin notkein ihminen,
kääntyi ja kiersi koko pituudeltaan, ikäänkuin olisi ollut vain
tavallinen kengänpohja, jollaisella seisten Saint-Georges muokkasi
jäätä; huolimatta koostaan, painostaan ja muodostaan oli
kuningattaren reki muodostunut luistimeksi, se eli, liiti ja kieppui kuin
tanssija.

Saint-Georges, joka oli kiemuroissaan sirompi, hienompi ja

säännöllisempi, alkoi pian käydä levottomaksi. Hän luisteli jo toista
tuntia. Filip näki hänen hikoilevan, hänen polvitaipeittensa
vavahtelevan jännityksestä ja päätti hänet voittaa uuvuttamalla. Hän
alkoi siis liikkua toisella tapaa, herkesi piirtämästä ympyriä, joiden
vuoksi oli pakko yhä nostaa rekeä, ja työnsi suoraan eteenpäin. Nyt
reki kiiti vasamaa nopeammin.

Saint-Georges tavoitti hänet pian yhdellä ponnahduksella, mutta

Filip käytti hyväkseen sitä hetkeä, jolloin toinen rynnistys tekee
ensimmäisen vauhdin moninkertaiseksi, ja sai reen liukumaan vielä
koskemattomalle kohdalle jäätä, mutta uusi vauhti oli niin ankara,
että hän itse jäi taemmaksi.

Nyt syöksähti Saint-Georges ottamaan rekeä kiinni, mutta silloin

Filipkin kokosi voimansa, pyyhkäisi luistimen äärimmäisellä särmällä
liitäen kilpailijansa ohitse ja pääsi molemmin käsin tarttumaan
rekeen. Sitten hän jättiläisliikkeellä kiepautti reen ympäri ja lennätti
sitä taas eteenpäin vastakkaiseen suuntaan; sillaikaa Saint-Georges,
joka ei voinut kohta hillitä suunnatonta vauhtiaan, menetti
korvaamatonta aikaa ja jäi kauas taakse.

Ilma kaikui niin vilkkaista suosionhuudoista, että Filip hämillään

punastui. Mutta hän hämmästyi suuresti, kun kuningatar, itsekin
taputettuaan käsiään, kääntyi häneen päin ja sanoi hekumallisen
nääntymyksen äänensävyllä:

"Voi, herra de Taverney, kun nyt voitto jäi teille, armahtakaa,

muuten tapatte minut!"
X

KIUSAAJA

Saatuaan kuningattarelta tämän käskyn eli oikeammin pyynnön,

Filip kiristi teräksisiä jäntereitään, jarrutti polvitaipeillaan, ja reki
pysähtyi jyrkästi niinkuin arabialainen ratsu kinttujen vielä
vavahdellessa erämaan hiekalla.

"Nyt saatte levätä", sanoi kuningatar ja astui reestä hoippuen. "En

olisi ikänä uskonut, että nopea vauhti niin huumaa; olitte vähällä
tehdä minut hulluksi."

Ja todellakin aivan horjuen hän nojasi Filipin käsivarteen.

Ällistyksen kohina, joka kulki pitkin koko tätä kullattua ja

koristettua parvea, oli hänelle merkkinä siitä, että hän taas oli
rikkonut hovisääntöä vastaan, jollaiset virheet olivat suunnattomia
kateuden ja orjamaisuuden silmissä.

Mitä Filipiin tulee, hämmentyi hän tästä erinomaisesta kunniasta

niin, että vavisten häpesi enemmän kuin jos hänen hallitsijattarensa
olisi häntä julkisesti loukannut. Hän loi katseensa maahan, ja sydän
jyskyi ihan haljetakseen. Merkillinen mielenliikutus, varmaankin
kiivaan kulun herättämä, valtasi myös kuningattaren, sillä hän veti
kohta kätensä takaisin ja nojasi sen sijaan neiti de Taverneyhin,
pyytäen päästä istumaan. Hänelle tuotiin telttatuoli.

"Anteeksi, herra de Taverney", sanoi hän Filipille.

Sitten hän lisäsi äkkinäisesti:

"Voi, Jumalani, kuinka onnetonta, kun ympärillä aina on uteliaita…

ja narreja", lisäsi hän vielä hiljaa.

Asianomaiset kamariherrat ja hovinaiset olivat saapuneet hänen

luokseen ja tuijottivat Filipiin, joka hämiään salatakseen riisui
luistimia. Tämän tehtyään Filip väistyi syrjään antaakseen tilaa
hoviväelle. Kuningatar oli hetken aikaa mietteissään, kohotti sitten
päänsä ja sanoi:

"Tunnen vilustuvani, jos jään tähän istumaan; vielä yksi kierros!"

Ja hän astui taas rekeen. Filip odotti turhaan käskyä. Silloin tarjosi
parikymmentä aatelismiestä palvelustaan.

"Ei, kiitos, herrat!" sanoi kuningatar. "Tulkoot tänne palvelijani!"

Kun nämä sitten olivat saapuneet, sanoi hän:

"Hiljaa, hiljaa."

Ja ummistaen silmänsä hän vaipui syviin ajatuksiin. Reki poistui

hiljakseen, niinkuin oli käsketty, perässä parvi kunnianhimoisia,
uteliaita ja kateellisia.

Filip jäi yksin, pyyhkien hikipisaria otsaltaan. Hän etsi katseillaan

Saint-Georgesta, lohduttaakseen tätä tappiosta joillakin
kohteliaisuuksilla. Mutta kilpailija oli saanut sanan suojelijaltaan,
Orleansin herttualta, ja poistunut taistelutantereelta.

Hieman surullisena ja väsyneenä, itsekin melkein kauhistuneena

siitä, mitä oli tapahtunut, oli Filip pysynyt liikkumatta seuraten
silmillään kuningattaren loittonevaa rekeä, kun tunsi jonkun
kosketusta sivullaan. Hän käännähti katsomaan ja näki siinä isänsä.

Ihan kurtistuneena kuin jokin Hoffmannin romaanien hahmo,

kääriytyneenä turkkiin kuin samojeedi, oli pieni ukko kyynäspäällä
sysännyt poikaansa, jottei tarvitsisi vetää käsiään puuhkasta, joka
hänellä riippui kaulaan sidottuna. Hänen joko kylmästä tai riemusta
laajentuneet silmänsä näyttivät Filipistä leimuavan.

"No, poikani, etkö tahdo minua syleillä?"

Ja nämä sanat hän lausui sillä äänensävyllä, jolla kreikkalaisen

atleetin isä olisi kiittänyt poikaansa kilpakentällä saavutetusta
voitosta.

"Kaikesta sydämestäni, rakas isä", vastasi Filip.

Mutta helppo oli huomata, ettei näiden sanain sävy ollut

sopusoinnussa merkityksen kanssa.

"Kas niin, ja nyt kun olet siitä päässyt, riennä joutuin!"

Ja ukko työnsi häntä menemään.

"Mutta minne te tahdotte minun menemään?" kysyi Filip.

"Tietysti tuonne, hitto vie!"

"Tuonneko?"
 "Niin, kuningattaren luo."

"Eikä mitä, isä, ei, kiitos vaan!"

"Miksi ei? Miksi kiitos vaan? Oletko hullu? Etkö tahdo takaisin
kuningattaren luo?"

"En, se ei käy päinsä; te ette ajattele, mitä tahdotte."

"Vai ei käy päinsä! Etkö voi palata kuningattaren luo, joka odottaa
sinua?"

"Joka odottaa minua?"

"Juuri niin; kuningattaren luo, joka ikävöi sinua."

"Ikävöi minua!"

Ja Filip loi parooniin tuikean silmäyksen.

"Uskonpa todellakin, isäni, että unohdatte, mitä sopii puhua",

sanoi hän kylmästi.

"Kummallista, kunniani kautta!" sanoi ukko suoristuen ja polkien

jäätä. "Kuuleppas, Filip, ole niin hyvä ja sano, mistä tulet."

"Monsieur", vastasi toinen surumielisesti, "pelkään tosiaankin, että

minulle tulee varmuus."

"Mikä varmuus?"

"Se, että teette pilaa minusta taikka…"

"Taikka…"
 "Anteeksi, isäni, taikka olette tulemassa hulluksi."

Ukko tarttui nyt poikaansa käsivarteen niin rajusti, että nuori mies
rypisti kipeäntunteesta kulmakarvojaan.

"Kuulkaapa, herra Filip", sanoi ukko. "Amerika on hyvin kaukana

Ranskasta, sen kyllä tiedän."

"Hyvin kaukana", toisti Filip, "mutta en ymmärrä, mitä tarkoitatte;

olkaa hyvä ja selittäkää."

"Se on sellainen maa, jossa ei ole kuningasta eikä kuningatarta."

"Eikä alamaisia."

"Aivan oikein! Eikä alamaisiakaan, herra filosofi. Siitä en kiistele,

eikä se minua vähääkään liikuta, mutta minusta ei ole yhdentekevää,
vaan päinvastoin minua piinaa ja nöyryyttää se, että minäkin pelkään
saavani erään varmuuden."

"Minkä? Kaikissa tapauksissa luulen, että varmuutemme koskevat

ihan eri asioita."

"Minulla näet on se pelko, että sinä olet hölmö, poikani, eikä se ole
luvallista tuonnäköiselle kookkaalle veitikalle. Katso nyt tuonne!"

"Katson kyllä."

"No? Kuningatar kääntyy tänne päin, jo kolmannen kerran. Niin,

herraseni, kuningatar on kolmasti kääntynyt, ja katso, nyt hän taas
kääntyy. Hän etsii… ketä? Herra hölmöä, herra puritaania, Amerikan
herraa! Aha!"
 Ja pieni ukko puri, ei enää hampailla, vaan ikenillä harmaata
peurannahkaista hansikastaan, johon olisi mahtunut kaksikin
sellaista kättä kuin hänen.

"Entä sitten, isäni, vaikka olisikin totta, mikä ei ole luultavaa, että
kuningatar etsii juuri minua?"

"Ah!" toisti ukko tömistäen jalkaansa. "Vaikka olisi totta, sanoo

hän. Mutta siinä miehessä ei ole minun vertani, se ei ole Taverneyn
poika!"

"Vai ei minulla ole suonissani teidän vertanne", mutisi Filip. Sitten

hän sanoi aivan hiljaa, katsahtaen taivasta kohti:

"Pitääkö minun siitä kiittää Jumalaa?"

"Monsieur", sanoi ukko, "sanon sinulle, että kuningatar kaipaa

sinua, hakee sinua."

"Hyvin te näette, isä", vastasi Filip kuivasti.

"Kuuleppa", jatkoi ukko leppeämmin, koettaen hillitä

maltittomuuttaan, "anna minun selittää. Tosin kyllä sinulla on omat
syysi, mutta minulla on kokemusta. Sano nyt, hyvä Filip, oletko mies
vai etkö?"

Filip kohautti hieman hartioitaan eikä vastannut. Kun ukko nyt

huomasi turhaan odottavansa vastausta, rupesi hän, pikemmin
ylenkatseen kuin minkään tarpeen vuoksi, tuijottamaan poikaansa, ja
silloin hän harmikseen sai tämän kasvoissa nähdä sen arvokkuuden,
järkkymättömän maltin, voittamattoman tahdon, jolla Filip oli
varustettu taisteluun kaiken hyvän puolesta. Hän salasi tuskansa,
hyväili puuhkalla nenänsä punaista nipukkaa ja virkkoi niin suloisella
äänellä kuin Orfeus oli puhutellut Tessalian kallioita:

"Filip, ystäväiseni, kuunteleppa nyt, mitä sanon."

"Minusta tuntuu, etten neljännestuntiin ole muuta tehnyt kuin

kuunnellut."

"Kyllä minä sinut, herra amerikalainen, romahutan

majesteettisesta korkeudestasi", ajatteli ukko. "Lienee sinullakin,
jättiläinen, heikko puolesi; kunhan pääsen siihen kiinni vanhoilla
kynsilläni, niin saat nähdä."

Sitten hän sanoi ääneen:

"Erästä asiaa et ole huomannut, Filip."

"Mitä?"

"Erästä seikkaa, joka on kunniaksi lapselliselle mielellesi."

"Antakaa kuulla, isä."

"Asia on se, että sinä tulet Amerikasta, jonne olit lähtenyt siihen
aikaan, kun oli vain kuningas, mutta ei kuningatarta, ellei oteta
lukuun rouva Dubarryta, jollainen majesteetti ei juuri herätä
kunnioitusta. Sitten palaat, näet kuningattaren ja tuumit:
kunnioittakaamme häntä."

"Epäilemättä."

"Lapsi-parka!" sanoi ukko.

 Ja hän peitti suunsa puuhkalla, tukehuttaakseen yskänsä ja
samalla hohotuksensa.

"Kuinka", kysyi Filip, "te surkuttelette minua, että pidän arvossa

kuninkuutta, te Taverney Maison-Rouge, ranskalainen kelpo
aatelismies?"

"Malta, en minä kuninkuudesta puhu, vaan kuningattaresta."

"Teistä siinä on eroa!"

"Totta vie! Mitä kuninkuus on? Kruunu, eikä siihen kajota, hornan
nimessä! Mitä on kuningatar? Nainen, niin juuri, nainen, ja siihen
kajotaan."

"Kajoatteko häneen?" huudahti Filip punastuen suuttumuksesta ja

ylenkatseesta ja liitti näihin sanoihin niin ylpeän liikkeen, ettei
yksikään nainen olisi voinut häntä katsella rakastamatta eikä
yksikään kuningatar ihailematta.

"Sinä et sitä usko, tietysti et. No hyvä, —" sanoi ukko matalalla,
ilkeällä äänellä, hymähtäen riettaasti, "kysy herra de Coignylta, kysy
herra de Lauzunilta, kysy herra de Vaudreuililta."

"Vaiti, vaiti, isä!" huudahti Filip kumeasti, "taikka, kun en näistä

kolmesta herjauksesta voi teitä kolmasti lävistää miekallani, niin
lävistän itseni, sen vannon, ja armotta, heti paikalla!"

Taverney peräytyi askeleen, käännähti ympäri niin kevyesti kuin

Richelieu kolmikymmenvuotiaana, ravisti puuhkaansa ja sanoi:

"Jaa, jaa, elukat ovat tyhmiä: hevonen on aasi, kotka on hanhi,

kukko on kuohilas. Hyvästi, sinusta on ollut huvia! Luulin olevani esi-
isä, jokin Kassander, mutta nyt minussa ilmeneekin jokin Valerus,
Adonis, Apollo. Hyvästi!"

Ja taas hän pyörähti kantapäillään.

Filip oli käynyt synkäksi; hän pysäytti ukon puolikäännöksessä.

"Ettehän ole tarkoittanut, mitä puhutte, isäni?" sanoi hän. "Sillä

jalosukuisen aatelismiehen, kuten teidän, on mahdotonta uskottaa
tuollaisia parjauksia, joiden alkuunpanijat eivät ole vain naisen ja
kuningattaren, vaan samalla kuningasvallan vihollisia."

"Vielä hän epäilee, pahkahupsu!" ivasi Taverney.

"Oletteko puhunut totta, niinkuin puhuisitte Jumalan edessä?"

"Olen kun olenkin."

"Jumalan edessä, jota lähestytte joka päivä!"

Nuori mies oli itse jatkanut niin ylenkatseellisesti keskeyttämäänsä

puhelua; tämän edun huomasi parooni ja astui taas likemmäksi.

"Luulisin", sanoi hän, "että minussa on hiukan aatelismiestä, herra

poikani, ja etten valehtele… aina."

Tämä "aina" tuntui vähän naurettavalta, mutta Filip ei nauranut.

"Te siis arvelette", sanoi Filip, "että kuningattarella on ollut

rakastajia?"

"Mokomakin uutinen!"

"Ne, jotka nimititte?"

 "Ja muita… mistä minä tiedän? Kysy kaupungilta ja hovilta. Täytyy
olla Amerikasta tullut, ellei tiedä, mitä puhutaan."

"Ja kutka puhuvat, monsieur? Kurjat häväistyskirjailijat?"

"Ahaa! Vai pidätkö minua uutistenlevittäjänä?"

"En, ja sehän juuri on onnetonta, että teidän kaltaisenne toistavat

sellaisia häväistyksiä, jotka muuten häipyisivät kuin epäterveelliset
huurut pimittämästä ihaninta aurinkoa. Juuri te ja muut ylimykset,
kun kertaatte näitä huhuja, annatte niille kauhean sitkeyden. Voi,
isäni, älkää Herran tähden enää puhuko semmoisia asioita!"

"Puhun sittenkin."

"Ja miksi niin teette?" huudahti nuori mies jalkaa polkien.

"Siksi", vastasi ukko, takertui poikansa käsivarteen ja katseli häntä

hymyillen kuin paholainen, "että saisin sinut uskomaan olleeni
oikeassa, kun sanoin: Filip, kuningatar kääntyy; kuningatar etsii;
kuningatar ikävöi; riennä, riennä, kuningatar odottaa!"

"Taivaan nimessä", huudahti nuori mies peittäen kasvonsa

käsillään, "vaietkaa, isä, muuten teette minut hulluksi!"

"Todellakaan en sinua ymmärrä, Filip", sanoi ukko. "Onko

rakastuminen rikollista? Sehän todistaa, että ihmisellä on sydän. Eikö
tämän naisen silmistä, äänestä, käytöksestä näy mitä hänellä on
sydämessä? Hän rakastaa, kuuletko? Mutta sinä olet filosofi,
puritaani, kveekari, Amerikan ihminen, sinä et rakasta. Jätä hänet
siis katselemaan, käännähtelemään, odottelemaan, loukkaa häntä,
ylenkatso, hylkää, sinä Filip, nimittäin: Josef de Taverney!"
 Ja nähtyään, mitä nämä julman ivallisesti korostetut sanat
vaikuttivat, riensi pieni ukko tiehensä kuin kiusaaja annettuaan ensi
neuvon rikokseen.

Filip jäi yksin paisunein sydämin, kuohahtelevin miettein; ei

huomannut sitäkään, että oli jo puolen tuntia seissyt kuin naulattuna
yhteen paikkaan, että kuningatar oli lopettanut kierroksensa ja nyt
palasi katsahtaen häneen, kunnes kuningatar ohitse kulkiessaan
huusi saattueensa keskeltä:

"Nyt lienette jo kyllin levännyt, herra de Taverney? Tulkaa siis, ei

täällä kukaan muu niin kuninkaallisesti osaa kuljettaa kuningatarta.
Antakaa tilaa, herrat!"

Filip riensi hänen luokseen sokeana, hurjana, huumaantuneena.

Laskiessaan kätensä reen selkämykseen hän tunsi liekehtivänsä;

kuningatar oli veltosti nojautunut taaksepäin; nuoren miehen sormet
olivat hipaisseet Marie-Antoinetten hiuksia.
XI

SUFFREN

Vastoin hovitapaa oli salaisuus uskollisesti säilynyt Ludvig XVI:n ja

Artoisin kreivin kesken. Kukaan ei tiennyt, mihin aikaan ja miten
herra de Suffren saapuisi.

Kuningas oli illaksi kutsunut peliseurueen. Kello seitsemän hän

astui sisään perheensä prinssien ja prinsessojen kanssa. Kuningas
tuli taluttaen kuninkaallista prinsessaa, joka oli vasta seitsenvuotias.
Seura oli lukuisa ja loistava.

Sillä välin, kun kaikki järjestyivät paikoilleen, lähestyi Artoisin kreivi

hiljaa kuningatarta ja kuiskasi:

"Katsokaapa hieman ympärillenne. Mitä näette?"

Kuningatar silmäili joka taholle, tarkasteli tiheitä kohtia, tutki tyhjät

välit, mutta ei huomannut muuta kuin kaikkialla ystäviä, kaikkialla
palvelijoita ja heidän joukossaan Andréen ja hänen veljensä.

"Täällä näkyy hyvin miellyttäviä kasvoja", vastasi hän.

 "Älkää katselko, keitä meillä on, kälyni, vaan kuka meiltä puuttuu."

"Ahaa, se on kun onkin totta!"

Artoisin kreivi alkoi nauraa.

"Vielä poissa", jatkoi kuningatar. "Voi, pitääkö hänen aina minua

karttaa?"

"Ei", sanoi Artoisin kreivi. "Kuje vain venyy. Monsieur on mennyt

tulliportille odottamaan herra de Suffrenia."

"Mutta sitten en ymmärrä, miksi nauratte, lanko!"

"Vai ette sitä ymmärrä!"

"En ollenkaan; jos Monsieur on tulliportilla vastaanottamassa herra

de Suffrenia, on hän ollut meitä sukkelampi, siinä kaikki, sillä hän
saa ensimmäisenä julkisesti onnitella vierastamme."

"Kas niin, rakas käly", vastasi prinssi yhä nauraen, "te vähäksytte
meidän valtioviisauttamme. Hän on kyllä mennyt Fontainebleaun
tulliportille tapaamaan sankariamme, se on totta, mutta meidän
puolestamme on joku odottamassa samaa sankaria Villejuifin
kievarissa."

"Todellako?"

"Niin että", jatkoi Artoisin kreivi, "Monsieur saa yksin värjötellä

tullipuominsa ääressä, kun taas kuninkaan määräyksestä herra de
Suffren kiertää Pariisin ja saapuu suoraan Versaillesiin, jossa häntä
odotamme."

"Mainiosti keksitty!"
 "Ei ainakaan huonosti, ja siitä olenkin itseeni tyytyväinen.
Ruvetkaa nyt pelaamaan, kälyni!"

Tällä hetkellä oli pelisalissa vähintään sata ylhäisintä henkilöä:

Condén prinssi, Penthièvren ja Trémouillen herttuat, prinsessat.

Kuningas yksin huomasi, että Artoisin kreivi nauratti kuningatarta,

ja ollakseen edes jotenkin mukana heidän salajuonessaan hän loi
heihin hyvin merkitsevän katseen.

Uutinen komentaja de Suffrenin tulosta, kuten jo sanoimme, ei

ollut päässyt leviämään, mutta ei oltu kuitenkaan voitu ehkäistä, että
kaikkien mielissä pyöri jokin aavistus; että jokin salaisuus paljastuisi;
että jotakin uutta tapahtuisi. Jokin outo harrastus valtasi tämän
ylhäisen maailman, jossa pieninkin tapahtuma käy kohta tärkeäksi,
kun hallitsija on paheksuen rypistänyt kulmakarvojaan tai hyväksyen
hymyillyt.

Kuningas, jonka tapana oli pelata vain yhden écun [entinen

kultaraha, arvoltaan 6 livreä; nykyään se merkitsee 3 frangia. —
Suom.] panoksella, rajoittaakseen prinssien ja hoviherrain peliä, ei
huomannut panneensa taskustaan pöydälle kaikki kultarahat.
Kuningatar, näytellen osaansa mainiosti, puhui politiikkaa ja eksytti
seuran huomiota, ollen kovin innostuvinaan peliinsä.

Filip, joka sai ottaa osaa tähän peliin ja istui vastapäätä sisartaan,
nautti yhtaikaa kaikilla aisteillaan tästä tavattomasta, huumaavasta
suosiosta, jolla häntä odottamatta hyväiltiin.

Vastoin tahtoaankin hän muisteli isänsä sanoja. Hän kysyi

itseltään, eikö hänen isänsä, joka oli nähnyt kolme tai neljä
suosikkivaltaa, saattaisi tarkoin tuntea aikojen ja tapojen historiaa;
eikö tämä puritaanisuus, joka läheni jumaloimista, ollut niitä
naurettavaisuuksia, joita hän oli mukanaan tuonut kaukaisista
maista.

Tuo kuningatar, niin runollinen, niin kaunis, niin herttainen — eikö

hän olisikaan muuta kuin erinomainen kiemailija, jonka mieli teki
liittää muistoihinsa yksi intohimo lisää, niinkuin hyönteistutkija
kiinnittää laatikkonsa pohjaan jonkin perhosen välittämättä siitä,
mitä itikka-parka kärsii sydän neulan lävistämänä.

Eikä kuningatar sittenkään ollut tavallinen nainen, jokapäiväinen

luonne. Hänen luomansa katse merkitsi jotakin, hänellä kun aina oli
selvillä joka silmäyksensä kantavuus.

"Coigny, Vaudreuil", toisti Filip, "ovat rakastaneet kuningatarta ja

saaneet vastarakkautta. Voi, miksi tämä parjaus on niin kaamea,
miksi ei ainoakaan valonsäde pujahda tähän syvään hornaan, jota
sanotaan naisen sydämeksi, ja joka kuningattaren sydämenä on
vieläkin syvempi?"

Ja kylliksi pyöriteltyään mielessään näitä kahta nimeä Filip katseli

herroja Coignyta ja Vaudreulia, jotka olivat sattumalta joutuneet
vierekkäin pöydän päähän ja istuivat siellä katsellen aivan toisaalle
kuin missä kuningatar oli, kylmäkiskoisina, melkeinpä
huolimattomina.

Silloin Filip tuumi itsekseen olevan mahdotonta, että nuo kaksi

miestä olivat rakastaneet ja nyt pysyivät noin tyyninä, että he olivat
saaneet rakkautta ja nyt olivat noin huolimattomia. Oi, jos
kuningatar rakastaisi häntä, hullaantuisi hän onnesta; jos kuningatar
rakkautensa unohtaisi, surmaisi hän itsensä epätoivosta.
 Ja herroista de Coignysta ja Vaudreuilista Filip käänsi silmänsä
kuningattareen. Yhä haaveissaan hän tiedusti tältä niin puhtaalta
otsalta, niin käskevältä suulta, niin majesteettiselta katseelta; hän
pyysi tämän naisen kaikkia suloja paljastamaan kuningattaren
salaisuuden.

Ei, ei, pelkkää parjausta kaikki nuo epämääräiset huhut, jotka

alkoivat liikkua kansassa ja joille vain hovin harrastukset, vihat tai
juonet soivat vähänkään tukea.

Näin pitkälle oli Filip päässyt mietteissään, kun henkivartijain

salissa kello löi neljännestä vaille kahdeksan. Samassa kuultiin
vilkasta hälinää.

Mainitusta salista kuului hätäisiä askelia. Pyssynperät jysähtivät

kivilattialle. Äänten tohina tunkeutui raollaan olevasta ovesta ja
herätti kuninkaan huomiota, niin että hän paremmin kuullakseen
käänsi päätään taaksepäin. Sitten hän antoi merkin kuningattarelle,
joka käsitti sen ja kohta lopetti pelin. Kaikki pelaajat ottivat talteen
edessään olevat rahat ja odottivat kuningattaren päätöstä.
Kuningatar siirtyi suureen vastaanottosaliin, jonne kuningas oli jo
ehtinyt mennä.

Kuningatarta lähestyi meriministeri de Castriesin ajutantti ja

kuiskasi hänelle jotakin.

"Hyvä", vastasi kuningas, "menkää!" Sitten hän sanoi

kuningattarelle:
"Kaikki käy hyvin."

Jokainen loi naapuriinsa kysyvän silmäyksen; nuo sanat "kaikki käy

hyvin" antoivat kaikille paljon ajattelemista. Äkkiä astui saliin marski
de Castries ja kysyi äänekkäästi: "Suvaitseeko teidän majesteettinne
ottaa vastaan komentaja de Suffrenin, joka saapuu Toulonista?"

Kun tämä nimi lausuttiin kovalla, riemastuneella, voitollisella

äänellä, herätti se seurassa kuvaamattoman hälinän.

"Kyllä, monsieur", vastasi kuningas, "hyvin mielelläni."

Herra de Castries poistui. Melkein kaikki syöksyivät nyt ovelle päin,

josta ministeri juuri oli mennyt.

Ei tarvita montakaan sanaa selittääksemme, miksi Ranska oli näin

myötätuntoinen herra de Suffrenille, miksi kuningas, kuningatar ja
kuninkaalliset prinssit pitivät niin tärkeänä saada ensimmäisinä häntä
tervehtiä. Suffren on aitoranskalainen nimi, niinkuin Turenne,
Catinat, Jean-Bart.

Siitä saakka, kun sodittiin Englannin kanssa, tai oikeammin

viimeisestä taistelukaudesta rauhantekoon asti oli komentaja de
Suffren suorittanut seitsemän meritaistelua ilman ainoatakaan
tappiota; hän oli vallannut Trinquemalen ja Gondelourin, turvannut
ranskalaisten alusmaat, puhdistanut meren ja opettanut intialaiselle
ruhtinaalle Hyder-Alille, että Ranska on Euroopan valloista etevin.
Meriammattinsa ohella hän oli osoittanut taitavan ja rehellisen
välittäjän valtioviisautta, soturin urhoollisuutta ja taktiikkaa, älykkään
hallitusmiehen kykyä. Rohkeana, uupumatonna, ylpeänä, kun asia
koski Ranskan lipun kunniaa, hän oli väsyttänyt englantilaisia maalla
ja merellä niin, etteivät nämä kopeat merimiehet uskaltaneet
kehittää voittonsa alkua loppuun tai karata Suffrenin kimppuun, kun
jalopeura näytti hampaitaan.
 Taistelun jälkeen, jossa hän oli pannut henkensä alttiiksi yhtä
uljaasti kuin mikä tahansa matruusi, hänet oli nähty inhimillisenä,
jalomielisenä, sääliväisenä. Komentaja de Suffrenissa Ranska taas
tapasi oikean meriurhon perikuvan, jollainen oli Jean-Bartin ja
Duguay-Trouinin ajoista jäänyt hieman unohduksiin.

Emme yritäkään kuvata sitä hälinää ja ihastusta, jonka hänen

tulonsa
Versaillesiin herätti tähän juhlaan kutsutuissa ylimyksissä.

Suffren oli kuudenkuudetta ikäinen mies, pyylevä ja tanakka,

katseissa tulta, liikkeissä ylevyyttä ja luontevuutta. Ketteränä, vaikka
oli lihava, arvokkaana, vaikka oli vilkasliikkeinen, hän piti ylväästi
pystyssä tukkaansa eli oikeammin harjaansa; kun hän oli tottunut
selviämään kaikista pulmista, oli hän nytkin matkavaunuissa saanut
vaihdetuksi pukua ja käherretyksi hiuksensa.

Hänen yllään oli sininen, kullalla kirjailtu takki, punaiset liivit,

siniset housut; kaulaansa hän oli jättänyt sotilaskauluksen, jota
vasten hänen mahtava leukansa pullistui tavattoman ison pään
arvokkaana liitteenä.

Hänen astuessaan henkivartijain saliin oli joku kuiskannut pari

sanaa herra de Castriesille, joka maltitonna käveli edestakaisin, ja
silloin tämä oli huutanut:

"Herra de Suffren, hyvät herrat!"

Henkivartijat tarttuivat heti musketteihinsa ja asettuivat itsestään

riviin, ikäänkuin olisi tullut Ranskan kuningas, ja komentajan
sivuutettua heidät he järjestyivät hänen taakseen, säännöllisesti
neljä vierekkäin, ikäänkuin hänen seurueekseen. Herra de Suffren
puristi ministerin kättä ja tahtoi häntä syleillä, mutta toinen torjui
sävyisästi sanoen:

"Ei, ei, herra, en tahdo eräältä itseäni arvokkaammalta riistää

onnea saada ensimmäisenä teitä syleillä."

Ja sitten hän vei herra de Suffrenin Ludvig XVI:n luo.

"Herra komentaja!" huudahti kuningas säteillen, nähdessään

hänet; "tervetuloa Versaillesiin! Tuotte tänne kunniaa, tuotte
kaikkea, mitä sankarit voivat maan päällä aikalaisilleen antaa;
jälkimaailmasta en puhu, se on teidän omanne. Syleilkää minua,
herra komentaja!"

Herra de Suffren oli notkistanut polvea, mutta kuningas

sydämellisesti, että koko seurassa kulki riemun kohina. Arvonanto
majesteettia kohtaan esti kuitenkin puhkeamasta hyvä-huutoihin.

Kuningas kääntyi kuningattareen päin.

"Madame", sanoi hän, "tässä on herra de Suffren, Trinquemalen ja

Condelourin voittaja, englantilaisten naapuriemme kauhu, minun
Jean-Bartini!"

"Monsieur", sanoi kuningatar, "minun asiani ei ole pitää teille

ylistyspuhetta, mutta tietäkää, että jokainen Ranskan kunniaksi
ampumanne kanuunanlaukaus on sydäntäni sykähdyttänyt ihailulla
ja kiitollisuudella teitä kohtaan."

Tuskin oli kuningatar puhunut, kun Artoisin kreivi läheni mukanaan

poikansa, Angoulêmen herttua.
 "Poikani", sanoi hän, "tuossa näet sankarin. Katsele tai kasti, sillä
sellainen on harvinaisuus."

"Monseigneur", vastasi pikku prinssi isälleen, "äsken luin

Plutarkoksessa suurista miehistä, mutta en nähnyt heitä. Kiitos, että
näytitte de Suffrenin!"

Ympärillä olevien sorinasta saattoi lapsi käsittää lausuneensa

sanoja, jotka jäisivät muistiin.

Sitten kuningas tarttui herra de Suffrenin käsivarteen ja aikoi viedä

hänet työhuoneeseensa saadakseen maantieteilijänä puhella hänen
kanssaan matkoista ja sotaretken vaiheista. Mutta herra de Suffren
esteli kunnioittavasti.

"Sire", sanoi hän, "koska teidän majesteettinne katsoo hyväksi

minulle osoittaa niin suurta kunniaa, niin suvainnette, että…"

"Pyydättekö jotakin, herra de Suffren?"

"Sire, eräs upseerini on niin ilmeisesti rikkonut sotakuria vastaan,

että mielestäni vain teidän majesteettinne voi asiassa tuomita."

"Kah, herra de Suffren", sanoi kuningas, "toivoin ensi pyyntönne

koskevan jotakin suosionosoitusta eikä rangaistusta."

"Sire, minulla oli kunnia sanoa, että teidän majesteettinne on itse

päättävä, mitä on tehtävä."

"Kuuntelen."

"Viimeisessä taistelussa se upseeri, jota tarkoitan, palveli Sévère-

laivalla."
 "Sillä, joka laski lippunsa", huomautti kuningas rypistäen
kulmakarvojaan.

"Sire, sen kapteeni oli todellakin laskenut lippunsa", myönsi herra

de Suffren kumartaen, "ja englantilainen amiraali, sir Hughes, oli jo
lähettänyt veneen ottamaan kaapatun laivan haltuunsa, mutta kun
Sévèren luutnantti, joka valvoi välikannen pattereita, oli huomannut
ammunnan lakanneen ja itsekin saanut käskyn lopettaa kanuuniensa
tulen, kiirehti hän ylös kannelle ja näki siellä lipun lasketuksi ja
kapteenin valmiina antautumaan. Pyydän teidän majesteettianne
suomaan anteeksi, mutta silloin hänessä kuohahti ranskalainen veri.
Hän tarttui lippuun, johon hänen kätensä ulottui, sieppasi vasaran ja
käskien taas aloittaa tulen ryhtyi naulaamaan lippua kiinni viirin alle.
Juuri tämä seikka pelasti Sévèren teidän majesteetillenne."

"Kaunis temppu!" sanoi kuningas.

"Uljas teko!" huudahti kuningatar.

"Niin, sire, niin, madame; mutta raskas rikkomus kuria vastaan.

Käskyn oli antanut kapteeni, luutnantin oli toteltava. Pyydän siis
armoa tälle upseerille, sire, sitäkin hartaammin, kun hän on
sisarenpoikani."

"Sisarenpoikanne!" ihmetteli kuningas, "ettekä ole hänestä

puhunut minulle!"

"En, en kuninkaalle; mutta minulla on ollut kunnia antaa siitä

selostus meriministerille pyytäen, ettei hän mitään mainitsisi teidän
majesteetillenne, ennenkuin toimittaisin syylliselle armahduksen."
Welcome to our website – the perfect destination for book lovers and
knowledge seekers. We believe that every book holds a new world,
offering opportunities for learning, discovery, and personal growth.
That’s why we are dedicated to bringing you a diverse collection of
books, ranging from classic literature and specialized publications to
self-development guides and children's books.

More than just a book-buying platform, we strive to be a bridge

connecting you with timeless cultural and intellectual values. With an
elegant, user-friendly interface and a smart search system, you can
quickly find the books that best suit your interests. Additionally,
our special promotions and home delivery services help you save time
and fully enjoy the joy of reading.

Join us on a journey of knowledge exploration, passion nurturing, and

personal growth every day!

ebookbell.com