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Design of Function Circuits with
555 Timer Integrated Circuit

This text discusses sigma-­delta-­type function circuits, peak detecting function

circuits, and peak sampling function circuits in a detailed manner. It further
covers all the function circuits designed by using the basic principles of the
six building blocks: integrator, the 555 timer integrated circuit, switch, low
pass filter, peak detector, and sample and hold circuit. It is a useful reference
text for senior undergraduate and graduate students in the fields of electrical
engineering and electronics and communication engineering. This book is
accompanied by teaching resources, including a solution manual for the
instructors.

• Discusses function circuits such as multipliers, dividers, and multiplier

cum dividers using the 555 timer.
• Explains how function circuits are developed with a simple integrator
and the 555 timer.
• Extends the applications of 555 timers to perform in function circuits.
• Covers important topics such as monostable multivibrator, inverting
amplifier, and peak responding divider.
• Presents function circuit conversion such as multiplier to square root
and divider to a multiplier.

This comprehensive book covers the design of function circuits with the
help of 555 timer integrated circuits in a single volume. It further discusses
how derived function circuits are implemented with integrator, comparator,
low pass filter, peak detector, and sample and hold circuits.
Design of Function Circuits
with 555 Timer Integrated
Circuit

K. C. Selvam
First edition published 2023
by CRC Press
6000 Broken Sound Parkway NW, Suite 300, Boca Raton, FL 33487–2742
and by CRC Press
4 Park Square, Milton Park, Abingdon, Oxon, OX14 4RN
CRC Press is an imprint of Taylor & Francis Group, LLC
© 2023, K. C. Selvam
Reasonable efforts have been made to publish reliable data
and information, but the author and publisher cannot assume
responsibility for the validity of all materials or the consequences
of their use. The authors and publishers have attempted to trace
the copyright holders of all material reproduced in this publication
and apologize to copyright holders if permission to publish in this
form has not been obtained. If any copyright material has not been
acknowledged please write and let us know so we may rectify in any
future reprint.
Except as permitted under U.S. Copyright Law, no part of this book
may be reprinted, reproduced, transmitted, or utilized in any form by
any electronic, mechanical, or other means, now known or hereafter
invented, including photocopying, microfilming, and recording, or
in any information storage or retrieval system, without written
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For permission to photocopy or use material electronically from this
work, access www.copyright.com or contact the Copyright Clearance
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Trademark notice: Product or corporate names may be trademarks
or registered trademarks and are used only for identification and
explanation without intent to infringe.
Library of Congress Cataloging‑in‑Publication Data
Names: Selvam, K. C., author.
Title: Design of function circuits with 555 timer integrated circuit /
K.C. Selvam.
Other titles: Design of function circuits with five hundred fifty-five
timer integrated circuit
Description: First edition. | Boca Raton : CRC Press, [2023] | Includes
bibliographical references and index.
Identifiers: LCCN 2022037988 (print) | LCCN 2022037989 (ebook) |
ISBN 9781032391700 (hbk) | ISBN 9781032424798 (pbk) |
ISBN 9781003362968 (ebk)
Subjects: LCSH: Function generators (Electronic instruments)—Design
and construction. | 555 timer IC (Integrated circuits)
Classification: LCC TK7895.F8 S45 2023 (print) | LCC TK7895.F8
(ebook) | DDC 621.3815—dc23/eng/20221107
LC record available at https://lccn.loc.gov/2022037988
LC ebook record available at https://lccn.loc.gov/2022037989
ISBN: 978-1-032-39170-0 (hbk)
ISBN: 978-1-032-42479-8 (pbk)
ISBN: 978-1-003-36296-8 (ebk)
DOI: 10.1201/9781003362968
Typeset in Sabon
by Apex CoVantage, LLC
Dedicated to my loving wife
S. Latha
Contents

Preface xiii
Author Biography xv
List of Useful Notations xvi
List of Abbreviations xvii
Introduction to the 555 Timer xix

1 Time Division Multipliers—Multiplexing 1

1.1 Saw Tooth Wave Based Time Division
Multipliers 1
1.2 Triangular Wave Referenced Time Division
Multipliers 2
1.3 Time Division Multiplier with No Reference—
Type I 4
1.4 Time Division Multiplier No Reference—
Type II 7
1.5 Time Division Multiplier Using 555 Astable
Multivibrator 9
1.5.1 Time Division Multiplier Using 555 Astable
Multivibrator—Type I 9
1.5.2 Multiplier from 555 Astable Multivibrator—
Type II 11
1.6 Multiplier from 555 Monostable Multivibrator 13
1.6.1 Multiplier from 555 Monostable
Multivibrator—Type I 13
1.6.2 Multiplier from 555 Monostable
Multivibrator—Type II 15
viii Contents

2 Time Division Multipliers—Switching 19

2.1 Saw Tooth Wave Based Time Division Multipliers 19
2.2 Triangular Wave Referenced Time Division
Multipliers 21
2.3 Time Division Multiplier with No Reference—
Type I 23
2.4 Time Division Multiplier No Reference—Type II 25
2.5 Multiplier from 555 Astable Multivibrator 28
2.5.1 Multiplier from 555 Astable Multivibrator—
Type I 28
2.5.2 Multiplier from 555 Astable Multivibrator—
Type II 29
2.6 Multiplier from 555 Monostable Multivibrator 31
2.6.1 Type I 31
2.6.2 Multiplier from 555 Monostable Multivibrator—
Type II 33

3 Time Division Dividers (TDD)—Multiplexing 37

3.1 Saw Tooth Wave Based Time Division Dividers 37
3.2 Triangular Wave Referenced Time Division
Dividers 39
3.3 Time Division Divider with No Reference—
Type I 41
3.4 Time Division Divider with No Reference—
Type II 43
3.5 Divider from 555 Astable Multivibrator 46
3.5.1 Type I 46
3.5.2 Divider from 555 Astable Multivibrator—
Type II 47
3.6 Divider from 555 Monostable Multivibrator 49
3.6.1 Type I 49
3.6.2 Divider from 555 Monostable Multivibrator—
Type II 51

4 Time Division Dividers (TDD)—Switching 55

4.1 Saw Tooth Wave Based Time Division Dividers 55
4.2 Triangular Wave Referenced Time Division Dividers 57
4.3 Time Division Divider with No Reference—Type I 59
 Contents ix

4.4 Time Division Divider with No Reference—Type II 61

4.5 Divider from 555 Astable Multivibrator 63
4.5.1 Type I 63
4.5.2 Divider from 555 Astable Multivibrator—
Type II 65
4.6 Divider from 555 Monostable Multivibrator 67
4.6.1 Type I 67
4.6.2 Divider from 555 Monostable Multivibrator 69

5 Time Division Multipliers cum Dividers (MCDs)—

Multiplexing73
5.1 Saw Tooth Wave Referenced MCDS 73
5.1.1 Saw Tooth Wave Referenced MCD—Type I—
Double Multiplexing and Averaging 73
5.1.2 Saw Tooth Based MCD—Type II 75
5.1.3 Saw Tooth Wave Referenced MCD—
Type III 77
5.2 Triangular Wave Based Time Division MCDs 79
5.2.1 Type I 79
5.2.2 Triangular Wave Based Time Division MCD—
Type II 81
5.2.3 Triangular Wave Based MCD—Type III 83
5.3 Multiplier cum Dividers from 555 Astable
Multivibrator 86
5.3.1 Type I 86
5.3.2 Type II Square Wave Referenced MCD 87
5.4 Multiplier cum Divider from 555 Monostable Multivibrator 89

6 Time Division Multiplier cum Divider—Switching 93

6.1 Saw Tooth Wave Based MCDS 93
6.1.1 Saw Tooth Wave Based Double Switching-­
Averaging Time Division MCD 93
6.1.2 Saw Tooth Wave Referenced Time Division
Multiply-­Divide MCD 96
6.1.3 Saw Tooth Wave Referenced Time Division
Divide-­Multiply MCD 99
6.2 Triangular Wave Based MCDS 102
6.2.1 Time Division MCD 102
x Contents

6.2.2 Divide-­Multiply Time Division MCD 105

6.2.3 Multiply-­Divide Time Division MCD 108
6.3 Multiplier cum Divider from 555 Astable
Multivibrator 111
6.3.1 Multiplier cum Divider from 555 Astable
Multivibrator—Type I 111
6.3.2 Square Wave Referenced MCD 113
6.4 Multiplier cum Divider from 555 Monostable
Multivibrator 115

7 Peak Responding Multiplier cum Dividers—Multiplexing 119

7.1 Double Single Slope Peak Responding MCDs 119
7.1.1 Double Single Slope Peak Responding
MCDs—Type I 119
7.1.2 Double Single Slope—Type II 122
7.2 Double Dual Slope Peak Responding MCD
with Flip Flop 125
7.3 Pulse Width Integrated Peak Responding MCD 128
7.4 Pulse Position Peak Responding MCDs 132

8 Peak Responding Multiplier cum Dividers—Switching 137

8.1 Double Single Slope Peak Responding MCD 137
8.1.1 Type I 137
8.1.2 Double Single Slope—Type II 140
8.2 Double Dual Slope Peak Responding MCD with
Flip Flop 143
8.3 Pulse Width Integrated Peak Responding MCD 146
8.4 Pulse Position Peak Responding MCDs 149

9 Time Division Square Rooters (TDD)—Multiplexing 155

9.1 Saw Tooth Wave Based Time Division Square
Rooters 155
9.2 Triangular Wave Referenced Time Division Square
Rooters 157
9.3 Time Division Square Rooter with No Reference—
Type I 159
 Contents xi

9.4 Time Division Square Rooter with No Reference—

Type II 161
9.5 Square Rooter from 555 Astable Multivibrator 163
9.5.1 Type I 163
9.5.2 Square Rooter from 555 Astable Multivibrator—
Type II 164
9.6 Square Rooter from 555 Monostable Multivibrator 166
9.6.1 Type I 166
9.6.2 Square Rooter from 555 Monostable
Multivibrator—Type II 168

10 Time Division Square Rooters (TDSR)—Switching 173

10.1 Saw Tooth Wave Based Time Division Square
Rooters 173
10.2 Triangular Wave Referenced Time Division Square
Rooters 175
10.3 Time Division Square Rooter with No Reference—
Type I 177
10.4 Time Division Square Rooter with No Reference—
Type II 179
10.5 Square Rooter from 555 Astable Multivibrator 181
10.5.1 Type I 181
10.5.2 Square Rooter from 555 Astable
Multivibrator—Type II 183
10.6 Square Rooter from 555 Monostable Multivibrator 184
10.6.1 Type I 184
10.6.2 Square Rooter from 555 Monostable
Multivibrator—Type II 186

11 Multiplexing Time Division Vector Magnitude

Circuits—Part I 191
11.1 Saw Tooth Wave Referenced VMCs 191
11.2 Triangular Wave Based Time Division VMCs 193
11.3 VMC from 555 Astable Multivibrator 195
11.4 Square Wave Referenced VMC 197
11.5 VMC from 555 Monostable Multivibrator 200
11.6 Time Division VMC with No Reference 202
xii Contents

12 Multiplexing Time Division VMC—Part II 207

12.1 Time Division VMC with No Reference—Type I 207
12.2 Time Division VMC with no Reference—Type II 210
12.3 Time Division VMC with No Reference—Type III 211
12.4 Time Division VMC with No Reference—Type IV 213
12.5 Time Division VMC with No Reference—Type V 215
12.6 Time Division VMC with No Reference—Type VI 218

Index221
Preface

After writing three books and publishing them with CRC Press, Taylor &
Francis, I found that the very popular timer IC 555 can be used to perform
function circuits. I worked on that, got useful results, and decided to write
another book, and this is the result. Earlier, the 555 timer IC was used for
timing and control applications, and now it can also use to perform func-
tion circuits.
I am highly indebted to my:

• Mentor, Prof. Dr. V.G.K. Murti who taught me about function circuits.
• Philosopher, Prof. Dr. P. Sankaran who taught me measurements and
instrumentation.
• Teacher, Prof. Dr. K. Radha Krishna Rao who taught me operational
amplifiers.
• Gurunather, Prof. Dr. V. Jagadeesh Kumar who guided me in the proper
way of the scientific world.
• Trainer, Dr. M. Kumaravel who trained me to do experiments with
op-­amps.
• Director, Prof. Dr. Kamakoti who motivated me to do this work.
• Encourager, Prof. Dr. Enakshi Bhattacharya who encouraged me to get
this result.
• Leader, Prof. Dr. Devendra Jalihal who kept me in a happy and peaceful
official atmosphere.
• Supervisor, Prof. Dr. David Koil Pillai who supervised all my research
work at IIT Madras.

I thank Dr. Gauravjeet Singh Reen, Senior Commissioning Editor, Taylor &
Francis, CRC Press who has shown keen interest in publishing all my theory
and concepts on function circuits. His hard work in making this book pos-
sible is commendable.
I also thank my friends Prof. Dr. R. Sarathi, Dr. Balaji Srinivasan, Dr. T.
G. Venkatesh, Dr. Bharath Bhikkaji, Dr. Bobey George, Dr. S. Anirudhan,
Dr. Aravind, Mrs. T. Padmavathy, Mrs. Sulochana, and Mrs. Karthiayini
xiv Preface

for their constant encouragement throughout my research work. I thank all

other staff, students, and faculty of the Electrical Engineering Department,
Indian Institute of Technology–Madras, for their immense help during the
experimental setups, manuscript preparation, and proofreading.
Author Biography

Dr. K. C. Selvam was born on April 2, 1968, in Krishnagiri district of Tamil

Nadu State, India. He obtained a diploma in electronics and communication
engineering from the government polytechnic college, Krishnagiri, Tamil Nadu,
India, in 1986. He graduated from the Institution of Electronics and Telecom-
munication Engineers, New Delhi, in 1994. He obtained an honorary PhD
degree from the University of Swahili, Government of Panama, in the year 2020.
He has been conducting research and development work for the past
33 years and has published more than 33 research papers in various national
and international journals. He also published the following technical and
scientific books in international publishers.

Design of Analog Multipliers Using Operational Amplifiers (CRC Press,

Taylor & Francis, New York and London, July 2019), DOI:10.1201/
9780429277450, ISBN: 9780429277450.
Multiplier-­
cum-­Divider Circuits; Principles, Design and Applications
(CRC Press, Taylor & Francis, New York and London June 2021),
DOI:10.1201/9781003168515, ISBN: 9781003168515.
Analog Function Circuits: Fundamentals, Principles, Design and Applica-
tions (CRC Press, Taylor & Francis, New York and London, Decem-
ber 2021), ISBN 9781032081601.
Design of Function Circuits with 555 Timer IC (Accepted and to be pub-
lished in CRC Press, Taylor & Francis).
Principles of Function Circuits (Lambert Academic Publishing, Germany),
ISBN-­13: 9786200532411.
Analog Dividing Circuits (Lambert Academic Publishing, Germany), SBN-­
13: 978–6200653987, ISBN-­10: 6200653984.

He got Best Paper Award by IETE in 1996 and the Students Journal Award
by IETE in 2017. In 2021, he received the Life Time Achievement Award
from the Institute of Researchers, Wayanad, Kerala, India. At present he is
working as a scientific staffer in the Department of Electrical Engineering,
Indian Institute of Technology–Madras, India.
Useful Notations

V1 First input voltage

V2 Second input voltage
V3 Third input voltage
VO Output voltage
VR Reference voltage/peak value of first saw tooth waveform
VT Peak value of first triangular waveform
VP Peak value of second triangular wave/saw tooth wave
VC Comparator 1 output voltage in the first saw tooth/triangular wave
generator
VM Comparator 2 output voltage by comparing saw tooth/triangular
waves with one input voltage
VN Low pass filter input signal
VS1 First generated saw tooth wave
VS2 Second generated saw tooth wave
VT1 First generated triangular wave
VT2 Second generated triangular wave
VS Sampling pulse
V1′ Slightly less than V1 voltage
V2′ Slightly less than V2 voltage
Abbreviations

TDM Time division multiplier

MTDM Multiplexing time division multiplier
STDM Switching time division multiplier
PRM Peak responding multiplier
MPRM Multiplexing peak responding multiplier
SPRM Switching peak responding multiplier
PDM Peak detecting multiplier
MPDM Multiplexing peak detecting multiplier
SPDM Switching peak detecting multiplier
PSM Peak sampling multiplier
MPSM Multiplexing peak sampling multiplier
SPSM Switching peak sampling multiplier
PPRM Pulse position responding multiplier
PPDM Pulse position detecting multiplier
PPSM Pulse position sampling multiplier
TDD Time division divider
MTDD Multiplexing time division divider
STDD Switching time division divider
PRD Peak responding divider
MPRD Multiplexing peak responding divider
SPRD Switching peak responding divider
PDD Peak detecting divider
MPDD Multiplexing peak detecting divider
SPDD Switching peak detecting divider
PSD Peak sampling divider
MPSD Multiplexing peak sampling divider
SPSD Switching peak sampling divider
PPRD Pulse position responding divider
PPDD Pulse position detecting divider
PPSD Pulse position sampling divider
TDMCD Time division multiplier cum divider
MTDMCD Multiplexing time division multiplier cum divider
xviii Abbreviations

STDMCD Switching time division multiplier cum divider

PRMCD Peak responding multiplier cum divider
MPRMCD Multiplexing peak responding multiplier cum divider
SPRMCD Switching peak responding multiplier cum divider
PDMCD Peak detecting multiplier cum divider
MPDMCD Multiplexing peak detecting multiplier cum divider
SPDMCD Switching peak detecting multiplier cum divider
PSMCD Peak sampling multiplier cum divider
MPSMCD Multiplexing peak sampling multiplier cum divider
SPSMCD Switching peak sampling multiplier cum divider
PPRMCD Pulse position responding multiplier cum divider
PPDMCD Pulse position detecting multiplier cum divider
PPSMCD Pulse position sampling multiplier cum divider
Introduction to the 555 Timer

Figure 0.1 shows the functional diagram of the 555 timer. The resistors R1,
R2, and R3 are used as voltage dividers and provide voltage references (1)
2VCC/3 for the upper comparator CMP1 and (2) VCC/3 for the lower com-
parator CMP2.
Initially when the power supply is switched on, the output of the upper
comparator CMP1 will be LOW, i.e., R = 0, and the output of the lower
comparator CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are Q = 1
and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is OFF,
and hence the discharge pin 7 is at the open position.
With the threshold pin 6 and trigger pin 2 tied together, a rising voltage is
applied to these connected pins 2 and 6. When the rising voltage is increased
above 2 VCC/3, the output of the upper comparator CMP1 becomes HIGH,
i.e., R = 1, and the output of the lower comparator CMP2 becomes LOW,
i.e., S = 0. The flip flop outputs are Q = 0 and Q′ = 1. The timer output at
pin 3 will be LOW, transistor Q1 is ON, and hence the discharge pin 7 is at
GND potential.

Figure 0.1 Functional diagram of the 555 timer.

xx Introduction to the 555 Timer

Table 0.1 States of the 555 Timer

Sl. No. Trigger (pin 2) Threshold (pin 6) Output (pin 3) Discharge (pin 7)

1 Below VCC/3 Below 2 VCC/3 HIGH OPEN

2 Below VCC/3 Above 2 VCC/3 Last state remains Last state remains
3 Above VCC/3 Below 2 VCC/3 Last state remains Last state remains
4 Above VCC/3 Above 2 VCC/3 LOW GROUND

Now let us change the rising voltage in to a falling voltage. When the fall-
ing voltage goes below 1/3 VCC, the output of the upper comparator CMP1
becomes LOW, i.e., R = 0, the output of lower comparator CMP2 becomes
HIGH, i.e., S = 1. The flip flop outputs are Q = 1 and Q′ = 0. The timer
output at pin 3 will be HIGH, transistor Q1 is OFF, and hence the discharge
pin 7 is at the open position.
The reset pin 4 is used to reset the flip flop if there are any overrides in
the operation. The transistor Q2 is working as a buffer to isolate the reset
input from the flip flop and transistor Q1. The transistor Q2 is driven by an
internal reference voltage VREF obtained from VCC. The different operation
states of the 555 timer are shown in Table 0.1.
Chapter 1

Time Division Multipliers—

Multiplexing

1.1 SAW TOOTH WAVE BASED TIME DIVISION MULTIPLIERS

The circuit diagrams of saw tooth wave based time division multipliers
are shown in Figure 1.1, and their associated waveforms are shown in Fig-
ure 1.2. A saw tooth wave VS1 of peak value VR and time period T is gener-
ated by the 555 timer.
In the circuits of Figure 1.1, the comparator OA2 compares the saw tooth
wave VS1 of peak value VR with the input voltage V1 and produces a rect-
angular waveform VM at its output. The ON time δ T of this rectangular
waveform VM is given as

V1
δT = T (1.1)
VR

The rectangular pulse VM controls the multiplexer M1. When VM is HIGH,

another input voltage V2 is connected to the R3C2 low pass filter (‘ay’ is
connected to ‘a’). When VM is LOW, zero voltage is connected to the R3C2
low pass filter (‘ax’ is connected to ‘a’). Another rectangular pulse VN with
maximum value of V2 is generated at the multiplexer M1 output. The R3C2
low pass filter gives the average value of this pulse train VN and is given as

δT
1
VO = V2 dt (1.2)
T 0

V2
VO = δT (1.3)
T

Equation (1.1) in (1.3) gives

V1 V2
VO = (1.4)
VR

where VR = 2/3 VCC.

DOI: 10.1201/9781003362968-1
2 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.1 (a) Saw tooth wave based time division multiplier—type I. (b) Saw tooth wave
based time division multiplier—type II.

1.2 TRIANGULAR WAVE REFERENCED TIME DIVISION

MULTIPLIERS
The circuit diagrams of triangular wave based multipliers are shown in Fig-
ure 1.3, and their associated waveforms are shown in Figure 1.4. In Fig-
ure 1.3(a), a triangular wave VT1 with ±VT peak to peak value and time
period T is generated by the 555 timer.
 Time Division Multipliers—Multiplexing 3

Figure 1.2 Associated waveforms of Figure 1.1.

Figure 1.3 (a) Triangular wave based multiplier—type I. (b) Triangular wave based multiplier—
type II.

One input voltage V1 is compared with the generated triangular wave

VT1 by the comparator on OA2. An asymmetrical rectangular waveform VM
is generated at the comparator OA2 output. From the waveforms shown in
Figure 1.4, it is observed that
4 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.4 Associated waveforms of Figure 1.3(a) and (b).

VT - V1 V + V1
T1 = T, T2 = T T, T = T1 + T2 (1.5)
2VT 2VT

This rectangular wave VM is given as control input to the multiplexer M1.

The multiplexer M1 connects the other input voltage +V2 during T2 (‘ay’ is
connected to ‘a’) and −V2 during T1 (‘ax’ is connected to ‘a’). Another rectan-
gular asymmetrical wave VN with peak to peak value of ±V2 is generated at
the multiplexer M1 output. The R3C2 low pass filter gives the average value
of the pulse train VN, which is given as

T2 T1 + T2
1 V2
VO = V2 dt + ( -V2 ) dt = (T2 - T1 ) (1.6)
T O T2
T

Equation (1.5) in (1.6) gives

V1 V2
VO = (1.7)
VT

where VT = VCC /3 .(1.8)

1.3 TIME DIVISION MULTIPLIER WITH NO

REFERENCE—TYPE I
The multipliers using the time division principle without using any refer-
ence clock is shown in Figure 1.5, and its associated waveforms are shown
in Figure 1.6.
 Time Division Multipliers—Multiplexing 5

Figure 1.5 Time division multiplier without reference clock—type I.

Figure 1.6 Associated waveforms of Figure 1.5.

Initially when the 555 timer output is HIGH, the inverting amplifier OA3
gives −VSAT to the differential integrator composed by resistor R1, capacitor
C1, and op-­amp OA1. The output of the differential integrator will be
6 Design of Function Circuits with 555 Timer Integrated Circuit

1
VT1 = (V1 + VSAT )dt
R1C1
(VSAT + V1 )
VT1 = t (1.9)
R1C1

The output of the differential integrator rises toward positive saturation,

and when it reaches the voltage level of +VT, the 555 timer output becomes
LOW. The inverting amplifier OA3 gives +VSAT to the differential integrator
composed of resistor R1, capacitor C1 and op-­amp OA1. Now the output of
the differential integrator will be

1
VT1 = (V1 - VSAT )dt
R1C1
(VSAT - V1 )
VT1 = - t (1.10)
R1C1

The output of the differential integrator reverses toward negative satu-

ration, and when it reaches the voltage level −VT, the 555 timer output
becomes HIGH, and the cycle therefore repeats, to give an asymmetrical
rectangular wave VC at the output of the 555 timer.

VCC
VT = (1.11)
3

From the waveforms shown in Figure 1.6, it is observed that

VSAT - V1 V + V1
T1 = T, T2 = SAT T, T = T1 + T2 (1.12)
2VSAT 2VSAT

The asymmetrical rectangular wave VC controls the multiplexer M2. The

multiplexer M2 connects +V2 during the OFF time VC (‘bx’ is connected to
‘b’) and −V2 during the ON time of the rectangular wave VC (‘by’ is con-
nected to ‘b’). Another rectangular wave VN is generated at the multiplexer
M2 output. The R2C2 low pass filter gives the average value of this pulse
train VN and is given as
T2 T1 + T2
1
VO = V2 dt + ( -V2 ) dt
T O T2

V2 (T2 - T1 )
VO = (1.13)
T
 Time Division Multipliers—Multiplexing 7

Equation (1.12) in (1.13) gives

V1 V2
VO = (1.14)
VSAT

1.4 TIME DIVISION MULTIPLIER NO REFERENCE—TYPE II

The time division multiplier using the time division principle without using
any reference clock is shown in Figure 1.7, and its associated waveforms are
shown in Figure 1.8.
Initially the 555 timer output VC is HIGH. −V1 is connected to the dif-
ferential integrator by the multiplexer M1 (‘ay’ is connected to ‘a’). The
inverting amplifier OA3 output will be LOW, i.e., −VSAT. The output of the
differential integrator will be

1
VT1 = (VO + V1 )dt
R1C1
(VO + V1 )
VT1 = t (1.15)
R1C1

The output of the differential integrator rises toward positive saturation,

and when it reaches the voltage level of +VT, the 555 timer output becomes
LOW. +V1 is connected to the differential integrator by the multiplexer M1

Figure 1.7 Time division multiplier without reference clock—type II.

8 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.8 Associated waveforms of Figure 1.7.

(‘ax’ is connected to ‘a’). The inverting amplifier OA3 output will be HIGH,
i.e., +VSAT. Now the output of the differential integrator will be

1
VT1 = (VO - V1 )dt
R1C1
(V1 - VO )
VT1 = - t (1.16)
R1C1

The output of the differential integrator reverses toward negative saturation,

and when it reaches the voltage level −VT, the 555 timer output becomes
HIGH, and the cycle therefore repeats, to give an asymmetrical rectangular
wave VC at the output of the 555 timer.

VCC
VT = (1.17)
3

From the waveforms shown in Figure 1.8, it is observed that

V1 - VO V + VO
T1 = T, T2 = 1 T, T = T1 + T2 (1.18)
2V1 2V1
 Time Division Multipliers—Multiplexing 9

Another rectangular wave VN with ±VSAT results as the peak to peak value
is generated at the inverting amplifier OA3 output. The R2C2 low pass filter
gives the average value of this pulse train VN and is given as
T2 T1 + T2
1
VX = VSAT dt + ( -VSAT ) dt
T O T2

VSAT (T2 - T1 )
VX = (1.19)
T

Equations (1.18) in (1.19) gives

VO VSAT
VX = (1.20)
V1

The op-­amp OA4 is at the negative closed loop configuration, and a positive
dc voltage is ensured in the feedback loop. Hence its non-­inverting terminal
voltage is equal to its inverting terminal voltage, i.e.,

V2 = VX (1.21)

From equations (1.20) and (1.21)

V1 V2
VO = (1.22)
VSAT

1.5 TIME DIVISION MULTIPLIER USING 555 ASTABLE

MULTIVIBRATOR

1.5.1 T ime Division Multiplier Using 555 Astable

Multivibrator—Type I
The circuit diagram of the multiplier using the 555 timer astable multivi-
brator is shown in Figure 1.9, and its associated waveforms are shown in
Figure 1.10. Refer to the internal diagram of the 555 timer IC shown in
Figure 0.1. Initially when we switch on the power supply, the output of the
upper comparator CMP1 will be LOW, i.e., R = 0, the output of the lower
comparator CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are Q = 1
and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is OFF,
and hence the discharge pin 7 is at the open position.
The capacitor C1 is charging toward +VCC through the resistors R1 and
R2 with a time constant of (R1+R2)C1, and its voltage is rising exponentially.
10 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.9 Multiplier with 555 timer astable multivibrator.

Figure 1.10 Associated waveforms of Figure 1.9.

When the capacitor voltage is rising above the voltage V1, the output of the
upper comparator CMP1 becomes HIGH, i.e., R = 1, and the output of lower
comparator CMP2 becomes LOW, i.e., S = 0. The flip flop outputs are Q = 0
and Q′ = 1. The timer output at pin 3 will be LOW, transistor Q1 is ON
and hence the discharge pin 7 is at GND potential. Now the capacitor C1 is
discharging to GND potential through the resistor R2 with a time constant
of R2C. When the capacitor voltage falls below 1/3 VCC, the output of the
upper comparator CMP1 becomes LOW, i.e., R = 0, the output of the lower
comparator CMP2 becomes HIGH, i.e., S = 1. The flip flop outputs are Q = 1
and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is OFF,
and hence the discharge pin 7 is at the open position.
Now the capacitor starts charging toward +VCC, and the cycle therefore
repeats to produce periodic pulses at the output pin 3 of the 555 timer.
The ON time of the 555 timer output VM is proportional to V1, which is
applied at its pin 5. The pulse VM controls the multiplexer M1. During the
ON time δT, the second input voltage V2 is connected to the R3C2 low pass
filter (‘ay’ is connected to ‘a’). During the OFF time of VM, zero voltage
is connected to the R3C2 low pass filter (‘ax’ is connected to ‘a’). Another
 Time Division Multipliers—Multiplexing 11

rectangular waveform VN, with V2 as the peak value, is generated at the

output of the multiplexer M1.

V1
δT = T (1.23)
VR

The R3C2 low pass filter gives the average value of this pulse train VN and
is given as
δT
1 V2
VO = V2 dt = δT
T 0
T
V1 V2
VO = (1.24)
VR

where VR is a constant value.

1.5.2 Multiplier from 555 Astable Multivibrator—

Type II
The circuit diagram of the divider using the 555 astable multivibrator is
shown in Figure 1.11, and its associated waveforms are shown in Figure 1.12.
Refer to the internal diagram of the 555 timer IC shown in Figure 0.1.
Initially when we switch on the power supply, the output of the upper com-
parator CMP1 will be LOW, i.e., R = 0, the output of the lower comparator
CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are Q = 1 and Q′ = 0.
The timer output at pin 3 will be HIGH, transistor Q1 is OFF, and hence the
discharge pin 7 is at the open position.
The capacitor C1 is charging toward V1 through the resistors R1 and R2
with a time constant of (R1+R2)C1, and its voltage is rising exponentially.

Figure 1.11 Multiplier from 555 astable—type II.

12 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.12 Associated waveforms of Figure 1.11.

When the capacitor voltage is rising above the voltage 2/3 VCC, the out-
put of the upper comparator CMP1 becomes HIGH, i.e., R = 1, and the
output of the lower comparator CMP2 becomes LOW, i.e., S = 0. The flip
flop outputs are Q = 0 and Q′ = 1. The timer output at pin 3 will be LOW,
transistor Q1 is ON and hence the discharge pin 7 is at GND potential.
Now the capacitor C1 is discharging to GND potential through the resis-
tor R2 with a time constant of R2C. When the capacitor voltage falls
below 1/3 VCC, the output of the upper comparator CMP1 becomes LOW,
i.e., R = 0, and the output of the lower comparator CMP2 becomes HIGH,
i.e., S = 1. The flip flop outputs are Q = 1 and Q′ = 0. The timer output at
pin 3 will be HIGH, transistor Q1 is OFF, and hence the discharge pin 7
is at the open position.
Now the capacitor starts charging toward V1, and the cycle therefore
repeats to produce periodic pulses at the output pin 3 of the 555 timer.
The ON time of the 555 timer output VM is inversely proportional to VO.
The 555 timer output controls the multiplexer M1. During the ON time δT,
the input voltage Vo is connected to the R3C2 low pass filter (‘ay’ is con-
nected to ‘a’). During the OFF time of VM, zero voltage is connected to the
R3C2 low pass filter (‘ax’ is connected to ‘a’). Another rectangular waveform
VN, with VO as the peak value, is generated at the output of multiplexer M1.
The ON time δT of this rectangular pulse VN is given as

VR
δT = T (1.25)
V1

where VR is a constant value.

The R3C2 low pass filter gives the average value of this pulse train VN and
is given as
δT
1 VO
VX = VO dt = δT
T 0
T
V
VX = O VR (1.26)
V1
 Time Division Multipliers—Multiplexing 13

The op-­amp OA1 is kept in a negative closed loop configuration, and a posi-
tive dc voltage is ensured in the feedback. Hence its inverting terminal volt-
age will be equal to its non-­inverting terminal voltage, i.e.,

VX = V2 (1.27)

From equations (1.26) and (1.27),

V1 V2
VO = (1.28)
VR

1.6 MULTIPLIER FROM 555 MONOSTABLE MULTIVIBRATOR

1.6.1 Multiplier from 555 Monostable Multivibrator—

Type I
The circuit diagram of a multiplier using the 555 timer monostable multi-
vibrator is shown in Figure 1.13, and its associated waveforms are shown
in Figure 1.14. Refer to the internal diagram of the 555 timer IC shown in

Figure 1.13 (a) Multiplier from 555 monostable. (b) Multiplier with 555 re-­trigger mono-
stable multivibrator.
14 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.14 (a) Associated waveforms of Figure 1.13(a). (b) Associated waveforms of
Figure 1.13(b).

Figure 0.1. Initially when the power supply is switched on, the output of
the upper comparator CMP1 will be LOW, i.e., R = 0, and the output of the
lower comparator CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are
Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is
OFF, and hence the discharge pin 7 is at the open position. The capacitor C1
is charging toward +VCC through the resistor R1. The capacitor voltage is
rising exponentially and when it reaches the value of V1, the output of the
upper comparator CMP1 becomes HIGH, i.e., R = 1, and the output of the
lower comparator CMP2 becomes LOW, i.e., S = 0. The flip flop outputs are
Q = 0 and Q′ = 1. The timer output at pin 3 will be LOW, transistor Q1 is
ON, and hence the discharge pin 7 is at GND potential. Now the capacitor
C1 is short circuited, zero volts is existing at pin 6, the output of the upper
comparator CMP1 becomes LOW, i.e., R = 0. A trigger pulse is applied at pin
2, and when the trigger voltage comes down to 1/3 VCC, the output of the
lower comparator CMP2 becomes HIGH, i.e., S = 1. The flip flop outputs
are Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1
is OFF, and hence the discharge pin 7 is at the open position.
Now the capacitor C1 is charging toward +VCC, and the sequence there-
fore repeats for every trigger input pulse.
The ON time of the 555 timer output VM is proportional to V1, which is
applied at its pin 5. The 555 timer output controls the multiplexer M1. Dur-
ing the ON time δT, the second input voltage V2 is connected to the R3C3
low pass filter (‘ay’ is connected to ‘a’). During the OFF time of VM, zero
 Time Division Multipliers—Multiplexing 15

voltage is connected to the R3C3 low pass filter (‘ax’ is connected to ‘a’).
Another rectangular waveform VN, with V2 as the peak value, is generated at
the output of multiplexer M1. The ON time δT of this rectangular waveform
VN is given as

V1
δT = T (1.29)
VR

The R3C3 low pass filter gives the average value of this pulse train VN and
is given as
δT
1 V2
VO = V2 dt = δT
T 0
T
VV
VO = 1 2 (1.30)
VR

where VR is a constant value.

The multiplier using the 555 re-­trigger monostable multivibrator is shown
in Figure 1.13(b).

1.6.2 Multiplier from 555 Monostable Multivibrator—

Type II
The circuit diagram of a divider using the 555 monostable multivibrator
is shown in Figure 1.15, and its associated waveforms are shown in Fig-
ure 1.16. Refer to the internal diagram of the 555 timer IC shown in Fig-
ure 0.1. Initially when the power supply is switched on, the output of the
upper comparator CMP1 will be LOW, i.e., R = 0, and the output of the
lower comparator CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are
Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is
OFF, and hence the discharge pin 7 is at the open position. The capacitor C1
is charging toward V1 through the resistor R1. The capacitor voltage is rising
exponentially, and when it reaches the value of 2/3 VCC, the output of the
upper comparator CMP1 becomes HIGH, i.e., R = 1, and the output of the
lower comparator CMP2 becomes LOW, i.e., S = 0. The flip flop outputs are
Q = 0 and Q′ = 1. The timer output at pin 3 will be LOW, transistor Q1 is
ON, and hence the discharge pin 7 is at GND potential. Now the capacitor
C1 is short circuited, zero voltage exists at pin 6, and the output of the upper
comparator CMP1 becomes LOW, i.e., R = 0. A trigger pulse is applied at pin
2, and when the trigger voltage comes down to 1/3 VCC, the output of the
lower comparator CMP2 becomes HIGH, i.e., S = 1. The flip flop outputs
are Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1
is OFF, and hence the discharge pin 7 is at the open position.
16 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 1.15 (a) Multiplier using 555 timer monostable multivibrator. (b) Multiplier using
re-­trigger monostable multivibrator.

Now the capacitor C1 is charging toward V1, and the sequence therefore
repeats for every trigger input pulse.
The ON time of the 555 timer output VM is inversely proportional to V1.
The output of the 555 timer controls the multiplexer M1. During the ON
time δT, the voltage VO is connected to the R3C3 low pass filter (‘ay’ is con-
nected to ‘a’). During the OFF time of VM, zero voltage is connected to the
R3C3 low pass filter (‘ax’ is connected to ‘a’). Another rectangular waveform
VN, with VO as peak value, is generated at the output of the multiplexer M1.

VR
δT = T (1.31)
V1

The R3C3 low pass filter gives the average value of this pulse train VN and
is given as
 Time Division Multipliers—Multiplexing 17

Figure 1.16 (a) Associated waveforms of Figure 1.15(a). (b) Associated waveforms of
Figure 1.15(b).

δT
1 VO
VX = VO dt = δT
T 0
T
V
VX = O VR (1.32)
V1

where VR is a constant value.

The op-­amp OA1 is kept in a negative closed loop configuration, and a
positive dc voltage is ensured in the feedback. Hence its inverting terminal
voltage will be equal to its non-­inverting terminal voltage, i.e.,

VX = V2 (1.33)

From equations (1.32) and (1.33),

V1 V2
VO = (1.34)
VR

Figure 1.15(b) shows the re-­trigger monostable multivibrator used as an

analog multiplier.
Chapter 2

Time Division Multipliers—

Switching

If the width of a pulse train is made proportional to one voltage and the
amplitude of the same pulse train to a second voltage, then the average
value of this pulse train is proportional to the product of two voltages and
is called a time division multiplier, a pulse averaging multiplier, or a sigma
delta multiplier. The time division multiplier can be implemented using (1) a
triangular wave, (2) a saw tooth wave, and (3) no reference wave.
There are two types of time division multipliers (TDM) (1) multiplexing
TDM (MTDM) and (2) switching TDM (STDM). A time division multiplier
using analog 2 to 1 multiplexers is called a multiplexing TDM. A time divi-
sion multiplier using analogue switches is called a switching TDM. Multi-
plexing time division multipliers are described in chapter 3, and switching
time division multipliers are described in this chapter.

2.1 SAW TOOTH WAVE BASED TIME DIVISION MULTIPLIERS

The circuit diagrams of saw tooth wave based time division multipliers
are shown in Figure 2.1, and their associated waveforms are shown in Fig-
ure 2.2. A saw tooth wave VS1 of peak value VR and time period T is gener-
ated by the 555 timer.
In the circuits of Figure 2.1, the comparator OA2 compares the saw tooth
wave VS1 of peak value VR with the input voltage V1 and produces a rect-
angular waveform VM at its output. The ON time δ T of this rectangular
waveform VM is given as

V1
δT = T (2.1)
VR

The rectangular pulse VM controls the switch S1. When VM is HIGH, another
input voltage V2 is connected to the R3C2 low pass filter (switch S1 is closed).
When VM is LOW, zero voltage is connected to the R3C2 low pass filter
(switch S1 is opened). Another rectangular pulse VN with a maximum value

DOI: 10.1201/9781003362968-2
20 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 2.1 (a) Saw tooth wave based time division multiplier—type I. (b) Saw tooth wave
based time division multiplier—type II.

of V2 is generated at the switch S1 output. The R3C2 low pass filter gives the
average value of this pulse train VN and is given as

δT
1
VO = V2 dt (2.2)
T 0

V2
VO = δT (2.3)
T
 Time Division Multipliers—Switching 21

Figure 2.2 Associated waveforms of Figure 2.1.

Equation (2.1) in (2.3) gives

V1 V2
VO = (2.4)
VR

where VR = 2/3 VCC.

2.2 TRIANGULAR WAVE REFERENCED TIME DIVISION

MULTIPLIERS
The circuit diagrams of triangular wave based multipliers are shown in Fig-
ure 2.3, and their associated waveforms are shown in Figure 2.4. A trian-
gular wave VT1 with ±VT peak to peak value and time period T is generated
by the 555 timer.
One input voltage V1 is compared with the generated triangular wave
VT1 by the comparator on OA2. An asymmetrical rectangular waveform VM
is generated at the comparator OA2 output. From the waveforms shown in
Figure 2.5, it is observed that

VT - V1 V + V1
T1 = T, T2 = T T, T = T1 + T2 (2.5)
2VT 2VT

This rectangular wave VM is given as the control input to the switch S1.
During T2 of VM, the switch S1 is closed, and the op-­amp OA3 will work as
non-­inverting amplifier. +V2 will be its output, i.e., VN = +V2. During T1 of
VM, the switch S1 is opened, and the op-­amp will work as inverting amplifier.
−V2 will be at its output, i.e., VN = −V2. Another rectangular asymmetrical
wave VN, with a peak to peak value of ±V2, is generated at the op-­amp OA3
22 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 2.3 (a) Triangular wave based multiplier—type I. (b) Triangular wave based
multiplier—type II.

Figure 2.4 Associated waveforms of Figure 2.3(a) and (b).

 Time Division Multipliers—Switching 23

output. The R4C3 low pass filter gives an average value of the pulse train VN
and is given as

T2 T1 + T2
1 V2
VO = V2 dt + ( -V2 ) dt = (T2 - T1 ) (2.6)
T O T2
T

Equation (2.5) in (2.6) gives

V1 V2
VO = (2.7)
VT
where VT = VCC/3.(2.8)

2.3 TIME DIVISION MULTIPLIER WITH NO REFERENCE—

TYPE I
The multiplier using the time division principle without using any reference
clock is shown in Figure 2.5, and its associated waveforms are shown in
Figure 2.6.
Initially the 555 timer output is HIGH. The inverting amplifier OA3 out-
put is −VSAT. The output of the differential integrator will be

Figure 2.5 Time division multiplier without reference clock.

24 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 2.6 Associated waveforms of Figure 2.5.

1
VT1 = (V1 + VSAT )dt
R1C1
(VSAT + V1 )
VT1 = t (2.9)
R1C1

The output of the differential integrator rises toward positive saturation,

and when it reaches the voltage level of +VT, the 555 timer output becomes
LOW. The inverting amplifier OA3 output is +VSAT. Now the output of the
differential integrator will be

1
VT1 = (V1 - VSAT )dt
R1C1
(VSAT - V1 )
VT1 = - t (2.10)
R1C1

The output of the differential integrator reverses toward negative saturation,

and when it reaches the voltage level −VT, the 555 timer output becomes
HIGH, and the cycle therefore repeats, to give an asymmetrical rectangular
wave VC at the output of the 555 timer.
 Time Division Multipliers—Switching 25

VCC
VT = (2.11)
3

From the waveforms shown in Figure 2.6, it is observed that

VSAT - V1 V + V1
T1 = T, T2 = SAT T, T = T1 + T2 (2.12)
2VSAT 2VSAT

The asymmetrical rectangular wave VC controls switch S1. The op-­amp OA4
gives −V2 during the ON time T1 of the rectangular waveform VC (the switch
S1 is closed, and the op-­amp OA4 will work as a non-­inverting amplifier) and
+V2 during the OFF time T2 of the rectangular wave VC (the switch S1 is
opened, and the op-­amp OA4 will work as an inverting amplifier). Another
rectangular wave VN with a peak to peak value of ±V2 is generated at the
output of op-­amp OA4. The R2C2 low pass filter gives the average value of
this pulse train VN and is given as

T2 T1 + T2
1
VO = V2 dt + ( -V2 ) dt
T O T2

V2 (T2 - T1 )
VO = (2.13)
T

Equation (2.12) in (2.13) gives

V1 V2
VO = (2.14)
VSAT

2.4 TIME DIVISION MULTIPLIER NO REFERENCE—TYPE II

The multipliers using the time division principle without using any refer-
ence clock is shown in Figure 2.7, and its associated waveforms are shown
in Figure 2.8.
Initially the 555 timer output is HIGH. The op-­amp OA3 gives −V1 to the
inverting terminal of differential integrator (the switch S1 is closed, and the
op-­amp OA3 will work as a non-­inverting amplifier). The output of differ-
ential integrator will be

1
VT1 = (VO + V1 )dt
R1C1
(VO + V1 )
VT1 = t (2.15)
R1C1
26 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 2.7 Time division multiplier without reference clock—II.

Figure 2.8 Associated waveforms of Figure 2.7.

The output of the differential integrator rises toward positive saturation,

and when it reaches the voltage level of +VT, the 555 timer output becomes
LOW. The op-­amp OA3 gives +V1 to the inverting terminal of the differential
 Time Division Multipliers—Switching 27

integrator (the switch S1 is opened, and the op-­amp OA3 will work as an
inverting amplifier). Now the output of the differential integrator will be

1
VT1 = (VO - V1 )dt
R1C1
(V1 - VO )
VT1 = - t (2.16)
R1C1

The output of the differential integrator reverses toward negative saturation,

and when it reaches the voltage level −VT, the 555 timer output becomes
HIGH, and the cycle therefore repeats, to give an asymmetrical rectangular
wave VC at the output of the 555 timer.

VCC
VT = (2.17)
3

From the waveforms shown in Figure 2.8, it is observed that

V1- VO V + VO
T1 = T, T2 = 1 T, T = T1 + T2 (2.18)
2V1 2V1

Another rectangular wave VN, with ±VSAT as the peak to peak value, is gen-
erated at the output of the inverting amplifier OA4. The R2C2 low pass filter
gives the average value of this pulse train VN and is given as

T2 T1 + T2
1
VX = VSAT dt + ( -VSAT ) dt
T O T2

VSAT (T2 - T1 )
VX = (2.19)
T

Equation (2.17) in (2.19) gives

VO VSAT
VX = (2.20)
V1

The op-­amp OA5 is at negative closed loop configuration, and a positive dc

voltage is ensured in the feedback loop. Hence its non-­inverting terminal
voltage is equal to its inverting terminal voltage, i.e.,

V2 = VX (2.21)
28 Design of Function Circuits with 555 Timer Integrated Circuit

From equations (2.20) and (2.21),

V1 V2
VO = (2.22)
VSAT

2.5 MULTIPLIER FROM 555 ASTABLE MULTIVIBRATOR

2.5.1 Multiplier from 555 Astable Multivibrator—

Type I
The circuit diagram of a multiplier using the 555 timer astable multivi-
brator is shown in Figure 2.9, and its associated waveforms are shown in
Figure 2.10. Refer to the internal diagram of the 555 timer IC shown in
Figure 0.1. Initially when we switch on the power supply, the output of the
upper comparator CMP1 will be LOW, i.e., R = 0, and the output of the
lower comparator CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are
Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1 is
OFF, and hence the discharge pin 7 is at the open position.
The capacitor C1 is charging toward +VCC through the resistors R1 and
R2 with a time constant of (R1+R2)C1, and its voltage is rising exponentially.
When the capacitor voltage is rising above the voltage V1, the output of the

Figure 2.9 Multiplier with 555 timer astable multivibrator—type I.

Figure 2.10 Associated waveforms of Figure 2.9.

 Time Division Multipliers—Switching 29

upper comparator CMP1 becomes HIGH, i.e., R = 1, and the output of the
lower comparator CMP2 becomes LOW, i.e., S = 0. The flip flop outputs are
Q = 0 and Q′ = 1. The timer output at pin 3 will be LOW, transistor Q1 is
ON, and hence the discharge pin 7 is at GND potential. Now the capaci-
tor C1 is discharging to GND potential through the resistor R2 with a time
constant of R2C. When the capacitor voltage falls below 1/3 VCC, the output
of the upper comparator CMP1 becomes LOW, i.e., R = 0, and the output of
the lower comparator CMP2 becomes HIGH, i.e., S = 1. The flip flop outputs
are Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1
is OFF, and hence the discharge pin 7 is at the open position.
Now the capacitor starts charging toward +VCC, and the cycle therefore
repeats to produce periodic pulses at the output pin 3 of the 555 timer.
The ON time of the 555 timer output VM is proportional to V1, which is
applied at its pin 5. During the ON time δT, the second input voltage V2 is
connected to R3C2 low pass filter (switch S1 is closed). During the OFF time
of VM, zero voltage exists on the R3C2 low pass filter (switch S1 is opened).
Another rectangular waveform VN, with V2 as the peak value, is generated
at the output of switch S1.

V1
δT = T (2.23)
VR

The R3C2 low pass filter gives the average value of this pulse train VN and
is given as

δT
1 V2
VO = V2 dt = δT
T 0
T
V1 V2
VO = (2.24)
VR

where VR is a constant value.

2.5.2 Multiplier from 555 Astable Multivibrator—Type II

The circuit diagram of a divider using the 555 astable multivibrator is shown
in Figure 2.11, and its associated waveforms are shown in Figure 2.12. Refer
to the internal diagram of the 555 timer IC shown in Figure 0.1. Initially
when we switch on the power supply, the output of the upper comparator
CMP1 will be LOW, i.e., R = 0, and the output of the lower comparator
CMP2 will be HIGH, i.e., S = 1. The flip flop outputs are Q = 1 and Q′ = 0.
The timer output at pin 3 will be HIGH, transistor Q1 is OFF, and hence the
discharge pin 7 is at the open position.
30 Design of Function Circuits with 555 Timer Integrated Circuit

Figure 2.11 Multiplier from 555 astable—type II.

Figure 2.12 Associated waveforms of Figure 2.11.

The capacitor C1 is charging toward V1 through the resistors R1 and R2

with a time constant of (R1+R2)C1, and its voltage is rising exponentially.
When the capacitor voltage rises above the voltage 2/3 VCC, the output of
the upper comparator CMP1 becomes HIGH, i.e., R = 1, and the output of
the lower comparator CMP2 becomes LOW, i.e., S = 0. The flip flop outputs
are Q = 0 and Q′ = 1. The timer output at pin 3 will be LOW, transistor Q1
is ON, and hence the discharge pin 7 is at GND potential. Now the capaci-
tor C1 is discharging to GND potential through the resistor R2 with a time
constant of R2C. When the capacitor voltage falls below 1/3 VCC, the output
of the upper comparator CMP1 becomes LOW, i.e., R = 0, and the output of
the lower comparator CMP2 becomes HIGH, i.e., S = 1. The flip flop outputs
are Q = 1 and Q′ = 0. The timer output at pin 3 will be HIGH, transistor Q1
is OFF, and hence the discharge pin 7 is at the open position.
Now the capacitor starts charging toward V1, and the cycle therefore
repeats to produce periodic pulses at the output pin 3 of the 555 timer.
The ON time of the 555 timer output VM is inversely proportional to V1.
During the ON time δT, the voltage VO is connected to the R3C2 low pass
filter (switch S1 is closed). During the OFF time of VM, zero voltage exists on
the R3C2 low pass filter (switch S1 is opened). Another rectangular waveform
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