RTUIF18

A 4.1-to-6.5GHz Transformer-Coupled CMOS Quadrature

Digitally-Controlled Oscillator with Quantization Noise Suppression
Shiyuan Zheng, Howard C. Luong
Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong

Abstract — A wideband quadrature digitally-controlled [2]. Fig. 1 shows the block diagram of a quadrature LC
oscillator (QDCO) operates in Class-C mode with embedded oscillator and its current phasor diagrams. For the two
phase shifters for better phase noise and I-Q accuracy.
Transformer-coupled fine tuning capacitors are controlled by coupled oscillators OSC1 and OSC2, the negative Gm cells
a ΣΔ modulator with embedded filter to achieve fractional generate currents i1 and i2 from the tank voltage v1 and v2
quantization step with intrinsic out-band noise suppression. while the coupled Gmc cells generate currents iC1 and iC2. In
The QDCO fabricated in 65nm CMOS measures tuning Fig. 1b, without the phase shifter, a phase difference is
range of 45% from 4.1GHz to 6.5GHz with frequency generated between the tank current it1 and tank voltage v1,
resolution of 5Hz while achieving 1.2° phase error and a
phase noise of -145.3dBc/Hz at 10MHz. It consumes 15mA which shifts the oscillation frequency ωOSC away from the
from a 1.2V supply corresponding to a FoM of 186.6dBc/Hz tank resonant frequency ω0 and lowers the tank
and a FoMT of 199.8dBc/Hz. impedance. In Fig. 1c, with the 90°phase shifter, the
Index Terms — QDCO, VCO, ADPLL, transformer, oscillation frequency is the same as the LC tank resonant
transformer-coupled, ΣΔ noise shaping, Class-C frequency. As a result, the tank impedance is maximized,
and the amplitude mismatches between the I-Q tanks do
I. INTRODUCTION not affect the quadrature accuracy. Unfortunately, the
phase shifters in series with the coupling paths consume
Digitally-controlled oscillator (DCO) is one of the key extra power and contribute more noise.
building blocks in all-digital phase-locked loops
(ADPLLs). Due to the digital frequency tuning control, L1 R1 C1 Φ=0° or 90° C2 R 2 L2
not only is its frequency resolution limited but also its
OSC1 iC1 OSC2
phase noise is significantly degraded due to the
Gmc Φ -1
quantization noise. Normally, in an LC oscillator, the v1 iC2 v2
LSB’s capacitors are switched by a high-speed ΣΔ- Φ Gmc
i1 i2
modulated dither to reduce the effective DCO quantization
step [1]. Depending on the dithering frequency, the out-of- Phase Shifter
band phase noise would increase due to the high-pass (a)
transfer function of the ΣΔ modulator. In FDD system, TX it1 | Z ( jω ) |
noise at the RX band has a very stringent requirement. α iC1
i1
Moreover, the co-existence of different wireless
connectivity makes the out-of-band phase noise v1 ω0
requirement more challenging. This paper presents a 4.1- α it2 ∠ Z ( jω )
v2
to-6.5GHz QDCO with intrinsic 6.6dB out-of-band noise i2
suppression without using a SAW filter. The QDCO iC2 ωOSC≠ω0 α
(b) ωOSC
operates in Class-C mode for better DC-to-RF conversion
it1
efficiency. The embedded phase shifters between the I-Q | Z ( jω ) |
coupling paths achieve better phase noise and I-Q phase i1 iC1
accuracy without burning extra power. v1
i2
v2 ω0
II. CLASS-C MODE QVCO WITH PHASE SHIFTER it2 ∠ Z ( jω )
ωOSC
A quadrature LC oscillator consists of two strongly iC2
ωOSC=ω0
coupled oscillators that are locked to the same frequency. (c)
Adding phase shifters in series with the I-Q coupling paths
can improve the QVCO phase noise and make the I-Q Fig. 1. (a) Block diagram of a quadrature LC oscillator;
current phasor, amplitude and phase of tank impedance (b)
phase accuracy less sensitive to the devices’ mismatches without phase shifter; and (c) with 90°phase shifter.

978-1-4673-0416-0/12/$31.00 ©2012 IEEE 519 2012 IEEE Radio Frequency Integrated Circuits Symposium
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 Fig. 2 shows the schematic of the proposed transformer
–coupled QVCO with embedded phase shifters to
minimize power and noise contribution. The propose
QVCO is based on a series-coupled QVCO, but the series-
coupled devices are also used as the phase shifter. Vg is
biased to be lower than VDD so that all the transistors are
operated in Class-C and are only on for around half of the
period. The primary coil of the transformer enlarges the
voltage swing at the gate to enhance the switching
effectiveness [3]. At the same time, the secondary coil
reduces the voltage swing at the drain to maximize Vds to
prevent the transistors from operating in the linear region
to improve phase noise. Capacitors Cs1 are added not only
for the current shaping in Class-C operation [4] but also as
part of the phase shifter.
Fig. 3 shows the current and voltage waveforms of M0,
M1 and Cs1 in the QVCO. The operation at the 4 critical Fig. 3. Transient current and voltage waveforms of M0 and M1
moments can be explained as follows. At 0°, vI- and vQ+
are low, and both M0 and M1 are off. At 90°, vQ+ increases, III. QDCO WITH ΣΔ SHAPED NOISE SUPPRESSION
M1 starts to conduct, and M0 is still off. Cs1 is discharged,
and no current is injected to the tank. At 180°, M0 starts to Fig. 4 shows the block diagram of the QDCO which
draw current from the tank. M1 is still on, but its drain consists of the QVCO in Fig. 2 and digitally-controlled
current is reduced since vds decreases, and Cs1 starts to be switched-capacitor arrays (SCAs) for frequency tuning.
charged. At 270°, vQ+ falls, M1 is turned off, and all the An 8-bit switched-MIM-capacitor array is employed in the
current from the tank flows through M0 to continue to primary coil for coarse tuning. Minimum-sized MOS
charge Cs1. In the steady state, the currents charging and capacitors are placed in the secondary coil instead of the
discharging Cs1 become equal. The Q-phase coupled primary coil to achieve finer tuning by exploiting the fact
current is firstly stored in Cs1 by M1 and then that the coupling coefficient is less than 1. In addition,
synchronously injected to the I-phase tank by M0, which since the voltage swing at the secondary coil is much
effectively generates a 90° phase shift. Since this phase smaller than that at the primary coil, the non-linearity
shifter reuses the active devices and the current of the effect of the tuning capacitors is significantly reduced.
quadrature series-coupled path, the performance is These MOS capacitors are controlled by a 10-bit integer
improved without extra noise and power. signal and a 14-bit fractional signal. For the 10-bit integer
VDD VDD
signal, the 4 MSB’s directly control the binary-weighted
MOS capacitors, and the 6 LSB’s use thermometer code to
Vg Vg control the 64 unit-weighted MOS capacitors. As a result,
k k k k
1-LSB integer signal corresponds to an 80-KHz tuning
step at 5GHz oscillation frequency. To reduce the
quantization step, a 3 -order ΣΔ modulator with 8-levels
rd

Output output is used for the 14-bit fractional control. This ΣΔ

id0
modulator operates at 1/16 of the oscillator frequency and
M0 achieves 5-Hz frequency resolution.
vI- vI+ vQ- vQ+
Due to the noise-shaping effect of the modulator, the
id1 ics1 out-of-band noise floor is dominated by the modulator’s
Cs1 vQ- vI- vI+
vQ+ shaped noise. For a fixed frequency tuning step, the noise
M1 level depends on the order and the dither frequency of the
modulator. Reducing the order can improve the out-of-
band phase noise, but in-band noise would become worse
and generate more tones and spurs. Increasing the dither
frequency can help to improve the quantization noise, but
Fig. 2. Proposed Class-C QVCO with embedded phase it would require more power and contribute more
shifters switching noise.

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 IV. MEASUREMENTS
A QDCO prototype is fabricated in a 65nm 1P6M LP
CMOS process. It draws 15mA from 1.2V and achieves a
tuning range of 45% from 4.08 to 6.52GHz. From Fig. 6,
phase noise of -145.3dBc/Hz at 10MHz offset is measured
at 4.9 GHz with ΣΔ dither power off, corresponding to
FoM of 186.6 dB and FOMT of 199.8 dB. As shown in Fig.
7, the phase noise is measured across the turning range
and has a variation less than 3dB. The worst case sideband
rejection measured with an on-chip Single-Side-Band
(SSB) up-mixer for 5 samples is 39.7dB, corresponding to
an I-Q phase error of 1.2°.

Fig. 4. Schematic of the proposed QDCO with ΣΔ shaped

quantization noise filter

For our proposed QDCO, a clock delay is inserted in the

4-phase fractional MOS capacitors to implement an
rd
embedded 3 -order sinc filter, which generates 3 zeros at
¼, ½ and ¾ of the ΣΔ dithering frequency to suppress the
quantization noise. As shown in Fig. 5, it theoretically Fig. 6. QDCO phase noise measure at 4.9GHz with the digital
attenuates the out-of-band noise floor by 7.1dB. control circuits power-off

Fig. 7. Measured phase noise at 10MHz offset frequency

across the entire frequency tuning range

To verify the effectiveness of the embedded ΣΔ noise

filter, the delay cells for the 4-phase fractional MOS
capacitors are either selected or bypassed. Fig. 8
compares the out-of-band phase noise measurements in 3
different cases: a) without filter by bypassing all the delay
st
cells, b) with 1 order filter by bypassing the first and the
rd
last delay cells, and c) with 3 order filter by turning on all
the delay cells. The QDCO operates at 5.6GHz and has an
st rd
integer step 87-KHz. The 1 -order and the 3 -order
Fig. 5. Phase noise simulation of the proposed QDCO (a) embedded filters help suppress the out-of-band ΣΔ noise
rd
without noise filter (b) with 3 -order Sinc noise filter

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by 4.5dB and 6.6dB, respectively. The measured
performance of the QDCO is compared to existing state-
of-the-art QVCO and DCO in Table I. Fig. 9 shows the
2
chip photo, which occupies a core area of 1.0 x 0.4mm .

-141.1dBc/Hz @175MHz -145.6dBc/Hz @175MHz

Fig. 9. Die photograph

V. CONCLUSION
(a) (b)
Fig. (a) (b) (c)
In this paper, we present a proposed Class-C mode
QDCO with embedded phase shifters and ΣΔ-shaped
Filter order No 1st 3 rd quantization noise filter. The embedded phase shifters use
-147.7dBc/Hz @175MHz

Phase noise -141.1 -145.6 -147.7 the same coupling devices and reuse the current of the
@175MHz dBc dBc dBc quadrature series-coupled paths to improve the phase
Noise NA 4.5dB 6.6dB
suppression noise and IQ phase accuracy without extra power.
rd
Moreover, an embedded 3 -ordered sinc filter is achieved
(c) by inserting one clock delay between the 4-phase
Fig. 8. QDCO out-band ΣΔ shaped quantization noise fractional tuning capacitors to suppress the out-band noise
st
measurements: (a) without filter, (b) with 1 order filter, and (c) by 6.6dB. A QDCO prototype was fabricated and
rd
with 3 order filter measured to prove the proposed solution and achieves
state-of-the-art performance.
TABLE I
PERFORMANCE SUMMARY AND COMPARISON ACKNOWLEDGEMENT

Ref. [3] [4] [5] This work This work was jointly supported by TSMC University
JSSC 2007 JSSC 2008 ISSCC 2010 Program and the Hong Kong Innovation and Technology
Type QVCO VCO DCO QDCO Funding ITS/169/09. The authors would like to
Technology 180nm 130nm 65nm 65nm acknowledge valuable technical support by P. Y. Wu, T.
CMOS CMOS CMOS CMOS J. Yeh, and C. P. Jou from TSMC.
Supply voltage 1 1 1.8 1.2

Frequency 14.8-17.6 4.9-5.65/ 2.62-3.3 4.1-6.5 REFERENCES

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