a Audio Processor

SST-Melody®-DAP
FEATURES Supports Standard APIs:
16-Bit Fixed-Point Audio Processor (DSP-Based) Start Play
Decodes Major Standard Audio Formats Using 16-Bit Stop Play
Fixed-Point Implementation for Decoding: Mute Play
MPEG 1 Layer I, II, and III (MP3) Resume Play
AAC 2-Channel Low Complexity Download Song to Flash
Microsoft WMA Forward to Next Song
Speech Codecs: MGSM, G.723.1, and Audible Audio Rewind to Previous Song
2 Independent Data Address Generators Delete a Song
Powerful Program Sequencer Provides Zero Overhead Bass/Equalizer
Looping Conditional Instruction Execution Program- Erase MP3 Flash
mable 16-Bit Interval Timer with Prescaler 100-Lead Upload Song/Voice from Flash
LQFP and 144-Ball Mini-BGA Rename Flash
Supports Postprocessing: Start Record
Jazz/Rock/Classic/Pop/Bass Stop Record
3-Band User Customizable Graphic Equalizer Report
Supports Major Storage Formats: Get File Information
SmartMedia Card Seek File
DataPlay List Number of Songs
SD Card Request Song Name
NAND Flash List Number of Voices
Supports DRM (Digital Rights Management) Technologies: Request Voice Note Name
Liquid Audio SP3 Start Record (G.723.1)
Microsoft DRM Stop Record (G.723.1)
DataPlay ContentKey Start Play (G.723.1)
Stop Play (G.723.1)
(continued on page 2)

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN
CONTROL

FULL MEMORY MODE

MEMORY

DATA ADDRESS PROGRAMMABLE EXTERNAL

PROGRAM DATA ADDRESS
GENERATORS PROGRAM MEMORY I/O
MEMORY BUS
SEQUENCER 16K
16 BIT AND
DAG1 DAG2 16K
24 BIT
FLAGS

EXTERNAL
DATABUS
PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

OR

DATA MEMORY DATA

EXTERNAL
DATABUS
ARITHMETIC UNITS SERIAL PORTS TIMER

ALU MAC SHIFTER SPORT0 SPORT1 INTERNAL

DMA
PORT
ADSP-2100 BASE
ARCHITECTURE
HOST MODE

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
SST-Melody-DAP
Mute Play (Voice) INTEGRATION
Resume Play (Voice) ADSP-2100 Family Code Compatible (Easy to Use
Download Voice to Flash Algebraic Syntax), with Instruction Set Extensions
Forward to Next Record 80 Kbytes of On-Chip RAM, Configured as 16K Words
Rewind to Previous Record Program Memory RAM
Delete a Record 16K Words Data Memory RAM
Erase Voice Flash Dual-Purpose Program Memory for Both Instruction and
Version Reporting (G.723.1) Data Storage
Get G.723.1 Record Information Independent ALU, Multiplier/Accumulator, and Barrel
Rename Voice File Shifter Computational Units
Format Flash SYSTEM INTERFACE
Volume Control Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
Get Song Name All Inputs Tolerate up to 3.6 V Regardless of Mode
Get Album Name 16-Bit Internal DMA Port for High Speed Access to
Get Singer Name On-Chip Memory (Mode Selectable)
Get Song Duration 4 MByte Memory Interface for Storage of Data Tables
Version Reporting and Program Overlays (Mode Selectable)
Supports PC Interface 8-Bit DMA to Byte Memory for Transparent Program
USB 1.1 Interface and Data Memory Transfers (Mode Selectable)
Parallel Port Interface I/O Memory Interface with 2048 Locations Supports
Other Features: Parallel Peripherals (Mode Selectable)
ID3 Tag Support Programmable Memory Strobe and Separate I/O
SDMI Capable Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
PERFORMANCE Two Double-Buffered Serial Ports with Companding
13.3 ns Instruction Cycle Time @ 2.5 V (Internal) Hardware and Automatic Data Buffering
75 MIPS Sustained Performance Automatic Booting of On-Chip Program Memory from
Single-Cycle Instruction Execution Byte-Wide External Memory, e.g., EPROM, or
Single-Cycle Context Switch through Internal DMA Port
3-Bus Architecture Allows Dual Operand Fetches in Six External Interrupts
Every Instruction Cycle 13 Programmable Flag Pins Provide Flexible System
Multifunction Instructions Signaling
Power-Down Mode Featuring Low CMOS Standby Power UART Emulation through Software SPORT
Dissipation with 200 CLKIN Cycle Recovery from Reconfiguration
Power-Down Condition ICE-Port™ Emulator Interface Supports Debugging in
Low Power Dissipation in Idle Mode Final Systems

ICE-Port is a trademark of Analog Devices, Inc.

–2– REV. 0
 SST-Melody-DAP
TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 17

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 4 Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . 4 IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RECOMMENDED OPERATING CONDITIONS . . . . . . . 4 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 19
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . 5 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . 6 Memory Mapped Registers (New to the
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . . . 6 SST-Melody-DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 20
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 7 Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 20
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . . 20
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . . . 8 Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 20
FREQUENCY DEPENDENCY FOR Internal Memory DMA Port (IDMA Port; Host Memory
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 8 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 22
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . . 22
SOFTWARE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 10 Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 10 OUTLINE DIMENSIONS
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 100-Lead Metric Thin Plastic Quad Flatpack
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Tables
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 13
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 13 Table I. Memory Timing Specifications . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table II. Environmental Conditions . . . . . . . . . . . . . . . . . . . 8
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 15 Table III. Power Dissipation Example . . . . . . . . . . . . . . . . . . 8
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table IV. Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . 13
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table V. Interrupt Priority and Interrupt Vector Addresses . 15
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table VI. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . 17
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table VII. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table VIII. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 19
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table IX. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table X. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REV. 0 –3–
SST-Melody-DAP
GENERAL DESCRIPTION Instruction Set Description
The SST-Melody-DAP is a single-chip microcomputer opti- The SST-Melody-DAP assembly language instruction set has
mized for digital signal processing (DSP) and other high speed an algebraic syntax that was designed for ease of coding and
numeric processing applications. readability.
The SST-Melody-DAP combines the ADSP-2100 family base The assembly language, which takes full advantage of the
architecture (three computational units, data address genera- processor’s unique architecture, offers the following benefits:
tors, and a program sequencer) with two serial ports, a 16-bit • The algebraic syntax eliminates the need to remember cryptic
internal DMA port, a byte DMA port, a programmable timer, assembler mnemonics. For example, a typical arithmetic add
flag I/O, extensive interrupt capabilities, and on-chip program instruction, such as AR = AX0 + AY0, resembles a simple
and data memory. equation.
The SST-Melody-DAP integrates 80 Kbytes of on-chip • Every instruction assembles into a single, 24-bit word that
memory configured as 16K words (24-bit) of program RAM, can execute in a single instruction cycle.
and 16K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated • The syntax is a superset ADSP-2100 family assembly lan-
portable equipment. The SST-Melody-DAP is available in a guage and is completely source and object code compatible
100-lead LQFP package and 144-ball mini-BGA. with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the
In addition, the SST-Melody-DAP supports new instruc- SST-Melody-DAP’s interrupt vector and reset vector map.
tions, which include bit manipulations—bit set, bit clear, bit
toggle, bit test—new ALU constants, new multiplication • Sixteen condition codes are available. For conditional
instruction (x squared), biased rounding, result-free ALU jump, call, return, or arithmetic instructions, the condition
operations, I/O memory transfers, and global interrupt mask- can be checked and the operation executed in the same
ing, for increased flexibility. Fabricated in a high speed, low instruction cycle.
power, CMOS process, the SST-Melody-DAP operates with a • Multifunction instructions allow parallel execution of an
13.3 ns instruction cycle time. Every instruction can execute in arithmetic instruction with up to two fetches or one write to
a single processor cycle. processor memory space during a single instruction cycle.
The SST-Melody-DAP’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle, the SST-Melody-
DAP can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer

SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade B Grade
Parameter Min Max Min Max Unit
VDDINT 2.37 2.63 2.25 2.75 V
VDDEXT 2.37 3.6 2.25 3.6 V
VINPUT VIL = –0.3 VIH = +3.6 VIL = –0.3 VIH = +3.6 V
TAMB 0 +70 –40 +85 °C
Specifications subject to change without notice.

–4– REV. 0
 SST-Melody-DAP
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter Test Conditions Min Typ Max Unit
1, 2
VIH Hi-Level Input Voltage @ VDDINT = max 1.5 V
VIH Hi-Level CLKIN Voltage @ VDDINT = max 2.0 V
VIL Lo-Level Input Voltage1, 3 @ VDDINT = min 0.7 V
VOH Hi-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOH = –0.5 mA 2.0 V
@ VDDEXT = 3.0 V, IOH = –0.5 mA 2.4 V
6
@ VDDEXT = min, IOH = –100 mA VDDEXT – 0.3 V
VOL Lo-Level Output Voltage1, 4, 5 @ VDDEXT = min, IOL = 2 mA 0.4 V
IIH Hi-Level Input Current3 @ VDDINT = max, VIN = 3.6 V 10 ␮A
IIL Lo-Level Input Current 3
@ VDDINT = max, VIN = 0 V 10 ␮A
IOZH Three-State Leakage Current 7
@ VDDEXT = max, VIN = 3.6 V 8
10 ␮A
IOZL Three-State Leakage Current7 @ VDDEXT = max, VIN = 0 V8 10 ␮A
9
IDD Supply Current (Idle) @ VDDINT = 2.5, tCK = 15 ns 9 mA
@ VDDINT = 2.5, tCK = 13.3 ns 10 mA
9 10
IDD Supply Current (Dynamic) @ VDDINT = 2.5, 15 ns , TAMB = 25°C 35 mA
@ VDDINT = 2.5, 13.3 ns10, TAMB = 25°C 38 mA
IDD Supply Current (Power-Down) 11
@ VDDINT = 2.5, TAMB = 25°C in Lowest 100 ␮A
Power Mode
CI Input Pin Capacitance3, 6 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C 8 pF
CO Output Pin Capacitance6, 7, 11, 12 @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C 8 pF
NOTES
1
Bidirectional pins: D0–D3, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH
5
Although specified for TTL outputs, all ADSP-2185M outputs are CMOS compatible and will drive to VDDEXT and GND, assuming no dc loads.
6
Guaranteed but not tested
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7
8
0 V on BR
9
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunctional (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
10
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11
See Chapter 9 of the ADSP-2100 Family User’s Manual (3rd Edition, 9/95) for details.
12
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.

REV. 0 –5–
SST-Melody-DAP
ABSOLUTE MAXIMUM RATINGS 1 ORDERING INFORMATION
Internal Supply Voltage (VDDINT) . . . . . . . . . –0.3 V to +3.0 V The Analog Devices SST-Melody-DAP Reference Design
Internal Supply Voltage (VDDEXT) . . . . . . . . . –0.3 V to +4.0 V must be ordered under the part number ADSST-Melody-
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V SDK for the standalone reference design. This includes the
Output Voltage Swing3 . . . . . . . . . . –0.5 V to VDDEXT + 0.5 V evaluation board with an evaluation copy of the software and
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C schematics.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Designers of products using this reference design also will be
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . . 280°C required to sign a license agreement with the respective license
NOTES holder––i.e., Digital Theater Systems (DTS), Dolby Labora-
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional tories, THX Ltd., Microsoft, or SRS Labs––to use the
operation of the device at these or any other conditions above those listed in the appropriate code and produce proof to Analog Devices of
operational sections of this specification is not implied. Exposure to absolute having successfully completed the appropriate licensing proce-
maximum rating conditions for extended periods may affect device reliability. dures before final products can be shipped to them. The final
2
Applies to bidirectional pins (D0–D3, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1–A13, PF0–PF7) and input only pins (CLKIN, RESET, BR, DR0,
product will be shipped from Analog Devices and will include
DR1, PWD) the decoder chipset and software; customers will be required to
3
Applies to output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, sign license agreements with Analog Devices and separately pay
PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH) system royalties to the respective license holder.

100-LEAD LQFP
PIN CONFIGURATION
94 PF0 [MODE A]
93 PF1 [MODE B]

89 PF2 [MODE C]
88 PF3 [MODE D]
96 PWDACK
100 A3/IAD2
99 A2/IAD1
98 A1/IAD0

90 VDDEXT
91 PWD
95 BGH

92 GND

80 GND
84 D23
83 D22
82 D21
81 D20
87 FL0
86 FL1
85 FL2

79 D19
78 D18
77 D17
76 D16
97 A0

A4/IAD3 1 75 D15
PIN 1 74 D14
A5/IAD4 2 IDENTIFIER
GND 3 73 D13

A6/IAD5 4 72 D12

A7/IAD6 5 71 GND
A8/IAD7 6 70 D11

A9/IAD8 7 69 D10

A10/IAD9 8 68 D9

A11/IAD10 9 67 VDDEXT

A12/IAD11 10 66 GND
A13/IAD12 11 65 D8

GND 12 64 D7/IWR
SST-Melody-DAP
CLKIN 13 TOP VIEW 63 D6/IRD
(Not to Scale)
XTAL 14 62 D5/IAL
VDDEXT 15 61 D4/IS
CLKOUT 16 60 GND
GND 17 59 VDDINT

VDDINT 18 58 D3/IACK

WR 19 57 D2/IAD15

RD 20 56 D1/IAD14

BMS 21 55 D0/IAD13

DMS 22 54 BG

PMS 23 53 EBG

IOMS 24 52 BR

CMS 25 51 EBR
IRQL1+PF6 29

DT0 31

RFS0 33
IRQE+PF4 26
IRQL0+PF5 27
GND 28

IRQ2+PF7 30

DT1/FO 37

RFS1/IRQ0 39
TFS0 32

EINT 50
DR0 34

VDDEXT 36

TFS1/IRQ1 38

GND 41

ERESET 43
RESET 44

EE 46

ELOUT 48
ELIN 49
SCLK0 35

DR1/FI 40

EMS 45
SCLK1 42

ECLK 47

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the SST-Melody-DAP features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–6– REV. 0
 SST-Melody-DAP
The LQFP package pinout is shown in the Pin Function Descriptions. Pin names in bold text replace the plain text named functions
when Mode C = 1. A plus (+) sign separates two functions when either function can be active for either major I/O mode. Signals
enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI are mode selectable by setting Bit 10 (SPORT1 configure) of
the System Control register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt
and flag pins. This bit is set to 1 by default upon reset.

PIN FUNCTION DESCRIPTION

Pin Pin Pin Pin
No. Mnemonic No. Mnemonic No. Mnemonic No. Mnemonic
1 A4/IAD3 26 IRQE+PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0+PF5 52 BR 77 D17
3 GND 28 GND 53 EBG 78 D18
4 A6/IAD5 29 IRQL1+PF6 54 BG 79 D19
5 A7/IAD6 30 IRQ2+PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDDINT 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDDEXT 61 D4/IS 86 FL1
12 GND 37 DT1/FO 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1/IRQ1 63 D6/IRD 88 PF3 [MODE D]
14 XTAL 39 RFS1/IRQ0 64 D7/IWR 89 PF2 [MODE C]
15 VDDEXT 40 DR1/FI 65 D8 90 VDDEXT
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDDEXT 92 GND
18 VDDINT 43 ERESET 68 D9 93 PF1 [MODE B]
19 WR 44 RESET 69 D10 94 PF0 [MODE A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2

signal characteristics. Switching characteristics tell what the

TIMING SPECIFICATIONS processor will do in a given circumstance. Switching characteris-
GENERAL NOTES tics may be used to ensure that any timing requirement of a
Use the exact timing information given. Do not attempt to device connected to the processor (such as memory) is satisfied.
derive parameters from the addition or subtraction of others. Timing requirements apply to signals that are controlled by
While addition or subtraction would yield meaningful results for circuitry external to the processor, such as the data input for a
an individual device, the values given in this data sheet reflect read operation. Timing requirements guarantee that the proces-
statistical variations and worst cases. Consequently, the user sor operates correctly with other devices.
cannot meaningfully add up parameters to derive longer times.
MEMORY TIMING SPECIFICATIONS
TIMING NOTES Table I shows common memory device specifications and the
Switching characteristics specify how the processor changes its corresponding SST-Melody-DAP timing parameters, for your
signals. There is no control over this. Timing circuitry external convenience.
to the processor must be designed for compatibility with these

REV. 0 –7–
SST-Melody-DAP
Table I. Memory Timing Specifications Assumptions:
Memory Timing • External data memory is accessed every cycle with 50% of the
Device Parameter address pins switching.
Specification Parameter Definition* • External data memory writes occur every other cycle with
50% of the data pins switching.
Address Setup to tASW A0–A13, xMS Setup
Write Start before WR Low • Each address and data pin has a 10 pF total load at the pin.
Address Setup to tAW A0–A13, xMS Setup • The application operates at VDDEXT = 3.3 V and
Write End before WR Deasserted tCK = 30 ns.
Address Hold tWRA A0–A13, xMS Hold Total Power Dissipation = PINT + (C ⫻ VDDEXT2 ⫻ f)
Time before WR Low PINT = internal power dissipation from Power vs. Frequency
Data Setup Time tDW Data Setup before WR High graph (see Figures 2a through 2c).
Data Hold Time tDH Data Hold after WR High (C ⫻ VDDEXT2⫻ f) is calculated for each output:
OE to Data Valid tRDD RD Low to Data Valid
Table III. Power Dissipation Example
Address Access tAA A0–A13, xMS to
Time Data Valid No. of
C
VDDEXT2
f PD
*xMS = PMS, DMS, CMS, or IOMS. Parameter Pins (pF) (V) (MHz) (mW)

FREQUENCY DEPENDENCY FOR TIMING Address 7 10 3.32 16.67 12.7

SPECIFICATIONS Data Output, WR 9 10 3.32 16.67 16.6
tCK is defined as 0.5 tCKI. The SST-Melody-DAP uses an input RD 1 10 3.32 16.67 1.8
clock with a frequency equal to half the instruction rate. For CLKOUT, DMS 2 10 3.32 33.3 7.2
example, a 37.50 MHz input clock (which is equivalent to 26.6 ns) Total 38.2
yields a 13.3 ns processor cycle (equivalent to 75 MHz). tCK
values within the range of 0.5 tCKI period should be substituted Total power dissipation for this example is PINT + 38.0 mW.
for all relevant timing parameters to obtain the specification value.
Output Drive Currents
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (15 ns) – 2 ns = 5.5 ns Figure 1 shows typical I–V characteristics for the output
drivers on the SST-Melody-DAP. The curves represent the
Table II. Environmental Conditions* current drive capability of the output drivers as a function of
output voltage.
Rating
Description Symbol LQFP Mini-BGA
80
Thermal Resistance ␪CA 48°C/W 63.3°C/W
60 VOH
(Case-to-Ambient) VDDEXT – 3.6V @ –40C
Thermal Resistance ␪JA 50°C/W 70.7°C/W 40
SOURCE CURRENT – mA

VDDEXT – 3.3V @ +25C

(Junction-to-Ambient)
20
Thermal Resistance ␪JC 2°C/W 7.4°C/W VDDEXT – 2.5V @ +85C
(Junction-to-Case) 0

*Where the Ambient Temperature Rating (T AMB) is: –20 VDDEXT – 3.6V @ –40C
TAMB = TCASE – (PD ⫻ ␪CA)
TCASE = Case Temperature in °C –40 VOL VDDEXT – 2.5V @ +85C
PD = Power Dissipation in W
VDDEXT – 3.3V @ +25C
–60
POWER DISSIPATION
–80
To determine total power dissipation in a specific application, 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
the following equation should be applied for each output: SOURCE VOLTAGE – V

2
C × VDD × f Figure 1. Typical Output Driver Characteristics

C = load capacitance, f = output switching frequency.

Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:

–8– REV. 0
 SST-Melody-DAP
POWER, INTERNAL1, 2, 3 Capacitive Loading
115
110mW Figures 3 and 4 show the capacitive loading characteristics of
110 the SST-Melody-DAP.
105
100 VDD – 2.65V 30
95mW T = 85C
POWER (PINT) – mW

95 VDD = 0V TO 2.0V
90 25
VDD – 2.5V

RISE TIME (0.4V–2.4V) – ns

85 82mW 82mW
80 20
VDD – 2.35V
75 70mW
70 15

65 61mW
60 10

55
50 55 60 65 70 75 80
5
1/tCK – MHz

0
POWER, IDLE1, 2, 4 0 50 100 150 200 250 300
30
CL – pF
28mW
28
VDD – 2.65V Figure 3. Typical Output Rise Time vs. Load Capacitance
26 (at Maximum Ambient Operating Temperature)
POWER (PIDLE) – mW

24mW 24mW
24 18
VDD – 2.5V
16
22
VALID OUTPUT DELAY OR HOLD – ns

20mW 20mW 14
20 12
VDD – 2.35V
10
18
16.5mW 8
16 6

4
14
50 55 60 65 70 75 80 2
1/tCK – MHz
NOMINAL

–2
POWER, IDLE nMODES2 –4
26
24mW –6
0 50 100 150 200 250
24 IDLE
CL – pF

22 Figure 4. Typical Output Valid Delay or Hold vs.

POWER (PIDLEn ) – mW

20mW Load Capacitance, C L (at Maximum Ambient

20
Operating Temperature)
18
16.4mW
16 15mW IDLE (16)
IDLE (128)
15.7mW
14
14.25mW

12
50 55 60 65 70 75 80
1/tCK – MHz

NOTES
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 TYPICAL POWER DISSIPATION AT 2.5V V
DIDINT AND 25C, EXCEPT
WHERE SPECIFIED.
3 IDO MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING
FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE
MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 20% ARE TYPE 2 AND TYPE 6,
AND 20% ARE IDLE INSTRUCTIONS.
4 IDLE REFERS TO STATE OF OPERATING DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND.

Figure 2. Power vs. Frequency

REV. 0 –9–
SST-Melody-DAP
SOFTWARE ARCHITECTURE • Calling library module
The SST-Melody-DAP software programming model has • Status report
the following parts:
The executive kernel is executed as soon as booting takes place.
• Executive kernel The hardware resources are initialized in the beginning. The
• Algorithm suite as library modules “command buffer” and general-purpose programmable flag pins
The executive kernel has the following functions: are initialized. Various data buffers and memory variables are
initialized. Interrupts are programmed and enabled. Then defi-
• Power-up hardware initialization nite signatures are written “command buffer” to inform the host
• Serial port management that ADSP is ready to receive the commands. Once commands
• Automatic stream detect are issued by host micro, these are executed and appropriate
action takes place. Decoding is handled by issuing appropriate
• Automatic code load commands by host micro.
• Command processing The kernel communicates with the library module for a particu-
• Interrupt handling lar algorithm in a definite way. The details are found in the
specific implementation documents.
• Data buffer management

EXECUTIVE KERNEL

INPUT STREAM OUTPUT STREAM

DECODING LIBRARY

ARCHITECTURE OVERVIEW A powerful program sequencer and two dedicated data address
The SST-Melody-DAP instruction set provides flexible data generators ensure efficient delivery of operands to these compu-
moves and multifunction (one or two data moves with a com- tational units. The sequencer supports conditional jumps,
putation) instructions. Every instruction can be executed in a subroutine calls, and returns in a single cycle. With internal
single processor cycle. The SST-Melody-DAP assembly language loop counters and loop stacks, the SST-Melody-DAP executes
uses an algebraic syntax for ease of coding and readability. A looped code with zero overhead; no explicit jump instructions
comprehensive set of development tools supports program are required to maintain loops.
development. Two data address generators (DAGs) provide addresses for
A functional block diagram of the SST-Melody-DAP is pro- simultaneous dual operand fetches (from data memory and
vided. The processor contains three independent computational program memory). Each DAG maintains and updates four
units: the ALU, the multiplier/accumulator (MAC), and the address pointers. Whenever the pointer is used to access data
shifter. The computational units process 16-bit data directly (indirect addressing), it is postmodified by the value of one of
and have provisions to support multiprecision computations. four possible modify registers. A length value may be associated
The ALU performs a standard set of arithmetic and logic opera- with each pointer to implement automatic modulo addressing
tions; division primitives are also supported. The MAC performs for circular buffers.
single-cycle multiply, multiply/add, and multiply/subtract opera- Efficient data transfer is achieved with the use of five
tions with 40 bits of accumulation. The shifter performs logical internal buses:
and arithmetic shifts, normalization, denormalization, and de-
rive exponent operations. • Program Memory Address (PMA) Bus
The shifter can be used to efficiently implement numeric • Program Memory Data (PMD) Bus
format control, including multiword and block floating-point • Data Memory Address (DMA) Bus
representations.
• Data Memory Data (DMD) Bus
The internal result (R) bus connects the computational units so
• Result (R) Bus
that the output of any unit may be the input of any unit on the
next cycle.

–10– REV. 0
 SST-Melody-DAP
The two address buses (PMA and DMA) share a single external register (TSCALE). When the value of the count register reaches
address bus, allowing memory to be expanded off-chip. The two zero, an interrupt is generated and the count register is reloaded
databuses (PMD and DMD) share a single external databus. from a 16-bit period register (TPERIOD).
Byte memory space and I/O memory space also share the Serial Ports
external buses. The SST-Melody-DAP incorporates two complete synchronous
Program memory can store both instructions and data, permit- serial ports (SPORT0 and SPORT1) for serial communications
ting the SST-Melody-DAP to fetch two operands in a single and multiprocessor communication.
cycle, one from program memory and one from data memory. Here is a brief list of the capabilities of the SST-Melody-DAP
The SST-Melody-DAP can fetch an operand from program SPORTs:
memory and the next instruction in the same cycle. In lieu of
the address and databus for external memory connection, the • SPORTs are bidirectional and have a separate, double buff-
SST-Melody-DAP may be configured for 16-bit Internal DMA ered transmit and receive section.
port (IDMA port) connection to external systems. The IDMA • SPORTs can use an external serial clock or generate their
port is made up of 16 data/address pins and five control pins. own serial clock internally.
The IDMA port provides transparent, direct access to the DSP’s
• SPORTs have independent framing for the receive and trans-
on-chip program and data RAM.
mit sections. Sections run in a frameless mode or with frame
An interface to low cost byte-wide memory is provided by the synchronization signals internally or externally generated.
Byte DMA port (BDMA port). The BDMA port is bidirectional Frame sync signals are active high or inverted, with either of
and can directly address up to four megabytes of external RAM two pulsewidths and timings.
or ROM for off-chip storage of program overlays or data tables.
• SPORTs support serial data-word lengths from three to 16 bits
The byte memory and I/O memory space interface supports and provide optional A-law and µ-law companding
slow memories and I/O memory-mapped peripherals with pro- according to CCITT recommendation G.711.
grammable wait state generation. External devices can gain
• SPORT receive and transmit sections can generate unique
control of external buses with bus request/grant signals (BR,
interrupts on completing a data-word transfer.
BGH, and BG).
• SPORTs can receive and transmit an entire circular buffer of
One execution mode (Go Mode) allows the SST-Melody-DAP
data with only one overhead cycle per data-word. An inter-
to continue running from on-chip memory. Normal execution
rupt is generated after a data buffer transfer.
mode requires the processor to halt while buses are granted.
The SST-Melody-DAP can respond to 11 interrupts. There can • SPORT0 has a multichannel interface to selectively receive
be up to six external interrupts (one edge-sensitive, two level- and transmit a 24- or 32-word, time-division multiplexed,
sensitive, and three configurable) and seven internal interrupts serial bitstream.
generated by the timer, the serial ports (SPORTs), the Byte • SPORT1 can be configured to have two external interrupts
DMA port, and the power-down circuitry. There is also a mas- (IRQ0 and IRQ1) and the FI and FO signals. The internally
ter RESET signal. The two serial ports provide a complete generated serial clock may still be used in this configuration.
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit PIN DESCRIPTIONS
and receive modes of operation. The SST-Melody-DAP is available in a 100-lead LQFP package
Each port can generate an internal programmable serial clock or and a 144-ball mini-BGA package. In order to maintain maxi-
accept an external serial clock. mum functionality and reduce package size and pin count, some
serial port, programmable flag, interrupt, and external bus pins
The SST-Melody-DAP provides up to 13 general-purpose
have dual multiplexed functionality. The external bus pins are
flag pins. The data input and output pins on SPORT1 can be
configured during RESET only, while serial port pins are soft-
alternatively configured as an input flag and an output flag.
ware configurable during program execution. Flag and interrupt
In addition, eight flags are programmable as inputs or out-
functionality is retained concurrently on multiplexed pins. In
puts, and three flags are always outputs.
cases where pin functionality is reconfigurable, the default state
A programmable interval timer generates periodic interrupts. is shown in plain text; alternate functionality is shown in italics.
A 16-bit count register (TCOUNT) decrements every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit

REV. 0 –11–
SST-Melody-DAP
Common-Mode Pins
Mnemonic No. of Pins I/O Function
RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2 1 I Edge- or Level-Sensitive Interrupt Request1
PF7 I/O Programmable I/O Pin
IRQL1 1 I Level-Sensitive Interrupt Requests1
PF6 I/O Programmable I/O Pin
IRQL0 1 I Level-Sensitive Interrupt Requests1
PF5 I/O Programmable I/O Pin
IRQE 1 I Edge-Sensitive Interrupt Requests1
PF4 I/O Programmable I/O Pin
Mode D 1 I Mode Select Input—Checked Only During RESET
PF3 I/O Programmable I/O Pin During Normal Operation
Mode C 1 I Mode Select Input—Checked Only During RESET
PF2 I/O Programmable I/O Pin During Normal Operation
Mode B 1 I Mode Select Input—Checked Only During RESET
PF1 I/O Programmable I/O Pin During Normal Operation
Mode A 1 I Mode Select Input—Checked Only During RESET
PF0 I/O Programmable I/O Pin During Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1:IRQ0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO2
PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
VDDINT 2 I Internal VDD (2.5 V) Power (LQFP)
VDDEXT 4 I External VDD (2.5 V or 3.3 V) Power (LQFP)
GND 10 I Ground (LQFP)
VDDINT 4 I Internal VDD (2.5 V) Power (Mini-BGA)
VDDEXT 7 I External VDD (2.5 V or 3.3 V) Power (Mini-BGA)
GND 20 I Ground (Mini-BGA)
EZ-Port 9 I/O For Emulation Use
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector
address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.

–12– REV. 0
 SST-Melody-DAP
Memory Interface Pins
The SST-Melody-DAP processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The
operating mode is determined by the state of the Mode C Pin during RESET and cannot be changed while the processor is running.
The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or
Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.

Full Memory Mode Pins (Mode C = 0)

Mnemonic No. of Pins I/O Function
A13:0 14 O Address Output Pins for Program, Data, Byte, and I/O Spaces
D23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces
(8 MSBs are also used as Byte Memory Addresses)

Host Mode Pins (Mode C = 1)

Mnemonic No. of Pins I/O Function
IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Program, Data, or
Byte Access*
D23:8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR 1 I IDMA Write Enable
IRD 1 I IDMA Read Enable
IAL 1 I IDMA Address Latch Pin
IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain
*In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

Table IV. Pin Terminations 1, 2, 3, 4

Table IV shows the recommendations for terminating unused pins.
I/O Three-State Reset Hi-Z5
Mnemonic (Z) State Caused By Unused Configuration
XTAL I I Float
CLKOUT O O Float
A13:1 or O (Z) Hi-Z BR, EBR Float
IAD 12:0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
D23:8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD I I BR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D2:0 or I/O (Z) Hi-Z BR, EBR Float
IAD15:13 I/O (Z) Hi-Z IS Float

REV. 0 –13–
SST-Melody-DAP
Table IV. Pin Terminations (continued)
I/O Three-State Reset Hi-Z5
Mnemonic (Z) State Caused By Unused Configuration
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive) or
Program as Output, Set to 1,
Let Float
IRQL1/PF6 I/O (Z) I Input = High (Inactive) or
Program as Output, Set to 1,
Let Float
IRQL0/PF5 I/O (Z) I Input = High (Inactive) or
Program as Output, Set to 1,
Let Float
IRQE/PF4 I/O (Z) I Input = High (Inactive) or
Program as Output, Set to 1,
Let Float
SCLK0 I/O I Input = High or Low,
Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O I High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low,
Output = Float
RFS1/IRQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/IRQ1 I/O I High or Low
DT1/FO O O Float
EE I I Float
EBR I I Float
EBG O O Float
ERESET I I Float
EMS O O Float
EINT I I Float
ECLK I I Float
ELIN I I Float
ELOUT O O Float
NOTES
1
If the CLKOUT Pin is not used, turn it off using CLKODIS in SPORT0 autobuffer control register.
2
If the interrupt/programmable flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts
and input flag pins, pull the pins high (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.
3
All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
4
CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used.
5
Hi-Z = High impedance.

–14– REV. 0
 SST-Melody-DAP
Interrupts LOW POWER OPERATION
The interrupt controller allows the processor to respond to the The SST-Melody-DAP has three low power modes that signifi-
11 possible interrupts and reset with minimum overhead. The cantly reduce the power dissipation when the device operates
SST-Melody-DAP provides four dedicated external interrupt under standby conditions. These modes are:
input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the • Power-Down
PF7:4 Pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FI, and FO, for a total of six external interrupts. • Idle
The SST-Melody-DAP also supports internal interrupts from • Slow Idle
the timer, the byte DMA port, the two serial ports, software,
The CLKOUT Pin may also be disabled to reduce external
and the power-down control circuit. The interrupt levels are
power dissipation.
internally prioritized and individually maskable (except power-
down and RESET). The IRQ2, IRQ0, and IRQ1 input pins can Power-Down
be programmed to be either level- or edge-sensitive. IRQL0 and The SST-Melody-DAP processor has a low power feature that
IRQL1 are level-sensitive and IRQE is edge-sensitive. The priori- lets the processor enter a very low power dormant state through
ties and vector addresses of all interrupts are shown in Table V. hardware or software control. Following is a brief list of power-
down features. Refer to the ADSP-2100 Family User’s Manual,
Table V. Interrupt Priority and Interrupt Vector Addresses “System Interface” chapter, for detailed information about the
power-down feature.
Interrupt Vector
• Quick recovery from power-down. The processor begins
Source of Interrupt Address (Hex)
executing instructions in as few as 200 CLKIN cycles.
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) • Support for an externally generated TTL or CMOS processor
Power-Down (Nonmaskable) 002C clock. The external clock can continue running during power-
IRQ2 0004 down without affecting the lowest power rating and 200
IRQL1 0008 CLKIN cycle recovery.
IRQL0 000C
SPORT0 Transmit 0010 • Support for crystal operation includes disabling the oscillator
SPORT0 Receive 0014 to save power (the processor automatically waits approxi-
IRQE 0018 mately 4096 CLKIN cycles for the crystal oscillator to start or
BDMA Interrupt 001C stabilize), and letting the oscillator run to allow 200 CLKIN
SPORT1 Transmit or IRQ1 0020 cycle startup.
SPORT1 Receive or IRQ0 0024 • Power-down is initiated by either the Power-Down pin (PWD)
Timer 0028 (Lowest Priority) or the software Power-Down Force bit. Interrupt support
allows an unlimited number of instructions to be executed
Interrupt routines can either be nested with higher priority before optionally powering down. The power-down interrupt
interrupts taking precedence or processed sequentially. Inter- also can be used as a nonmaskable, edge-sensitive interrupt.
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits • Context clear/save control allows the processor to continue
in IMASK; the highest priority unmasked interrupt is then where it left off or start with a clean context when leaving the
selected. The power-down interrupt is nonmaskable. power-down state.
The SST-Melody-DAP masks all interrupts for one instruction • The RESET pin also can be used to terminate power-down.
cycle following the execution of an instruction that modifies • Power-Down Acknowledge pin indicates when the processor
the IMASK register. This does not affect serial port autobuffering has entered power-down.
or DMA transfers. Idle
The interrupt control register, ICNTL, controls interrupt nest- When the SST-Melody-DAP is in the Idle mode, the processor
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts waits indefinitely in a low power state until an interrupt occurs.
to be either edge or level-sensitive. The IRQE pin is an external When an unmasked interrupt occurs, it is serviced; execution then
edge-sensitive interrupt and can be forced and cleared. The continues with the instruction following the IDLE instruction. In
IRQL0 and IRQL1 pins are external level-sensitive interrupts. Idle mode, IDMA, BDMA, and autobuffer cycle steals still occur.
The IFC register is a write-only register used to force and clear Slow Idle
interrupts. On-chip stacks preserve the processor status and are The IDLE instruction is enhanced on the SST-Melody-DAP
automatically maintained during interrupt handling. The stacks to let the processor’s internal clock signal be slowed, further
are 12 levels deep to allow interrupt, loop, and subroutine reducing power consumption. The reduced clock frequency, a
nesting. The following instructions allow global enable or dis- programmable fraction of the normal clock rate, is specified
able servicing of the interrupts (including power-down), by a selectable divisor given in the IDLE instruction.
regardless of the state of IMASK. Disabling the interrupts does
not affect serial port autobuffering or DMA. The format of the instruction is:
IDLE (n);
ENA INTS;
where n = 16, 32, 64, or 128. This instruction keeps the proces-
DIS INTS; sor fully functional, but operating at the slower clock rate. While
When the processor is reset, interrupt servicing is enabled. it is in this state, the processor’s other internal clock signals

REV. 0 –15–
SST-Melody-DAP
(such as SCLK, CLKOUT) and timer clock are reduced by the Host Memory mode allows access to the full external databus,
same ratio. The default form of the instruction, when no clock but limits addressing to a single address bit (A0). Through the
divisor is given, is the standard IDLE instruction. use of external hardware, additional system peripherals can
When the IDLE (n) instruction is used, it effectively slows be added in this mode to generate and latch address signals.
down the processor’s internal clock and thus its response time Clock Signals
to incoming interrupts. The one-cycle response time of the The SST-Melody-DAP can be clocked by either a crystal or a
standard idle state is increased by n, the clock divisor. When an TTL compatible clock signal. The CLKIN input cannot be
enabled interrupt is received, the SST-Melody-DAP will remain halted, changed during operation, nor operated below the
in the idle state for up to a maximum of n processor cycles specified frequency during normal operation. The only exception
(n = 16, 32, 64, or 128) before resuming normal operation. is while the processor is in the power-down state.
When the IDLE (n) instruction is used in systems that have an If an external clock is used, it should be a TTL compatible
externally generated serial clock (SCLK), the serial clock rate signal running at half the instruction rate. The signal is con-
may be faster than the processor’s reduced internal clock rate. nected to the processor’s CLKIN input. When an external
Under these conditions, interrupts must not be generated at a clock is used, the XTAL input must be left unconnected.
faster than can be serviced rate, due to the additional time the The SST-Melody-DAP uses an input clock with a frequency
processor takes to come out of the idle state (a maximum of n equal to half the instruction rate; a 37.50 MHz input clock yields
processor cycles). a 13 ns processor cycle (which is equivalent to 75 MHz).
Normally, instructions are executed in a single processor cycle.
SYSTEM INTERFACE All device timing is relative to the internal instruction clock rate,
Figure 5 shows typical basic system configurations with the which is indicated by the CLKOUT signal when enabled.
SST-Melody-DAP, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories Because the SST-Melody-DAP includes an on-chip oscillator
(mode-selectable). Programmable wait state generation allows circuit, an external crystal may be used. The crystal should be
the processor to connect easily to slow peripheral devices. The connected across the CLKIN and XTAL pins, with two capacitors
SST-Melody-DAP also provides four external interrupts and connected as shown in Figure 6. Capacitor values are dependent
two serial ports or six external interrupts and one serial port.

FULL MEMORY MODE HOST MEMORY MODE

SST-Melody-DAP
1/2x CLOCK CLKIN 1/2x CLOCK CLKIN
OR 14 A13–0 OR XTAL
CRYSTAL XTAL CRYSTAL
ADDR13–0 1
FL0–2 D23–16 A0–A21 FL0–2 A0

24 D15–0 BYTE IRQ2+PF7 16

IRQ2+PF7
DATA23–0 DATA MEMORY IRQE+PF4 DATA23–0
IRQE+PF4
IRQL0+PF5
IRQL0+PF5 SST-Melody-DAP BMS
BMS CS IRQL1+PF6
IRQL1+PF6
MODE D/PF3 WR
WR A10–0
MODE D/PF3 ADDR MODE C/PF2 RD
RD
MODE C/PF2 D23–0
I/O SPACE MODE A/PF0
MODE A/PF0 DATA (PERIPHERALS) MODE B/PF1
MODE B/PF1 2040 LOCATIONS
IOMS CS SPORT1 IOMS
SPORT1 SCLK1
A13–0
SCLK1 RFS1/IRQ0
ADDR SERIAL
RFS1/IRQ0 OVERLAY TFS1/IRQ1
SERIAL D23–0 DEVICE
TFS1/IRQ1 MEMORY
DEVICE DATA DT1/FO
DT1/FO TWO 8K DR1/FI PMS
PMS
DR1/FI PM SEGMENTS
DMS
DMS
CMS TWO 8K SPORT0 CMS
SPORT0 DM SEGMENTS SCLK0
SCLK0 BR RFS0 BR
SERIAL
SERIAL
RFS0 BG DEVICE TFS0 BG
DEVICE TFS0 BGH DT0 BGH
DT0 PWD DR0 PWD
DR0 PWDACK PWDACK
IDMA PORT
D6/IRD
SYSTEM D7/IWR
INTERFACE D4/IS
OR D5/IAL
CONTROLLER D3/IACK
IAD15–0
16

Figure 5. Basic System Interface

–16– REV. 0
 SST-Melody-DAP
on crystal type and should be specified by the crystal manufac- The RESET input contains some hysteresis; however, if an RC
turer. A parallel-resonant, fundamental frequency, circuit is used to generate the RESET signal, the use of an external
microprocessor-grade crystal should be used. Schmitt trigger is recommended.
A clock output (CLKOUT) signal is generated by the processor The master reset sets all internal stack pointers to the empty
at the processor’s cycle rate. This can be enabled and disabled stack condition, masks all interrupts, and clears the MSTAT
by the CLKODIS bit in the SPORT0 Autobuffer Control register. register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
CLKIN XTAL CLKOUT
on-chip program memory location 0x0000 once boot loading
completes.
DSP
Power Supplies
The SST-Melody-DAP has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power sup-
Figure 6. External Crystal Connections plies. The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V supply.
RESET All external supply pins must be connected to the same supply. All
The RESET signal initiates a master reset of the SST-Melody- input and I/O pins can tolerate input voltages up to 3.6 V, regard-
DAP. The RESET signal must be asserted during the power-up less of the external supply voltage. This feature provides
sequence to assure proper initialization. maximum flexibility in mixing 2.5 V and 3.3 V components.
RESET during initial power-up must be held long enough to
allow the internal clock to stabilize. If RESET is activated any MODES OF OPERATION
time after power-up, the clock continues to run and does not Setting Memory Mode
require stabilization time. The power-up sequence is defined as Memory Mode selection for the SST-Melody-DAP is made
the total time required for the crystal oscillator circuit to stabi- during chip reset through the use of the Mode C pin. This pin is
lize after a valid VDD is applied to the processor, and for the multiplexed with the DSP’s PF2 pin, so care must be taken in
internal phase-locked loop (PLL) to lock onto the specific crys- how the mode selection is made. The two methods for selecting
tal frequency. A minimum of 2000 CLKIN cycles ensures that the value of Mode C are active and passive.
the PLL has locked but does not include the crystal oscillator
Passive Configuration
start-up time. During this power-up sequence, the RESET
signal should be held low. On any subsequent resets, the RESET Passive configuration involves the use of a pull-up or pull-down
signal must meet the minimum pulsewidth specification, tRSP. resistor connected to the Mode C pin. To minimize power

Table VI. Modes of Operation

Mode D Mode C Mode B Mode A Booting Method

X 0 0 0 BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory mode.*
X 0 1 0 No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory mode. BDMA can
still be used, but the processor does not automatically use or wait for these
operations.
0 1 0 0 BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host mode; IACK has active pull-down
(requires additional hardware).
0 1 0 1 IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written to.
Chip is configured in Host mode. IACK has active pull-down.*
1 1 0 0 BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host mode; IACK requires external pull-
down (requires additional hardware).
1 1 0 1 IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written to.
Chip is configured in Host mode. IACK requires external pull down.*
*Considered standard operating settings. Using these configurations allows for easier design and better memory management.

REV. 0 –17–
SST-Melody-DAP
consumption, or if the PF2 pin is to be used as an output in the Active Configuration
DSP application, a weak pull-up or pull-down, on the order of Active configuration involves the use of a three-statable external
10 kΩ, can be used. This value should be sufficient to pull the pin driver connected to the Mode C pin. A driver’s output enable
to the desired level and still allow the pin to operate as a program- should be connected to the DSP’s RESET signal such that it
mable flag output without undue strain on the processor’s output only drives the PF2 pin when RESET is active low. When
driver. For minimum power consumption during power-down, RESET is deasserted, the driver should three-state, thus
reconfigure PF2 to be an input, as the pull-up or pull-down will allowing full use of the PF2 pin as either an input or output. To
hold the pin in a known state, and will not switch. minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and will not oscillate should the three-state driver’s level
hover around the logic switching point.

PM (MODE B = 0) PM (MODE B = 1)1

ALWAYS
ACCESSIBLE
RESERVED 0x2000 –
AT ADDRESS
0x0000 – 0x1FFF 0x3FFF

0x2000 – ACCESSIBLE WHEN 0x0000 –

0x3FFF PMOVLAY = 0 0x1FFF2
ACCESSIBLE WHEN
PMOVLAY = 0 ACCESSIBLE WHEN 0x0000 –
PMOVLAY = 0 0x1FFF2
0x2000 –
0x3FFF2
ACCESSIBLE WHEN EXTERNAL RESERVED
PMOVLAY = 1 MEMORY
0x2000 –
0x3FFF2
NOTES
ACCESSIBLE WHEN 1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
EXTERNAL
MEMORY PMOVLAY = 2 2SEE TABLE VII FOR PMOVLAY BITS

PROGRAM MEMORY PROGRAM MEMORY

MODE B = 0 ADDRESS MODE B = 1 ADDRESS
0x3FFF 0x3FFF
8K INTERNAL
PMOVLAY = 0
8K INTERNAL
OR
PMOVLAY = 0
8K EXTERNAL
PMOVLAY = 1, 2 0x2000 0x2000
0x1FFF 0x1FFF
8K 8K
INTERNAL EXTERNAL
0x0000 0x0000

Figure 7. Program Memory

Table VII. PMOVLAY Bits

PMOVLAY Memory A13 A12:0
0 Internal Not Applicable Not Applicable
1 External Overlay 1 0 13 LSBs of Address between 0x2000 and 0x3FFF
2 External Overlay 2 1 13 LSBs of Address between 0x2000 and 0x3FFF

–18– REV. 0
 SST-Melody-DAP
IACK Configuration MEMORY ARCHITECTURE
Mode D = 0 and in Host Mode, IACK is an active, driven The SST-Melody-DAP provides a variety of memory and pe-
signal and cannot be “Wire-Ored.” ripheral interface options. The key functional groups are
Mode D = 1 and in Host Mode, IACK is an open drain and program memory, data memory, byte memory, and I/O. Refer
requires an external pull-down, but multiple IACK pins can be to the following figures and tables for PM and DM memory
“Wire-Ored” together. allocations in the SST-Melody-DAP.

DATA MEMORY DATA MEMORY ADDR

32 MEMORY 0x3FFF
ALWAYS MAPPED
ACCESSIBLE REGISTERS 0x3FE0
AT ADDRESS
0x2000 – 0x3FFF 0x3FDF
INTERNAL
8160 WORDS
0x2000
0x0000–0x1FFF
0x1FFF
ACCESSIBLE WHEN 8K INTERNAL
DMOVLAY = 0 DMOVLAY = 0
0x0000–0x1FFF* OR
EXTERNAL 8K
0x0000–0x1FFF* DMOVLAY = 1, 2
ACCESSIBLE WHEN 0x0000
DMOVLAY = 1

EXTERNAL ACCESSIBLE WHEN *SEE TABLE VIII FOR DMOVLAY BITS

MEMORY DMOVLAY = 2

Figure 8. Program Memory

Table VIII. DMOVLAY Bits

DMOVLAY Memory A13 A12:0
0 Internal Not Applicable Not Applicable
1 External Overlay 1 0 13 LSBs of Address between 0x2000 and 0x3FFF
2 External Overlay 2 1 13 LSBs of Address between 0x2000 and 0x3FFF

WAIT STATE CONTROL

Program Memory
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Program memory (Full Memory mode) is a 24-bit wide space 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0
3FFE)
for storing both instruction opcodes and data. The SST-Melody-
DAP has 16K words of program memory RAM on-chip, and DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
the capability of accessing up to two 8K external memory overlay
WAIT STATE MODE SELECT
spaces using the external databus. 0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 – N WAIT STATES, RANGING
FROM 0 TO 7)
Program memory (Host mode) allows access to all internal 1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 – 2N + 1 WAIT STATES, RANGING
FROM 0 TO 15)
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in Figure 9. Wait State Control Register
Host Mode due to a restricted databus that is 16 bits wide only.
PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL
Data Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data memory (Full Memory mode) is a 16-bit wide space used 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 DM(0
3FE6)
for the storage of data variables and for memory-mapped con-
trol registers. The SST-Melody-DAP has 16K words on BMWAIT CMSSEL PFTYPE
0 = DISABLE CMS 0 = INPUT
data memory RAM on-chip. Part of this space is used by 1 = ENABLE CMS 1 = OUTPUT
32 memory-mapped registers. Support also exists for up to two 8K (WHERE BIT: 11–IOM, 10–BM, 9–DM, 8–PM)
external memory overlay spaces through the external databus.
Figure 10. Programmable Flag and Composite
All internal accesses complete in one cycle. Accesses to external
Control Register
memory are timed using the wait states specified by the DWAIT
register and the Wait State mode bit.

REV. 0 –19–
SST-Melody-DAP
Memory-Mapped Registers (New to the SST-Melody-DAP) Each bit in the CMSSEL register, when set, causes the CMS
The SST-Melody-DAP has three memory-mapped registers signal to be asserted when the selected memory select is
that differ from other ADSP-21xx Family DSPs. The slight asserted. For example, to use a 32K word memory to act as
modifications to these registers (Wait State Control, Program- both program and data memory, set the PMS and DMS bits in
mable Flag and Composite Select Control, and System Control) the CMSSEL register and use the CMS Pin to drive the chip
provide the SST-Melody-DAP’s wait state and BMS control select of the memory, and use either DMS or PMS as the addi-
features. Default bit values at reset are shown; if no value is tional address bit.
shown, the bit is undefined at reset. Reserved bits are shown on The CMS pin functions like the other memory select signals
a gray field. These bits should always be written with zeros. with the same timing and bus request logic. A “1” in the enable
Data Memory (Host Mode) allows access to all internal bit causes the assertion of the CMS signal at the same time as
memory. External overlay access is limited by a single external the selected memory select signal. All enable bits default to 1 at
address line (A0). reset, except the BMS bit.
SYSTEM CONTROL
Byte Memory Select (BMS)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The SST-Melody-DAP’s BMS disable feature, combined with
0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0
3FFF) the CMS pin, allows use of multiple memories in the byte
memory space. For example, an EPROM could be attached to
RESERVED, ALWAYS PWAIT
RESERVED
SET TO 0 SET TO 0 PROGRAM MEMORY the BMS select, and an SRAM could be connected to CMS.
SPORT0 ENABLE
WAIT STATES Because BMS is enabled at reset, the EPROM would be used
0 = DISABLE
1 = ENABLE
DISABLE BMS for booting. After booting, software could disable BMS and set
0 = ENABLE BMS
SPORT1 ENABLE 1 = DISABLE BMS, EXCEPT WHEN MEMORY the CMS signal to respond to BMS, enabling the SRAM.
0 = DISABLE STROBES ARE THREE-STATED
1 = ENABLE Byte Memory
SPORT1 CONFIGURE The byte memory space is a bidirectional, 8-bit wide, external
0 = FI, FO, IRQ0, IRQ1, SCLK memory space used to store programs and data. Byte memory is
1 = SPORT1
accessed using the BDMA feature. The byte memory space
RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS. consists of 256 pages, each of which is 16K ⫻ 8. The byte
memory space on the SST-Melody-DAP supports read and
Figure 11. System Control Register write operations as well as four different data formats. The
I/O Space (Full Memory Mode) byte memory uses data bits 15:8 for data. The byte memory
The SST-Melody-DAP supports an additional external memory uses data bits 23:16 and address bits 13:0 to create a 22-bit
space called I/O space. This space is designed to support simple address. This allows up to a 4 meg ⫻ 8 (32 megabit) ROM or
connections to peripherals (such as data converters and external RAM to be used without glue logic. All byte memory accesses are
registers) or to bus interface ASIC data registers. I/O space timed by the BMWAIT register and the Wait State Mode bit.
supports 2048 locations of 16-bit wide data. The lower 11 bits Byte Memory DMA (BDMA, Full Memory Mode)
of the external address bus are used; the upper three bits are The byte memory DMA controller allows loading and storing of
undefined. Two instructions were added to the core ADSP-2100 program instructions and data using the byte memory space.
Family instruction set to read from and write to I/O memory The BDMA circuit is able to access the byte memory space
space. The I/O space also has four dedicated 3-bit wait state while the processor is operating normally and steals only one
registers, IOWAIT0–3, which in combination with the wait state DSP cycle per 8-, 16-, or 24-bit word transferred.
mode bit specify up to 15 wait states to be automatically gener-
ated for each of four regions. The wait states act on address ranges BDMA CONTROL
as shown in Table IX. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM(0
3FE3)

Table IX. Wait States BMPAGE BDMA BTYPE

OVERLAY
BITS BDIR
Address Range Wait State Register 0 = LOAD FROM BM
1 = STORE TO BM
0x000–1x1FF IOWAIT0 and Wait State Mode Select Bit BCR
0x200–3x1FF IOWAIT1 and Wait State Mode Select Bit 0 = RUN DURING BDMA
1 = HALT DURING BDMA
0x400–5x1FF IOWAIT2 and Wait State Mode Select Bit
0x600–7x1FF IOWAIT3 and Wait State Mode Select Bit Figure 12. BDMA Control Register

Composite Memory Select (CMS) The BDMA circuit supports four different data formats that are
The SST-Melody-DAP has a programmable memory select selected by the BTYPE register field. The appropriate number
signal that is useful for generating memory select signals for of 8-bit accesses are done from the byte memory space to build
memories mapped to more than one space. The CMS signal the word size selected. Table X shows the data formats sup-
is generated to have the same timing as each of the individual ported by the BDMA circuit.
memory select signals (PMS, DMS, BMS, IOMS) but can
combine their functionality.

–20– REV. 0
 SST-Melody-DAP
Table X. Data Formats 3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
BTYPE Internal Memory Space Word Size Alignment into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of Bits 7:0 represent the IDMA overlay and bits 14:8
00 Program Memory 24 Full Word
must be set to 0. If Bit 15 = 0, the value of Bits 13:0 represent
01 Data Memory 16 Full Word
the starting address of internal memory to be accessed and
10 Data Memory 8 MSBs
Bit 14 reflects PM or DM for access. For SST-Melody-DAP,
11 Data Memory 8 LSBs
IDDMOVLAY and IDPMOVLAY bits in the IDMA Overlay
Unused bits in the 8-bit data memory formats are filled with 0s. register should be set to zero.
The BIAD register field is used to specify the starting address 4. Host uses IS and IRD (or IWR) to read (or write) DSP
for the on-chip memory involved with the transfer. The 14-bit internal memory (PM or DM).
BEAD register specifies the starting address for the external
5. Host checks IACK line to see if the DSP has completed the
byte memory space. The 8-bit BMPAGE register specifies the
previous IDMA operation.
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally, the 14-bit 6. Host ends IDMA transfer.
BWCOUNT register specifies the number of DSP words to The IDMA port has a 16-bit multiplexed address and databus and
transfer and initiates the BDMA circuit transfers. supports 24-bit program memory. The IDMA port is completely
BDMA accesses can cross page boundaries during sequential asynchronous and can be written while the SST-Melody-DAP is
addressing. A BDMA interrupt is generated on the completion of operating at full speed.
the number of transfers specified by the BWCOUNT register. The DSP memory address is latched and then automatically
The BWCOUNT register is updated after each transfer so it incremented after each IDMA transaction. An external device
can be used to check the status of the transfers. When it can therefore access a block of sequentially addressed memory
reaches zero, the transfers have finished and a BDMA interrupt by specifying only the starting address of the block. This increases
is generated. The BMPAGE and BEAD registers must not be throughput as the address does not have to be sent for each
accessed by the DSP during BDMA operations. memory access.
The source or destination of a BDMA transfer will always be IDMA port access occurs in two phases. The first is the IDMA
on-chip program or data memory. Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
When the BWCOUNT register is written with a nonzero value,
an external device. The address specifies an on-chip memory
the BDMA circuit starts executing byte memory accesses with
location, the destination type specifies whether it is a DM or
wait states set by BMWAIT. These accesses continue until the
PM access. The falling edge of the IDMA address latch signal
count reaches zero. When enough accesses have occurred to
(IAL) or the missing edge of the IDMA select signal (IS) latches
create a destination word, it is transferred to or from on-chip
this value into the IDMAA register.
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory accesses. Once the address is stored, data can be read from or written to,
the SST-Melody-DAP’s on-chip memory. Asserting the select
The BDMA Context Reset bit (BCR) controls whether the
line (IS) and the appropriate read or write line (IRD and IWR
processor is held off while the BDMA accesses are occurring.
respectively) signals the SST-Melody-DAP that a particular
Setting the BCR bit to 0 allows the processor to continue opera-
transaction is required. In either case, there is a one processor
tions. Setting the BCR bit to 1 causes the processor to stop
cycle delay for synchronization. The memory access consumes
execution while the BDMA accesses are occurring, to clear the
one additional processor cycle.
context of the processor, and start execution at address 0 when
the BDMA accesses have completed. Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
The BDMA Overlay bits specify the OVLAY memory blocks to
be accessed for internal memory. For SST-Melody-DAP, set to Through the IDMAA register, the DSP can also specify the
zero BDMA Overlay bits in the BDMA Control register. starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
The BMWAIT field, which has four bits on SST-Melody-DAP,
the SST-Melody-DAP to write the address onto the IAD0–14 bus
allows selection up to 15 wait states for BDMA transfers.
into the IDMA control register. If Bit 15 is set to 0, IDMA
Internal Memory DMA Port (IDMA Port; Host Memory Mode) latches the address. If Bit 15 is set to 1, IDMA latches into the
The IDMA port provides an efficient means of communication OVLAY register. This register, shown in Figure 13, is memory-
between a host system and the SST-Melody-DAP. The port is mapped at address DM (0x3FE0). Note that the latched address
used to access the on-chip program memory and data memory (IDMAA) cannot be read back by the host. For SST-Melody-
of the DSP with only one DSP cycle per word overhead. The DAP, IDDMOVLAY and IDPMOVLAY bits in the IDMA
IDMA port cannot, however, be used to write to the DSP’s overlay register should be set to 0.
memory-mapped control registers. A typical IDMA transfer
Refer to the following figures for more information on IDMA
process is described as follows:
and DMA memory maps.
1. Host starts IDMA transfer
2. Host checks IACK control line to see if the DSP is busy

REV. 0 –21–
SST-Melody-DAP
IDMA OVERLAY IDMA Port Booting
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The SST-Melody-DAP can also boot programs through its
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM(0x3FE7)
Internal DMA port. If Mode C = 1, Mode B = 0, and Mode
RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY A = 1, the SST-Melody-DAP boots from the IDMA port. The
SHORT READ ONLY IDMA feature can load as much on-chip memory as desired.
0 = ENABLE Program execution is held off until on-chip program memory
RESERVED SET TO 0 1 = DISABLE
location 0 is written to.
IDMA CONTROL (U = UNDEFINED AT RESET) Bus Request and Bus Grant
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The SST-Melody-DAP can relinquish control of the data and
0 U U U U U U U U U U U U U U U DM(0x3FE70)
address buses to an external device. When the external device
IDMAA ADDRESS requires access to memory, it asserts the bus request (BR) signal.
IDMAD DESTINATION MEMORY TYPE If the SST-Melody-DAP is not performing an external memory
0 = PM access, it responds to the active BR input in the following processor
RESERVED SET TO 0 1 = DM
cycle by:
RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD
ALWAYS BE WRITTEN WITH ZEROS. • Three-stating the data and address buses and the PMS, DMS,
Figure 13. IDMA Control/OVLAY Registers BMS, CMS, IOMS, RD, and WR output drivers,
• Asserting the bus grant (BG) signal, and
DMA DMA • Halting program execution.
PROGRAM MEMORY DATA MEMORY
OVLAY OVLAY If Go mode is enabled, the SST-Melody-DAP will not halt
program execution until it encounters an instruction that requires
ALWAYS ALWAYS
ACCESSIBLE ACCESSIBLE
an external memory access.
AT ADDRESS AT ADDRESS
0x0000 – 0x1FFF 0x2000 – 0x3FFF If the SST-Melody-DAP is performing an external memory
access when the external device asserts the BR signal, it will not
0x2000 – 0x0000 – three-state the memory interfaces nor assert the BG signal until
0x3FFF 0x1FFF
ACCESSIBLE WHEN ACCESSIBLE WHEN the processor cycle after the access completes. The instruction
PMOVLAY = 0 DMOVLAY = 0
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
IDMA AND SDMA HAVE SEPARATE DMA CONTROL REGISTERS.
When the BR signal is released, the processor releases the BG
Figure 14. Direct Memory Access––PM and DM signal, re-enables the output drivers, and continues program
Memory Maps execution from the point at which it stopped.
Bootstrap Loading (Booting) The bus request feature operates at all times, including when
The SST-Melody-DAP has two mechanisms to allow automatic the processor is booting and when RESET is active.
loading of the internal program memory after reset. The method
The BGH pin is asserted when the SST-Melody-DAP requires
for booting is controlled by the Mode A, B, and C Configura-
the external bus for a memory or BDMA access, but is stopped.
tion bits.
The other device can release the bus by deasserting the bus
When the MODE pins specify BDMA booting, the SST-Melody- request. Once the bus is released, the SST-Melody-DAP deasserts
DAP initiates a BDMA boot sequence when reset is released. BG and BGH and executes the external memory access.
The BDMA interface is set up during reset to the following Flag I/O Pins
defaults when BDMA booting is specified: the BDIR, BMPAGE, The SST-Melody-DAP has eight general-purpose program-
BIAD, and BEAD registers are set to 0, the BTYPE register mable input/output flag pins. They are controlled by two
is set to 0 to specify program memory 24-bit words, and the memory-mapped registers. The PFTYPE register determines
BWCOUNT register is set to 32. This causes 32 words of on-chip the direction: 1 = output and 0 = input. The PFDATA register
program memory to be loaded from byte memory. These 32 words is used to read and write the values on the pins. Data being
are used to set up the BDMA to load in the remaining program read from a pin configured as an input is synchronized to the
code. The BCR bit is also set to 1, which causes program execu- SST-Melody-DAP’s clock. Bits that are programmed as outputs
tion to be held off until all 32 words are loaded into on-chip will read the value being output. The PF pins default to input
program memory. Execution then begins at Address 0. during reset.
The IDLE instruction can also be used to allow the processor to In addition to the programmable flags, the SST-Melody-DAP
hold off execution while booting continues through the BDMA has five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2
interface. For BDMA accesses while in Host mode, the addresses are dedicated output flags. FI and FO are available as an alternate
to boot memory must be constructed externally to the SST- configuration of SPORT1.
Melody-DAP. The only memory address bit provided by the
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
processor is A0.
configuration during reset.

–22– REV. 0
 SST-Melody-DAP
OUTLINE DIMENSIONS
Dimensions shown in millimeters

100-Lead Quad Flatpack [LQFP]

(ST-100)

16.00 BSC SQ
1.60 MAX
14.00 BSC SQ

0.75 12 100 76

1 75
0.60 TYP
0.45
SEATING
PLANE

TOP VIEW 12.00

(PINS DOWN) REF
0.20
0.15 0.09
0.05 7
3.5 VIEW A
0.08 0
MAX LEAD SEATING 25 51
COPLANARITY PLANE 26 50

0.27
VIEW A 0.50 BSC
0.22
ROTATED 90 CCW 0.17

COMPLIANT TO JEDEC STANDARDS MS-026BED

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION

REV. 0 –23–
–24–
PRINTED IN U.S.A. C03010–0–10/02(0)