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EE203Week5Report

digital electronics lab

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tannerlooney
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EE203Week5Report

digital electronics lab

Uploaded by

tannerlooney
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EE203-03

Laboratory Exercise 5

Verilog Tutorial

Tanner Looney
February 17, 2025
1. Introduction

This lab exercise introduces Verilog HDL. In this exercise we use Verilog in the Quartus

environment to build a circuit, then simulate and test the circuit for functionality and accuracy.

This exercise builds upon our previous experience with the Quartus software to now use Verilog

which is another method for building circuits.

Verilog HDL is a programming language used for modeling and designing digital circuitry.

HDL stands for Hardware description language. It enables engineers to quickly and effectively

model circuits at different levels of abstraction, build using sequential logic, and use control flow

constructs. These tools can massively improve the speed and effectiveness of circuit design.

2. Theory and Analysis

2.1. Theory

In this exercise we will implement a circuit described by the Quartus tutorial manual. The

code describes a circuit composed of two inputs, two AND gates, an OR gate and a single

output. The circuit is a Verilog implementation of a XOR gate. The figure below shows how

variables are declared to represent inputs and outputs. The output is then assigned via a logic

expression using AND gates (&) and OR gates (|). The expression in the code shows how the

inputs 𝑋! and 𝑋" are input in the circuit and complemented. The (~) is the complement or the

equivalent of passing the signal through a NOT gate. This is the equivalent circuit of the

XOR gate we built in week 2.


Figure 1: Verilog Code

Figure 2: Equivalent Circuit

Figure 3: XOR Gate Truth Table


2.2. Analysis

After the code has been written it must be compiled and tested. As seen in the terminal output

in Figure 1, the code was compiled successfully. Then it is ready to be run in the waveform

simulator for analysis. The waveform simulation is performed the same as in Week 2 lab report

where we build a clocked testing environment to implement the truth table variables to ensure

they match our XOR gate truth table. In Figure 4, we see the correct waveform output of the

XOR gate.

Figure 4: Waveform Output

3. Procedures

The procedures for this experiment were outlined in the lab manual and followed precisely with

no deviations. First a new project was created to the specifications of the DE-10 board. Then in

the text editor the code was written and compiled. After that, the waveform was simulated and

analyzed. Then pins were assigned and the board was blasted via USB.

4. Results

The image results show the proper implementation of the XOR gate to the DE-10 board via

Verilog code.
Figure 5: Inputs 0 0
Figure 6: Inputs 0 1
Figure 7: Inputs 0 1
Figure 8: Inputs 1 1
5. Discussion and Conclusion

5.1. Discussion

This experiment was to introduce the Verilog programming language and show how it

can effectively be used to model and design digital circuitry. The procedure was followed

precisely from the lab manual and there were no deviations. The code compiled successfully

and after simulation and analysis it was deemed functional and accurate. Then the DE-10

board was blasted with the program for further testing. The result was successful in

implementing a functional XOR gate.

5.2. Conclusion

This exercise was a very enlightening exposure to Verilog programming language. It

highlights its ease of use and allowed the student to gain more experience with the Quartus

software environment.
Appendices
Quartus II Lab Tutorial Manual

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