FPGA Vs ASIC Design Flow

The image compares the FPGA vs. ASIC Design Flow, highlighting key differences in their development processes.
Main Differences Observed:
.
1.Design Flow Complexity:
◦ASIC: Requires insertion of scan chains for testing, ASIC vendor-specific place & route, static timing
• . sign-off, and fabrication (which takes weeks).
analysis,
◦FPGA: Uses user mapping, place & route, and can be programmed instantly for prototyping.

2.Time to Market:
◦ASIC: Takes 8-16 weeks due to fabrication and testing.
◦FPGA: Available "off the shelf" and can be quickly deployed.

3.Cost & Flexibility:

◦ASIC: High NRE (Non-Recurring Engineering) costs, but low per-unit cost for mass production.
◦FPGA:No upfront NRE cost, but higher per-unit cost.

4.Modification & Debugging:

◦ASIC:Difficult to modify once fabricated; requires ECO (Engineering Change Order) and re-fabrication.
◦FPGA:Easily reprogrammable, allowing for instant debugging and updates.
Example to Illustrate the Difference:
• Suppose a company is developing a custom AI accelerator chip.

◦ If they use ASIC, they must ensure the design is perfect before fabrication,
as changes after production are costly and time-consuming.
◦ If they use FPGA, they can test and iterate the design quickly, modifying
parameters before finalizing the ASIC version.
• Conclusion:

• FPGA is best for rapid prototyping, debugging, and applications with evolving
requirements.
• ASIC is better for high-performance, power-efficient, mass-produced designs
but requires longer development time.
TYPES OF ASICS
MODULE - 3
• RTL SYNTHESIS FLOW

TRANSITION+OPTIMIZATION+MAPPING
 CPF File (Common Power Format) (.cpf Constraint File (.sdc - Synopsys Design Constraints)
•Purpose: Defines timing, clock, and area

.v for Verilog

.lib:
urpose: Contains standard TCF/SAIF/VCD Files(Toggle Count Format, Switching Activity
cell information, including Interchange Format, Value Change Dump) (.tcf, .saif, .vcd)
timing, power, and area data. (Optional)
•Purpose: Contains switching activity and power-related
information.

SDC Constraints (.sdc)

•Purpose: Ensures the design meets performance
requirements by defining constraints like clock frequencies,
Gate-Level Netlist Files (.vg, .vhdl)
setup/hold times, and input/output delays.
•Purpose: The output of the synthesis process,
representing the design in terms of standard cell gates.
technology dependent vs independent
• In logic synthesis, technology-independent and technology-dependent synthesis are two key phases:
• Technology-Independent Synthesis

• Focuses on transforming RTL (Register Transfer Level) code into an optimized Boolean representation.
• Uses generic logic functions such as AND, OR, XOR, and NOT, without considering specific gate implementations.
• Performs logic minimization techniques like:
◦ Boolean simplification
◦ State encoding optimization
◦ Retiming and logic restructuring
• Independent of any particular standard cell library or technology node.
• Example: Converting a high-level Verilog description into a simplified Boolean network.
Technology-Dependent Synthesis
• Maps the optimized Boolean representation onto a specific technology library (ASIC standard cells or FPGA LUTs).
• Considers physical constraints like:
◦ Delay and timing optimization
◦ Power and area constraints
◦ Technology-specific gate implementations (e.g., NAND vs. NOR dominance)
• Optimization techniques include:
◦ Gate sizing
◦ Buffer insertion
◦ Cell selection from the technology library
• Example: Mapping Boolean logic into a 45nm ASIC library using NAND and NOR gates.
• Both steps work together to ensure an efficient design that meets performance, power, and area constraints.
• Would you like me to expand on any specific part of this?
 Speculation
Optimization Explanation
1.Reduction of Critical Path Delay:
◦In the initial design, the delay includes MUX
selection followed by the adder operation.
◦In the optimized design, addition happens first,
allowing the MUX to simply select between
precomputed results, thereby removing the adder
from the critical path.
2.Parallel Computation:
◦Instead of sequentially processing MUX selection
and addition, the addition operations are computed
in parallel.
◦This takes advantage of the parallel execution
capability of FPGA Aor ASIC architectures, reducing
latency.
3.Improved Timing Performance:
◦Since the adder is removed from the critical path,
the circuit can operate at a higher clock frequency.
◦This benefits high-speed designs where minimizing
the delay is crucial.
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• QUESTION:

technology libraries can be separated in two broad

classes:
1. Logic library

2. Physical library
module mealy(input clk,reset,x, output reg z);
always @(state) begin
parameter A=4’h0, B=4’h1 .......; A: Z=1’b0;
reg[3:0] state, nextstate; b
c
always(@posedge clk or nedegdge st_n)begin d
if(!rst_n) e
state<= A; default: Z=1’b0;
else endcase
state <= nextstate; end
end

always@(state or x)begn
case(state)
A: nextstate = x ? 1: 0;

default: nextstate = A;
endcase
end
Wireload model
Wire load Models Types:

If a net crosses a hierarchical boundary, then different wire load models can be applied to different parts of the net and these wire
load modes are of three types:

Top
Enclosed
Segmented
In general, not all fanouts are mentioned in a
given WLM lookup table. For example, in
above WLM1 and WLM2 lookup table,
capacitance and resistance values for fanouts 1,
2, 3, 4, 5, 7, 8, 9, 10 is given. If we want to
estimate the values at fanouts in the gaps (e.g.
from 6) or outside the fanout range specified in
t h e t a b l e ( e . g Fa n o u t 2 0 ) , w e h a v e t o
calculated those value using (linear)
interpolation and extrapolation.
constraints create_clock -name clk -period 10 -waveform {0 5} [get_ports
"clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]

set_clock_uncertainty 0.01 [get_clocks "clk"]

# Input Delays
set_input_delay -max 1.0 [get_ports "reset_n"] -clock clk
set_input_delay -max 1.0 [get_ports "load"] -clock clk
set_input_delay -max 1.0 [get_ports "shift"] -clock clk
set_input_delay -max 1.0 [get_ports "rl_n"] -clock clk
set_input_delay -max 1.0 [get_ports "set_data[*]"] -clock clk

# Output Delays
set_output_delay -max 1.0 [get_ports "data_out"] -clock clk
set_output_delay -max 1.0 [get_ports "data_valid"] -clock clk
set_output_delay -max 1.0 [get_ports "eoc"] -clock clk
specify the clcokc constraints with a period of
40ns and with uneuqal on and off time(70% duty
cycle)