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TPS2552D, TPS2553D
SLVSDL7 – SEPTEMBER 2016

TPS255xD Precision Adjustable Current-Limited Power-Distribution Switches

1 Features 3 Description
•
1 Up to 1.5 A Maximum Load Current The TPS2552D and TPS2553D power-distribution
switches are intended for applications where
• ±6% Current-Limit Accuracy at 1.7 A (Typ) precision current limiting is required or heavy
• Meets USB Current-Limiting Requirements capacitive loads and short circuits are encountered
• Backwards Compatible with TPS2550/51 and provide up to 1.5 A of continuous load current.
• Adjustable Current Limit, 75 mA–1700 mA (Typ) These devices offer a programmable current-limit
threshold between 75 mA and 1.7 A (typ) via an
• Constant-Current (TPS2552D and TPS2553D) external resistor. Current-limit accuracy as tight as
• TPS2552D (Enable Low) and TPS2553D (Enable ±6% can be achieved at the higher current-limit
High) settings. The power-switch rise and fall times are
• Fast Overcurrent Response - 2 μs (Typ) controlled to minimize current surges during turn
on/off.
• 85-mΩ High-Side MOSFET (DBV Package)
• Reverse Input-Output Voltage Protection The TPS2552D/3D devices limit the output current to
a safe level by using a constant-current mode when
• Operating Range: 2.7 V to 6.5 V the output load exceeds the current-limit threshold.
• Built-in Soft-Start An internal reverse-voltage comparator disables the
• 15 kV ESD Protection per IEC 61000-4-2 (With power-switch when the output voltage is driven higher
External Capacitance) than the input to protect devices on the input side of
the switch. The FAULT output asserts low during
• UL Listed – File No. E169910 and NEMKO overcurrent and reverse-voltage conditions.
IEC60950-1-am1 ed2.0
• See the TI Switch Portfolio Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications TPS2552D SOT-23 (6) 2.90 mm × 1.60 mm
• USB Ports/Hubs TPS2553D SOT-23 (6) 2.90 mm × 1.60 mm
• Digital TV (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Set-Top Boxes
• VOIP Phones
Simplified Schematic
TPS2552D/53D
5V USB 0.1 mF USB Data USB
Input IN OUT Port
RFAULT
100 kW
120 mF
ILIM RILIM
Fault Signal FAULT
20 kW USB requirement only*
Control Signal EN GND
*USB requirement that downstream
Power Pad facing ports are bypassed with at least
120 mF per hub

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 10 Application and Implementation........................ 17
2 Applications ........................................................... 1 10.1 Application Information.......................................... 17
3 Description ............................................................. 1 10.2 Typical Applications .............................................. 17
4 Revision History..................................................... 2 11 Power Supply Recommendations ..................... 25
5 Device Comparison Table..................................... 3 11.1 Self-Powered and Bus-Powered Hubs ................. 25
11.2 Low-Power Bus-Powered and High-Power Bus-
6 Pin Configuration and Functions ......................... 4
Powered Functions .................................................. 25
7 Specifications......................................................... 5 11.3 Power Dissipation and Junction Temperature ...... 25
7.1 Absolute Maximum Ratings ...................................... 5
12 Layout................................................................... 26
7.2 ESD Ratings ............................................................ 5
12.1 Layout Guidelines ................................................. 26
7.3 Recommended Operating Conditions....................... 5
12.2 Layout Example .................................................... 26
7.4 Thermal Information .................................................. 6
13 Device and Documentation Support ................. 27
7.5 Electrical Characteristics........................................... 7
13.1 Device Support...................................................... 27
7.6 Typical Characteristics .............................................. 8
13.2 Related Links ........................................................ 27
8 Parameter Measurement Information ................ 11
13.3 Receiving Notification of Documentation Updates 27
9 Detailed Description ............................................ 13 13.4 Community Resources.......................................... 27
9.1 Overview ................................................................. 13 13.5 Trademarks ........................................................... 27
9.2 Functional Block Diagram ....................................... 13 13.6 Electrostatic Discharge Caution ............................ 27
9.3 Feature Description................................................. 13 13.7 Glossary ................................................................ 27
9.4 Device Functional Modes........................................ 14
14 Mechanical, Packaging, and Orderable
9.5 Programming........................................................... 15 Information ........................................................... 27

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

September 2016 * Initial Release

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5 Device Comparison Table

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6 Pin Configuration and Functions

TPS2552D/3D
DBV Package
Top View

IN 1 6 OUT
GND 2 5 ILIM
EN 3 4 FAULT

EN = Active Low for the TPS2552D

EN = Active High for the TPS2553D

Pin Functions
PIN
TPS2552D TPS2553D I/O DESCRIPTION
NAME
DBV DBV
EN 3 – I Enable input, logic low turns on power switch
EN – 3 I Enable input, logic high turns on power switch
GND 2 2 Ground connection; connect externally to PowerPAD
Input voltage; connect a 0.1 μF or greater ceramic
IN 1 1 I
capacitor from IN to GND as close to the IC as possible.
Active-low open-drain output, asserted during overcurrent,
FAULT 4 4 O
overtemperature, or reverse-voltage conditions.
OUT 6 6 O Power-switch output
External resistor used to set current-limit threshold;
ILIM 5 5 O
recommended 15 kΩ ≤ RILIM ≤ 232 kΩ.
Internally connected to GND; used to heat-sink the part to
PowerPAD
– – the circuit board traces. Connect PowerPAD to GND pin
™
externally.

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7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage range on IN, OUT, EN , ILIM, FAULT –0.3 7 V
Voltage range from IN to OUT –7 7 V
IO Continuous output current Internally Limited
Continuous total power dissipation See the Thermal Information
Continuous FAULT sink current 0 25 mA
ILIM source current 0 1 mA
TJ Maximum junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltages are referenced to GND unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
±500
V(ESD) Electrostatic discharge all pins (2) V
IEC 61000-4-2 contact discharge (3) ±8000
IEC 61000-4-2 air-gap discharge (3) ±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Surges per EN61000-4-2. 1999 applied to output terminals of EVM. These are passing test levels, not failure threshold.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage, IN 2.7 6.5 V
VEN TPS2552D 0 6.5
Enable voltage V
VEN TPS2553D 0 6.5
VEN Enable voltage 0 6.5 V
VIH High-level input voltage on EN 1.1
V
VIL Low-level input voltage on EN 0.66
Continuous output –40 °C ≤ TJ ≤ 125 °C 0 1.2
IOUT A
current, OUT –40 °C ≤ TJ ≤ 105 °C 0 1.5
RILIM Current-limit threshold resistor range (nominal 1%) from ILIM to GND 15 232 KΩ
IO Continuous FAULT sink current 0 10 mA
Input de-coupling capacitance, IN to GND 0.1 μF
Operating virtual IOUT ≤ 1.2 A –40 125
TJ junction °C
temperature (1) IOUT ≤ 1.5 A –40 105

(1) See "Dissipation Rating Table" and "Power Dissipation and Junction Temperature" sections for details on how to calculate maximum
junction temperature for specific applications and packages.

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7.4 Thermal Information

TPS2552D TPS2553D
THERMAL METRIC (1) DBV DBV UNIT
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 182.6 182.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 122.2 122.2 °C/W
RθJB Junction-to-board thermal resistance 29.4 29.4 °C/W
ψJT Junction-to-top characterization parameter 20.8 20.8 °C/W
ψJB Junction-to-board characterization parameter 28.9 28.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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7.5 Electrical Characteristics

over recommended operating conditions, VEN = VIN, RFAULT = 10 kΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
POWER SWITCH
DBV package, TJ = 25°C 85 95
DBV package, –40°C ≤TJ ≤125°C 135
rDS(on) Static drain-source on-state resistance DRV package, TJ = 25°C 100 115 mΩ
DRV package, –40°C ≤TJ ≤105°C 140
DRV package, –40°C ≤TJ ≤125°C 150
VIN = 6.5 V 1.1 1.5
tr Rise time, output
VIN = 2.5 V CL = 1 μF, RL = 100 Ω, 0.7 1
ms
VIN = 6.5 V (see Figure 20) 0.2 0.5
tf Fall time, output
VIN = 2.5 V 0.2 0.5
ENABLE INPUT EN OR EN
Enable pin turn on/off threshold 0.66 1.1 V
IEN Input current VEN = 0 V or 6.5 V, VEN = 0 V or 6.5 V –0.5 0.5 μA
ton Turnon time 3 ms
CL = 1 μF, RL = 100 Ω, (see Figure 20)
toff Turnoff time 3 ms
CURRENT LIMIT
RILIM = 15 kΩ –40°C ≤TJ ≤105°C 1610 1700 1800
TJ = 25°C 1215 1295 1375
RILIM = 20 kΩ
–40°C ≤TJ ≤125°C 1200 1295 1375
Current-limit threshold (Maximum DC output current IOUT delivered to
IOS TJ = 25°C 490 520 550 mA
load) and Short-circuit current, OUT connected to GND RILIM = 49.9 kΩ
–40°C ≤TJ ≤125°C 475 520 565
RILIM = 210 kΩ 110 130 150
ILIM shorted to IN 50 75 100
tIOS Response time to short circuit VIN = 5 V (see Figure 21) 2 μs
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point
95 135 190 mV
(VOUT – VIN)
Time from reverse-voltage condition to
VIN = 5 V 3 5 7 ms
MOSFET turn off
SUPPLY CURRENT
IIN_off Supply current, low-level output VIN = 6.5 V, No load on OUT, VEN = 0 V 0.1 1 μA
RILIM = 20 kΩ 120 150 μA
IIN_on Supply current, high-level output VIN = 6.5 V, No load on OUT
RILIM = 210 kΩ 100 130 μA
IREV Reverse leakage current VOUT = 6.5 V, VIN = 0 V TJ = 25 °C 0.01 1 μA
UNDERVOLTAGE LOCKOUT
UVLO Low-level input voltage, IN VIN rising 2.35 2.45 V
Hysteresis, IN TJ = 25 °C 25 mV
FAULT FLAG
VOL Output low voltage, FAULT I/FAULT = 1 mA 180 mV
Off-state leakage V/FAULT = 6.5 V 1 μA
FAULT assertion or de-assertion due to overcurrent condition 5 7.5 10 ms
FAULT deglitch
FAULT assertion or de-assertion due to reverse-voltage condition 2 4 6 ms
THERMAL SHUTDOWN
Thermal shutdown threshold 155 °C
Thermal shutdown threshold in
135 °C
current-limit
Hysteresis 10 °C

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.

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7.6 Typical Characteristics

TPS2552D
VIN 10 mF
VOUT
IN OUT
RFAULT
10 kW
150 mF
ILIM
Fault Signal FAULT RILIM
Control Signal EN GND

Power Pad

Figure 1. Typical Characteristics Reference Schematic Figure 2. Turnon Delay and Rise Time

Figure 3. Turnoff Delay and Fall Time Figure 4. Device Enabled into Short-Circuit

Figure 5. Full-Load to Short-Circuit Transient Response Figure 6. Short-Circuit to Full-Load Recovery Response

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Typical Characteristics (continued)

Figure 7. No-Load to Short-Circuit Transient Response Figure 8. Short-Circuit to No-Load Recovery Response

Figure 9. No Load to 1-Ω Transient Response Figure 10. 1-Ω to No Load Transient Response

Figure 12. Reverse-Voltage Protection Recovery

Figure 11. Reverse-Voltage Protection Response

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Typical Characteristics (continued)

2.40 0.40
RILIM = 20 kW
2.39 RILIM = 20 kW 0.36

IIN - Supply Current, Output Disabled - mA

2.38 0.32
UVLO - Undervoltage Lockout - V

2.37 0.28

2.36 UVLO Rising 0.24

2.35 0.20 VIN = 6.5 V

2.34 0.16
UVLO Falling
2.33 0.12

2.32 0.08
VIN = 2.5 V
2.31 0.04

2.30 0
-50 0 50 100 150 -50 0 50 100 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C

Figure 13. UVLO – Undervoltage Lockout – V Figure 14. IIN – Supply Current, Output Disabled – μA

150 20
RILIM = 20 kW VIN = 6.5 V VIN = 5 V,
135 VIN = 5 V 18
RILIM = 20 kW,
IIN - Supply Current, Output Enabled - mA

120 16 TA = 25°C

Current Limit Response - ms

105 14

90
12
75 VIN = 3.3 V
10
VIN = 2.5 V
60
8
45
6
30
4
15
2
0
-50 0 50 100 150 0
TJ - Junction Temperature - °C 0 1.5 3 4.5 6
Peak Current - A

Figure 15. IIN – Supply Current, Output Enabled – μA Figure 16. Current Limit Response – μs
150 1400
rDS(on) - Static Drain-Source On-State Resistance - mW

1300
1200
125 DRV Package
IDS - Static Drain-Source Current - mA

1100 TA = -40°C

1000
100 TA = 25°C
900
DBV Package 800 TA = 125°C

75 700
600
500
50
400
300
25
200 VIN = 6.5 V,
100 RILIM = 20 kW

0 0
-50 0 50 100 150 0 100 200 300 400 500 600 700 800 900 1000
TJ - Junction Temperature - °C VIN - VOUT - 100 mV/div

Figure 17. MOSFET rDS(on) Vs. Junction Temperature Figure 18. Switch Current Vs. Drain-Source Voltage
Across Switch

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Typical Characteristics (continued)

150
140
130

IDS - Static Drain-Source Current - mA

120
110 TA = -40°C TA = 25°C
TA = 125°C
100
90
80
70
60
50
40
30
20 VIN = 6.5 V,
RILIM = 200 kW
10
0
0 100 200 300 400 500 600 700 800 900 1000
VIN - VOUT - 100 mV/div

Figure 19. Switch Current Vs. Drain-Source Voltage Across Switch

8 Parameter Measurement Information

OUT
tr tf
RL CL
VOUT 90% 90%
10% 10%

TEST CIRCUIT

VEN 50% 50% VEN 50% 50%

toff
ton toff ton toff
90% 90%
VOUT VOUT
10% 10%

VOLTAGE WAVEFORMS

Figure 20. Test Circuit and Voltage Waveforms

IOS

IOUT

tIOS

Figure 21. Response Time to Short Circuit Waveform

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Parameter Measurement Information (continued)

Decreasing
Load Resistance

VOUT

Decreasing
Load Resistance

IOUT

IOS

Figure 22. Output Voltage Vs. Current-Limit Threshold

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9 Detailed Description

9.1 Overview
The TPS2552D and TPS2553D are current-limited, power-distribution switches using N-channel MOSFETs for
applications where short circuits or heavy capacitive loads will be encountered and provide up to 1.5 A of
continuous load current. These devices allow the user to program the current-limit threshold between 75 mA and
1.7 A (typ) via an external resistor. Additional device shutdown features include overtemperature protection and
reverse-voltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary
to drive the N-channel MOSFET. The charge pump supplies power to the driver circuit and provides the
necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input
voltages as low as 2.7 V and requires little supply current. The driver controls the gate voltage of the power
switch. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large
current and voltage surges and provides built-in soft-start functionality. There are two device families that handle
overcurrent situations differently. The TPS255xD family enters constant-current mode when the load exceeds the
current-limit threshold.

9.2 Functional Block Diagram

-
Reverse
Voltage
+ Comparator

IN CS OUT
Deglitch
Current
4-ms

Sense

Charge
Pump

Current
EN Driver
Limit

(Note A) FAULT
UVLO
GND
Thermal
Sense 8-ms Deglitch

ILIM
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A. TPS255x parts enter constant current mode during current limit condition

9.3 Feature Description

9.3.1 Overcurrent Conditions
The TPS2552D and TPS2553D respiond to overcurrent conditions by limiting their output current to the IOS levels
shown in Figure 23. When an overcurrent condition is detected, the device maintains a constant output current
and reduces the output voltage accordingly. Two possible overload conditions can occur.
The first condition is when a short circuit or partial short circuit is present when the device is powered-up or
enabled. The output voltage is held near zero potential with respect to ground and the TPS2552D and
TPS2553D ramps the output current to IOS. The TPS2552D and TPS2553D devices limits the current to IOS until
the overload condition is removed or the device begins to thermal cycle.
The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is
enabled and powered on. The device responds to the overcurrent condition within time tIOS (see Figure 21). The
current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit
MOSFET. The current-sense amplifier recovers and limits the output current to IOS. Similar to the previous case,
the TPS2552D and TPS2553D devices limit the current to IOS until the overload condition is removed or the
device begins to thermal cycle.
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Feature Description (continued)

The TPS2552D/53D thermal cycles if an overload condition is present long enough to activate thermal limiting in
any of the above cases. The device turns off when the junction temperature exceeds 135°C (typ) while in current
limit. The device remains off until the junction temperature cools 10°C (typ) and then restarts. The
TPS2552D/53D cycle on/off until the overload is removed (see Figure 6 and Figure 8) .

9.3.2 Reverse-Voltage Protection

The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typ) for 4-ms (typ).A reverse current of (VOUT – VIN)/rDS(on)) are present when this
occurs. This prevents damage to devices on the input side of the TPS2552D/53D by preventing significant
current from sinking into the input capacitance. The TPS2552D/53D devices allow the N-channel MOSFET to
turn on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The reverse-
voltage comparator also asserts the FAULT output (active-low) after 4-ms.

9.3.3 FAULT Response

The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage
condition. The TPS2552D/53D asserts the FAULT signal until the fault condition is removed and the device
resumes normal operation. The TPS2552D/53D are designed to eliminate false FAULT reporting by using an
internal delay "deglitch" circuit for overcurrent (7.5-ms typ) and reverse-voltage (4-ms typ) conditions without the
need for external circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as
starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving fault conditions.
Overtemperature conditions are not deglitched and assert the FAULT signal immediately.

9.3.4 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-
on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current
surges.

9.3.5 ENABLE
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the
supply current. The supply current is reduced to less than 1-μA when a logic high is present on EN or when a
logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver,A logic high
input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both TTL
and CMOS logic levels.

9.3.6 Thermal Sense

The TPS2552D/53D self-protection features use two independent thermal sensing circuits that monitor the
operating temperature of the power switch and disable operation if the temperature exceeds recommended
operating conditions. The TPS2552D/53D devices operate in constant-current mode during an overcurrent
conditions, which increases the voltage drop across power-switch. The power dissipation in the package is
proportional to the voltage drop across the power switch, which increases the junction temperature during an
overcurrent condition. The first thermal sensor turns off the power switch when the die temperature exceeds
135°C (min) and the part is in current limit. Hysteresis is built into the thermal sensor, and the switch turns on
after the device has cooled approximately 10°C.
The TPS2552D/3D also have a second ambient thermal sensor. The ambient thermal sensor turns off the power-
switch when the die temperature exceeds 155°C (min) regardless of whether the power switch is in current limit
and will turn on the power switch after the device has cooled approximately 10°C. The TPS2552D/53D families
continue to cycle off and on until the fault is removed.
The open-drain fault reporting output FAULT is asserted (active low) immediately during an overtemperature
shutdown condition.

9.4 Device Functional Modes

There are no other functional modes.

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9.5 Programming

9.5.1 Programming the Current-Limit Threshold

The overcurrent threshold is user programmable via an external resistor. The TPS2552D/53D use an internal
regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional to the
current sourced out of ILIM. The recommended 1% resistor range for RILIM is 15 kΩ ≤ RILIM ≤ 232 kΩ to ensure
stability of the internal regulation loop. Many applications require that the minimum current limit is above a certain
current level or that the maximum current limit is below a certain current level, so it is important to consider the
tolerance of the overcurrent threshold when selecting a value for RILIM. The following equations and Figure 23
can be used to calculate the resulting overcurrent threshold for a given external resistor value (RILIM). Figure 23
includes current-limit tolerance due to variations caused by temperature and process. However, the equations do
not account for tolerance due to external resistor variation, so it is important to account for this tolerance when
selecting RILIM. The traces routing the RILIM resistor to the TPS2552D/53D should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
RILIM can be selected to provide a current-limit threshold that occurs 1) above a minimum load current or 2)
below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current limit above a
minimum threshold is important to ensure start up into full load or heavy capacitive loads. The resulting maximum
current-limit threshold is the intersection of the selected value of RILIM and the IOS(max) curve.
To design below a maximum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(max) curve and choose a value of RILIM above this value. Programming the current limit below a
maximum threshold is important to avoid current limiting upstream power supplies causing the input voltage bus
to droop. The resulting minimum current-limit threshold is the intersection of the selected value of RILIM and the
IOS(min) curve.

Current-Limit Threshold Equations (IOS):

22980V
IOSmax (mA) =
RILIM0.94kW
23950V
IOSnom (mA) =
RILIM0.977kW
25230V
IOSmin (mA) =
RILIM1.016kW (1)
where 15 kΩ ≤ RILIM ≤ 232 kΩ.
While the maximum recommended value of RILIM is 232 kΩ, there is one additional configuration that allows for
a lower current-limit threshold. The ILIM pin may be connected directly to IN to provide a 75 mA (typ) current-limit
threshold. Additional low-ESR ceramic capacitance may be necessary from IN to GND in this configuration to
prevent unwanted noise from coupling into the sensitive ILIM circuitry.

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Programming (continued)

1800
1700
1600
1500
1400
Current Limit Threshold - mA

1300
1200
1100
1000
900
IOS(max)
800
700
600
500 IOS(nom)
400
300
200 IOS(min)
100
0
15 25 35 45 55 65 75 85 95 105 115 125 135 145 155 165 175 185 195 205 215 225 235
RILIM - Current Limit Resistor - kW

Figure 23. Current-Limit Threshold vs RILIM

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Constant-Current and Impact on Output Voltage

During normal operation the N-channel MOSFET is fully enhanced, and VOUT = VIN - (IOUT x rDS(on)). The voltage
drop across the MOSFET is relatively small compared to VIN, and VOUT ≉ VIN.
The TPS2552D/53D devices limit current to the programmed current-limit threshold set to RILIM by operating the
N-channel MOSFET in the linear mode. During current-limit operation, the N-channel MOSFET is no longer fully-
enhanced and the resistance of the device increases. This allows the device to effectively regulate the current to
the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across
the device is no longer negligible (VIN ≠ VOUT), and VOUT decreases. The amount that VOUT decreases is
proportional to the magnitude of the overload condition. The expected VOUT can be calculated by IOS × RLOAD,
where IOS is the current-limit threshold and RLOAD is the magnitude of the overload condition. For example, if IOS
is programmed to 1 A and a 1 Ω overload condition is applied, the resulting VOUT is 1 V.
The TPS2552D/53D devices assert the FAULT flag after the deglitch period and continue to regulate the current
to the current-limit threshold indefinitely. In practical circuits, the power dissipation in the package will increase
the die temperature above the overtemperature shutdown threshold (135°C min), and the device will turn off until
the die temperature decreases by the hysteresis of the thermal shutdown circuit (10°C typ). The device will turn
on and continue to thermal cycle until the overload condition is removed. The TPS2552D/53D devices resume
normal operation once the overload condition is removed.

10.2 Typical Applications

10.2.1 Two-Level Current-Limit Circuit
Some applications require different current-limit thresholds depending on external system conditions. Figure 24
shows an implementation for an externally controlled, two-level current-limit circuit. The current-limit threshold is
set by the total resistance from ILIM to GND (see the Programming the Current-Limit Threshold section). A logic-
level input enables/disables MOSFET Q1 and changes the current-limit threshold by modifying the total
resistance from ILIM to GND. Additional MOSFET/resistor combinations can be used in parallel to Q1/R2 to
increase the number of additional current-limit levels.

NOTE
ILIM should never be driven directly with an external signal.

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Typical Applications (continued)

Input 0.1 mF Output

IN OUT
RFAULT RLOAD
CLOAD
100 kW R1
210 kW
ILIM
Fault Signal FAULT R2
22.1 kW
Control Signal EN GND

Power Pad Q1 Current Limit

2N7002 Control Signal

Copyright © 2016, Texas Instruments Incorporated

Figure 24. Two-Level Current-Limit Circuit

10.2.1.1 Design Requirements

For this example, use the parameters shown in Table 1.

Table 1. Design Requirements

PARAMETER VALUE
Input voltage 5V
Output voltage 5V
Above a minimum current limit 1000 mA
Below a maximum current limit 500 mA

10.2.1.2 Detailed Design Procedures

10.2.1.2.1 Designing Above a Minimum Current Limit

Some applications require that current limiting cannot occur below a certain threshold. For this example, assume
that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the
IOS equations and Figure 23 to select RILIM.
IOSmin (mA) = 1000mA
25230V
IOSmin (mA) =
RILIM1.016 k W
1
æ 25230V ÷ö1.016
RILIM (k W ) = ççç ÷÷
çè I
OSmin mA ÷ø
RILIM (k W ) = 24k W (2)
Select the closest 1% resistor less than the calculated value: RILIM = 23.7 kΩ. This sets the minimum current-limit
threshold at 1 A . Use the IOS equations, Figure 23, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold.
RILIM (kW) = 23.7kW
22980V
IOSmax (mA) =
RILIM0.94kW
22980V
IOSmax (mA) =
23.70.94kW
IOSmax (mA) = 1172.4mA (3)
The resulting maximum current-limit threshold is 1172.4 mA with a 23.7 kΩ resistor.

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10.2.1.2.2 Designing Below a Maximum Current Limit

Some applications require that current limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 500 mA to protect an up-stream power supply. Use
the IOS equations and Figure 23 to select RILIM.
IOSmax (mA) = 500mA
22980V
IOSmax (mA) =
RILIM0.94kW
1
æ 22980V ÷ö0.94
RILIM (kW) = ççç ÷
çèIOSmax mA ÷÷ø
RILIM (kW) = 58.7kW (4)
Select the closest 1% resistor greater than the calculated value: RILIM = 59 kΩ. This sets the maximum current-
limit threshold at 500 mA . Use the IOS equations, Figure 23, and the previously calculated value for RILIM to
calculate the minimum resulting current-limit threshold.
RILIM (kW) = 59kW
25230V
IOSmin (mA) =
RILIM1.016kW
25230V
IOSmin (mA) =
591.016kW
IOSmin (mA) = 400.6mA (5)
The resulting minimum current-limit threshold is 400.6 mA with a 59 kΩ resistor.

10.2.1.2.3 Accounting for Resistor Tolerance

The previous sections described the selection of RILIM given certain application requirements and the importance
of understanding the current-limit threshold tolerance. The analysis focused only on the TPS2552D/53D
performance and assumed an exact resistor value. However, resistors sold in quantity are not exact and are
bounded by an upper and lower tolerance centered around a nominal resistance. The additional RILIM resistance
tolerance directly affects the current-limit threshold accuracy at a system level. The following table shows a
process that accounts for worst-case resistor tolerance assuming 1% resistor values. Step one follows the
selection process outlined in the application examples above. Step two determines the upper and lower
resistance bounds of the selected resistor. Step three uses the upper and lower resistor bounds in the IOS
equations to calculate the threshold limits. It is important to use tighter tolerance resistors, e.g. 0.5% or 0.1%,
when precision current limiting is desired.

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Table 2. Common RILIM Resistor Selections

DESIRED RESISTOR TOLERANCE ACTUAL LIMITS
IDEAL CLOSEST
NOMINAL
RESISTOR 1% RESISTOR IOS MIN IOS NOM IOS MAX
CURRENT LIMIT 1% LOW (kΩ) 1% HIGHT (kΩ)
(kΩ) (kΩ) (mA) (mA) (mA)
(mA)
75 SHORT ILIM to IN 50.0 75.0 100.0
120 226.1 226 223.7 228.3 101.3 120.0 142.1
200 134.0 133 131.7 134.3 173.7 201.5 233.9
300 88.5 88.7 87.8 89.6 262.1 299.4 342.3
400 65.9 66.5 65.8 67.2 351.2 396.7 448.7
500 52.5 52.3 51.8 52.8 448.3 501.6 562.4
600 43.5 43.2 42.8 43.6 544.3 604.6 673.1
700 37.2 37.4 37.0 37.8 630.2 696.0 770.8
800 32.4 32.4 32.1 32.7 729.1 800.8 882.1
900 28.7 28.7 28.4 29.0 824.7 901.5 988.7
1000 25.8 26.1 25.8 26.4 908.3 989.1 1081.0
1100 23.4 23.2 23.0 23.4 1023.7 1109.7 1207.5
1200 21.4 21.5 21.3 21.7 1106.0 1195.4 1297.1
1300 19.7 19.6 19.4 19.8 1215.1 1308.5 1414.9
1400 18.3 18.2 18.0 18.4 1310.1 1406.7 1517.0
1500 17.0 16.9 16.7 17.1 1412.5 1512.4 1626.4
1600 16.0 15.8 15.6 16.0 1512.5 1615.2 1732.7
1700 15.0 15.0 14.9 15.2 1594.5 1699.3 1819.4

10.2.1.2.4 Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, a 0.1μF or greater ceramic bypass capacitor between
IN and GND is recommended as close to the device as possible for local noise de-coupling. This precaution
reduces ringing on the input due to power-supply transients. Additional input capacitance may be needed on the
input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy
transient conditions. This is especially important during bench testing when long, inductive cables are used to
connect the evaluation board to the bench power-supply.
Placing a high-value electrolytic capacitor on the output pin is recommended when large transient currents are
expected on the output.

10.2.1.3 Application Curves

Figure 25. Turn on Delay and Rise Time Figure 26. Reverse-Voltage Protection Recovery

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10.2.2 Auto-Retry Functionality

Some applications require that an overcurrent condition disables the part momentarily during a fault condition
and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and
capacitor. During a fault condition, FAULT pulls low disabling the part. The part is disabled when EN is pulled
low, and FAULT goes high impedance allowing CRETRY to begin charging. The part re-enables when the voltage
on EN reaches the turnon threshold, and the auto-retry time is determined by the resistor/capacitor time
constant. The device continues to cycle in this manner until the fault condition is removed.

0.1 mF TPS2553D
Input Output
IN OUT
RFAULT RLOAD
100 kW CLOAD

ILIM
FAULT RILIM
20 kW
EN GND
CRETRY
0.1 mF Power Pad

Figure 27. Auto-Retry Functionality

Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.
Figure 28 shows how an external logic signal can drive EN through RFAULT and maintain auto-retry functionality.
The resistor/capacitor time constant determines the auto-retry time-out period.
TPS2553D
Input 0.1 mF
Output
IN OUT
RLOAD
CLOAD

External Logic ILIM

RFAULT RILIM
Signal & Driver FAULT
100 kW 20 kW
EN GND
CRETRY
0.1 mF Power Pad

Figure 28. Auto-Retry Functionality With External EN Signal

10.2.2.1 Design Requirements

For this example, use the parameters shown in Table 3.

Table 3. Design Requirements

PARAMETER VALUE
Input voltage 5V
Output voltage 5V
Current 1200 mA

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10.2.2.2 Detailed Design Procedure

Refer to Programming the Current-Limit Threshold section for the current limit setting. For auto-retry functionality,
once FAULT asserted, EN pull low, TPS2553D is disabled, FAULT des-asserted, CRETRY is slowly charged to EN
logic high via RFAULT, then enable, after deglitch time, FAULT asserted again. In the event of an over-load,
TPS2553D cycles and has output average current. ON-time with output current is decided by FAULT deglitch
time. OFF-time without output current is decided by RFAULT x CRETRY constant time to EN logic high and ton time.
Therefore, set the RFAULT × CRETRY to get the desired output average current during overload.

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10.2.3 Typical Application as USB Power Switch

TPS2552D/53D
5V USB 0.1 mF USB Data USB
Input IN OUT Port
RFAULT
100 kW
120 mF
ILIM RILIM
Fault Signal FAULT
20 kW USB requirement only*
Control Signal EN GND
*USB requirement that downstream
Power Pad facing ports are bypassed with at least
120 mF per hub

Figure 29. Typical Application as USB Power Switch

10.2.3.1 Design Requirements

For this example, use the parameters shown in Table 4.

Table 4. Design Requirements

PARAMETER VALUE
Input voltage 5V
Output voltage 5V
Current 1200 mA

10.2.3.1.1 USB Power-Distribution Requirements

USB can be implemented in several ways regardless of the type of USB device being developed. Several power-
distribution features must be implemented.
• SPHs must:
– Current limit downstream ports
– Report overcurrent conditions
• BPHs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 μF)
• Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS2552D/53D meets each of these requirements. The integrated current limiting and
overcurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the
need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.

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10.2.3.2 Detailed Design Procedure

10.2.3.2.1 Universal Serial Bus (USB) Power-Distribution Requirements

One application for this device is for current limiting in universal serial bus (USB) applications. The original USB
interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC
peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the
USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is
conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,
and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply. The USB specification classifies two different classes of
devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as
defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. The latest USB standard should always be referenced when considering the current-
limit threshold
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or receive data or control information over the bus. A USB
function can be embedded in a USB hub. A USB function can be one of three types included in the list below.
• Low-power, bus-powered function
• High-power, bus-powered function
• Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS2552D/53D have higher current
capabilities than required for a single USB port allowing it to power multiple downstream ports.

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11 Power Supply Recommendations

11.1 Self-Powered and Bus-Powered Hubs

A SPH has a local power supply that powers embedded functions and downstream ports. This power supply
must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions.
SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller.
Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with
less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller
of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the
embedded function may need to be kept off until enumeration is completed. This is accomplished by removing
power or by shutting off the clock to the embedded function. Power switching the embedded function is not
necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current
drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the
downstream ports, and it is limited to 500 mA from an upstream port.

11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting.

11.3 Power Dissipation and Junction Temperature

The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated using Equation 6.
PD = rDS(on) × IOUT 2
where
• PD = Total power dissipation (W)
• rDS(on) = Power switch on-resistance (Ω)
• IOUT = Maximum current-limit threshold (A)
• This step calculates the total power dissipation of the N-channel MOSFET. (6)
Finally, calculate the junction temperature:
TJ = PD × θJA + TA
where
• TA = Ambient temperature (°C)
• θJA = Thermal resistance (°C/W)
• PD = Total power dissipation (W) (7)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance θJA, and thermal resistance is highly dependent on the individual package and board
layout. The Thermal Information Table provides example thermal resistances for specific packages and board
layouts.

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12 Layout

12.1 Layout Guidelines

• TI recommends placing the 100-nF bypass capacitor near the IN and GND pins, and make the connections
using a low-inductance trace.
• TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin is
recommended when large transient currents are expected on the output.
• The traces routing the RILIM resistor to the device should be as short as possible to reduce parasitic effects
on the current limit accuracy.
• The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.

12.2 Layout Example

/FAULT

IN 1 6 OUT

2 5 ILIM

EN 3 4

Figure 30. Layout Recommendation

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13 Device and Documentation Support

13.1 Device Support

For the TI Switch Portfolio, go here.

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 5. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS2552D Click here Click here Click here Click here Click here
TPS2553D Click here Click here Click here Click here Click here

13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

13.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPS2552DDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15IL
TPS2552DDBVR.Z Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15IL
TPS2552DDBVT Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15IL
TPS2552DDBVT.Z Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15IL
TPS2553DDBVR Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15JL
TPS2553DDBVR.Z Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15JL
TPS2553DDBVRG4.Z Active Production SOT-23 (DBV) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15JL
TPS2553DDBVT Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15JL
TPS2553DDBVT.Z Active Production SOT-23 (DBV) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 15JL

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-May-2025

and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2552DDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS2552DDBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS2553DDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS2553DDBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2552DDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
TPS2552DDBVT SOT-23 DBV 6 250 210.0 185.0 35.0
TPS2553DDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
TPS2553DDBVT SOT-23 DBV 6 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

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 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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