<br>

4 8051 Interfacing

Syllabus:
LED, LCD, SevenSegment display.
4.1 /OInterfacing: Keyboard, Relays.
80O51 Simple programs for ADCintertacing.
2ntertacing ADC 0808/09 with
programs for DAC intertacing.
Intertacing DAC 0808/09 with 8051, Simple
.3
4.4 Memory Interfacing: Program and Data Memory.

As long as no keys are pressed, the microcontralle.

4.1 I/O Interfacing checks logic high on each of the pins connected
to

rows.
While designing the 8051 microcontroller based the keyboard
system, we have to expand the I/0 ports as Port 0 The nibble driven onto the columns always contains
and Port 2 are used to interface external memory. only a single 0.
any row pin is
The I/0 devices such as LED, relays, keyboard, LCD, The microcontroller can find a 0 on
Seven Segment Display, stepper motor can be for the keyboard keys to be pressed that connects
a row.
interfaced using port pins of 8051 Microcontroller. the column set to 0 to
The controller knows which column is ata 0 level and
4.1.1 4 x 4 Matrix Keyboard which row reads 0, which determine which kev
is

Draw interfacing diagram of 4x4 keyboard matrix with pressed.

W-19, S-22, 2 Marks
8051 microcontroller 4.1.1(A) Interfacing of 4 x 4 Matrix Keyboard
Usually, the keyboard is used as a primary input As shown in ig. 4.1.2, P3.0 to P3.3 pins are
device with embedded microcontrollers. connected column and P3.4 to P3.7 are connected to
C2 C3 C4
rows of 4 x 4 matrix keyboard and eight LED's are
3
connected to P2.0 to P2.7.
R1
6

R2
7 8 9

R3
E D

R4

Fig. 4.1.1: 4 x 4
Matrix Keyboard RÀ

Pa
The keyboard consists of a number of keys i.e.
Switches, connected in a matrix form i.e. row and
column arrangement as shown in Fig. 4.1.1.
a
In order to scan the keyboard, microcontroller makes
one of the columns low and then reads the rows to see
if any keys in that column have been pressed.
The rows are pulled up by resistance in the 8051ports.
Fig.4.1.2: Interfacing of 4 x 4 matrix
keyboard with 8051 microcontroller
<br>

Microcontroller and Applications

4-2 8051 Interfacing
Algorithm
A11(B) Scan column 3, if column 3 is low then 'A' key is
Asyou can see no pin is connected to ground, over pressed.
e Scan column 4, if column 4 is low then 'B' key is
the controller pin itself provides the ground.
We pull one
of
the column Pins low and check the pressed.
ow Dins if any of the Pin is low which indicates Key Clear row 4, set other 3
Scan column 1, if column 1 is low then 'C key is
is pressed.
we
made column 1
pressed.
Suppose pin low and while
Scan column 2, if column 2 is low then 'D' key is
checking the rows we got Row 3 is low then it
pressed.
indicates switch 7 has been pressed.
Scan column 3, if column 3 is low then E'key is
Now we will see how the keyboard is scanned. The
pressed.
steps are: Scan column 4, if column 4 is low then F' key is
Scan row 1
pressed,
Scan row 2
Scan row 3 4.1.1 (C) Flowchart
Scan row 4 Start

Scanning a row is done by applying 0 V to the port Ground all rowS

pin for that row and 5 V to the other three rows,

then scanning each individual column to check if
one of them is LOW. Read all rows

If it is,then the key at the junction between the current No All keyS
row and column being scanned is the pressed key. open?
Yes
Start.
Make All Pins High
Read all columns
Clear row 1, set other 3
Scan column 1, if column 1 is low then 0' key is No All
keys
pressed. open?
Scan column 2, if column 2 is low then (1' key is Yes
pressed. Wait for debounoe
Scan column 3, if column 3 is low then 2' key is
Bead all columns
pressed.
Scan column 4, if column 4 is low then '3' key is NC
Any keys
pressed. down?
Yes
Clear row 2, set other 3
Scan column 1, if column 1
is low then '4' key is
pressed. Ground next row
Scan column 2, if column 2 is low then '5 key is
Read all colunns
pressed.
Scan column 3, if column 3 is low then '6 key is No Key press
pressed. in this row?
Scan column 4, if column 4 is low then '7' key is Yes
pressed. Find which key is pressed

Clear row 3, set other 3 Get code from lookup table

Scan column 1, if column 1 is low then '8 key is
pressed. End
Scan column 2, if column 2 is low then '9' key is
Flowchart 1
pressed.
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8051 Interfacing
Microcontroller and Applications 4-3
4.1.1 (D) Program CLR PRESSED ;reset the flag
JB COL1, NEXTCOL
check if first key is pressed
KEYPORT EQU P3
4x4 keyboard port
JNB COL1,$ ;if yes then wait for
connected to port 3
;key release
LEDPORT EQU P2
; LED connected to PORT 2
COL1 EQU P3.0 SETB PRESSED
; set the flag
1
column
COL2 EQU P3.1
column 2
;

RET
COL3 EQU P3.2 read col2
column 3 NEXTCOL:
COL4 EQU P3.3
column 4 JB COL2, NEXTCOL1
;
checkifsecond key is
KEYVALEQU 30H
to store key number ;pressed
PRESSED BIT OH
flag
JNB COL2,$ ;if yesthen wait for key
KEY_INIT:
MOV KEYPORT,#0FH ;release
make rows as
;

0/P and
; column as I/P INC KEYVAL ;its key number 2
RET ;
SETBPRESSED set the flag
GET KEY:

RET
MOV KEYVAL,#0
;reset the number
MOV KEYPORT,#7FH NEXTCOL1: ; read col3
;make row1 low
ACALL READ_COL read columns JB COL3, NEXTCOL2 ;check if third key is pressed
JB PRESSED, DONE ;check if flag is set
JNBCOL3,$ ;if yes then wait for key release
MOV KEYVAL,#4 ;if not then read next row INC KEYVAL ;its key3
MOV KEYPORT,#OBFH ;make row2 low
INC KEYVAL
ACALL READ_COL ;read columns
JB PRESSED,DONE ;check if flag is set
SETB PRESSED :set the flag
MOV KEYVAL,#8 RET
if not then read nextrow
MOV KEYPORT,#ODFH NEXTCOL2: ;read column 4
;make row3 low
ACALL READ_COL JB COL4, EXIT ;check if fourth key
;read columns pressed
JB PRESSED,DONE check if flag is set JNB COL4,S ;ifyes then wait for key release
MOV KEYVAL,#12 ;ifnot read row4 INC KEYVAL its key 4
MOV KEYPORT,#OEFH ;make row4 low INC KEYVAL
ACALL READ_COL ;
read columns
INC KEYVAL
JB PRESSED, DONE ;check if flag is set
SETB PRESSED ; set the flag
DONE:
RET
MOV A, KEYVAL ;display keys pressed
EXIT:
if nokey is pressed
on LED CLR PRESSED
;clrthe flag
MOV LEDPORT, A
CLR KEYVAL
reset the number
RET
RET
READ_COL: read columns routine
END

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<br>

Microcontroller:and Applications 4 -4 8051 Interfacing

of 4 x
41.4(E)
Interfacing 4 Matrix Keyboard
The only way the microcontroller can find a 0 on
with 8051 Microcontroller any row pin is for the keypad button to be pressed

interfacing diagram showing 4 x 4 matrix that connects the column set to 0 to a row.
. Draw

vovboard connections to Port 2 and Port 1 of 8051 The controller knows which column is at a 0-level
mícrocontroller. Draw fiowchart to detect
a
pressed and which row reads 0, allowing it to determine
key. W-15, 6 Marks
which key is pressed.

Kevpads are often used as a primary input device For the keypad, the pins from left to right are: R1,
for embedded microcontrollers. R2, R3, R4, C1,C2, C3, C4.

The keypads actually consist of a number of C3 C4

C2
switches, connected in a matrix i.e. row and column
2
arrangement as shown in Fig, 4.1.3.
R1
In order for the microcontroller to scan the keypad,
itoutputs a nibble to force one (only one) of the R2
columns low and then reads the rows to see if any
buttons in that column have been pressed. R3

The rows are pulled up by the internal weak pull

R4
ups in the 8051 ports.

Consequently, as long as no buttons are pressed, the Fig. 4.1.3 :

4 x 4
Matrix Keyboard Connection

microcontroller see logic high on each of the pins

As shown in Fig. 4.1.4, P1.0 to P1.3 pins are
attached tothe keypad rows.
connected column and P2.0 to P2.3 are connected to
The nibble driven onto the columns always contains rows of 4 x 4 matrix keyboard.
a 0.
only single

45V

Vee

P1.3
P1.2
P11
P1.0
C3

R'
8051 P2.3
R
R2
92.2
R2
R3
TAL: P2.1
R2
R4
HO
P2.0
C2 R4
TAL2

Fig. 4.1.4:Interfacing of 4 x 4 matrix keyboard with 805l microcontroller

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8051 Interfacing
Microcontroller and Applications 4-5

4.1.2 Interfacing of Relays with 8051 Port

Start
or electromechanical
Ground all rows relay is an electrical OFF
A switch
which perform
ON and operations without any
human interaction.
It is therefore connected to output pins of th
Read all rows
microcontroller and used to turn on/off high-power
No All keys devices such as motors, transformers, heaters,
open? bulbs, antenna systems etc.
Yes power to turn ON, but it
Thus, a relay takes small
can control high power devices to switch ON ana
Read all columns OFF.
Relay not directly interfaced to 8051
is
No
microcontroller, because a relay uses 7OmA current
Allkeys

open?
Yes or some relays may operates with 50mA current to
Wait for debounce excite the inductor coil.
But the current sinking capability of each port pin of
Read all columns
8051 is 20mA.
No
Any keys So whenever 70mA current flow through the nort
down?
Yes pin may harm that particular port pin.
So, large current sinker is required to avoid this
problem.
Ground next row
Hence, to drive the relay with 8051 microcontroller.
Read all columns ULN2003/ULN2803 driver can be used.

No
A
driver has 500mA current sinking capacity
ULN
Key pre ss
in this row? for each output pin, hence 8051 microcontroller is
Yes interfaced with relay via ULN driver which will not
Find which key is pressed damage the microcontroller port pin.
Fig. 4.1.5 shows the interfacing relay with 8051
Get code from lookup tabie
microcontroller to make bulb ON or OFF.
End IN1 pin of ULN2803 is connected to Port 2 pin i.e.
Flowchart 2 P2.0of 8051 microcontroller.
+5V +5V
(Bub

C1

XTAL1 1
| in Out 1
P20
Cystal XTAL2 in 2 out 2
+12 V
33p in 3 out 3
R1 in 4
RST 8051 out 4
8k2 C3 in 5 |out 5
ULN2803
T10u EA in 6
out 6
in 7 Out 7
in 8
Out 8
GND
COM

+5V
Fig. 4.1.5: Interfacing of Relay with 8051

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Microcontroller.and Applications
4-6 8051 Interfacing
Program
4.1.3 Interfacing of LED (Light Emitting
NEXT:
Diode) with 8051
SETB P2.0 ;Make Relay ON

MOV R5, #OFFH LED is a semiconductor device used in various

electronic devices, for signal transmission
ACALL Delay Wait forsome time /power
indication purposes.
CLR P2.0 :Make Relay OFF
It is very cheap in price and easily obtainable in a
MOV
R5, #OFFH
variety of shape, color, and size.
ACALL Delay Wait for some time
The set of LEDs are also used for design message
SJMP NEXT
display boards and traffic control signal lights etc.
Delay:
LED has two pins i.e. positive (anode) and negative
MOV R4, #64H
UP:
(Cathode) as shown in the Fig. 4.1.6.
UPT: MOV R3, #0FDH

UP2: DJNZ R3, UP2

DJNZ R4, UP1

Cathode
DJNZ R5, UP
Anode

RET Fig. 4.1.6: LED diagram

After the execution of above program, the bulb
The symbol of LED is shown in Fig. 4.1.7.
connected to ULN2803 will be made ON and OFF
Cathode
continuously. Refer Fig, 4.1.5
Program
Anode
ORG OH
Fig. 4.1.7: Symbol of LED
MAIN

SETB PI.0 Mostly used LEDs have voltage drop of 1.7v and
MOVR5 #55 current of 10mA to glow at full intensity.
ACALL DELAY
LED can be connected to any port pin of 8051.
CLRP1.0 LED is
A
connected to P1.0 of 8051, as shown in
MOV R5, #55
Fig. 4.1.8.
ACALL DELAY

SIMP MAIN
XTAL1
DELAY:
Cystal XTAL2
MOV R4, #100
H2
MOV R3, #253
RST
DJNZ R3, H3 8051
EA
DJNZ R4, H2

DINZ R5, H1

P10
RET

END
Fig. 4.1.8 : LED Connected to 8051

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Microcontroller and Applications 8051 Interfacing

4-7
Program interface the 4 Keye s
Fig, 4.1.10 shows how to
NEXT:
4 LED's to microcontroller 8051Ports.
MOV A, #01H
MOV P1, A ;Make LED ON When any key is pressed then key number will be
ACALL Delay displayed on corresponding LED.
Wait for some time
MOV A, #00H we will get the
So, after pressing key, code as given
MOV P1, A
;Make LED OFF
in Table 4.1.1.
ACALL Delay
;Wait forsome time Table 4.1.1 : Key Codes
SJMP NEXT

Key PO.7PO.6 P0.5 P0.4PO.3 PO.2 PO.1 PO.0 Hey

4.1.4 Interfacing of 8 LEDS with 8051 Ports 1 1 1 1 1
S1 1 FEH
Q. Draw the interfacing diagram of 8 LED 1 1 1
to pot 2 of S2 1 1 1 FDH
8051 microcontroler. Write an
assembly language S3 1 1 1 1 1 0 1 1 FBH
program to make LED ON
and OFF after certain
delay. S4 1 1 1 1 1 1 1 F7H
W-15, WN:17, 6 Marks
Sketch 8051 microcontroller interfacing
diagram to The LED codes are given in the Table 4.1.2.
interface 4 LEDs and 4 switches. Interface LEDs
to Table 4.1.2 : LED Codes
Port 0 upper nibble and switch to Port 1. Write an
ALP
for 8051 to read status of switches and operate Key P2.7 P2.6 P2.5| P2.4 P2.3|P2.2P2.1 P2.0 Hex
LEDs
as per switch status S-16, S-18, 6 Marks LEDO 1
0 10H
The complete interfacing of Eight LEDs to 8051 LED 1
using Port 2 is shown in Fig. 4.1.9.
0 0 020H
LED2 1
0 0 40H
Alleight LEDs are connected Port 2.
LED3 1 0 0
80H

AL $2

Crystal XTALE
P20 XTALI
8051 P21
RÍ P22
RST 13.0882
P2
P2.
MaTL3
E P2
R2.6 LEDS

LEDZ

:
Fig. 4.1.9 Interfacing of Eight LEDs with Port 2 of 8051
Progranm
UP: MOV A, #00H Load A with 00 to make LED OFF

MOV P2, A Smake LED OFF

ACALL Delay Wait for some time
Fig. 4.1.10
MOV A, #0FFH Load A with FFH to make NEXT: MOV A
P1 ; Read
;
KEY Status
LED ON
CINE A, #OFEH,
DN1
MOV P2, A make LED ON

MOV A, #10H
ACALL Delay ;Wait for some time
MOV P2,A
;Make LEDO ON
SJMP UP
ACALL Delay
:Wait for 20 ms

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Microcontroller and Applications

4-8
8051 Interfacing
SJMP NEXT
The pin out scheme and
CINE A, #OFDH, DN2
plcture of a typlcal 7
DNI: segment LED display is shown
in Fig. 4.1.11.
MOV A, #20H gf com a b

MOVP2, A
Make LED1 ON

ACALL Delay Wait for 20 ms

SJMP NEXT

DN2: CJNE A, #OFBH,DN3

MOV A, #40H
MOV P2,A Make LED2 ON"
d
comC dot
ACALL Delay Wait for 20 ms
Fig. 4.1.11 : Seven Segment LED
SJMP NEXT
The common digit patterns of a seven segment
CJNE A, #OF7H, DN4
DN3
display are shown in the Table 4.1.3.
MOV A, #80H Table 4.1.3: Code for Digit
MOV P2, A Make LED3 ON
Pins of Seven Segment Display Hex
ACALL Delay Wait for 20 ms |Digit
dp e C b Code
DN4: SJMP NEXT
0 1 1
CO
4.1.5 Seven Segment Display 1 1 1 1 1 1 1 P9
Now we will see how to interface a seven segment 2 1 1 1
0 A4
LED display to an 8051 microcontroller using 8255.
3 1 1 1
BO
Seven segment LED display mostly used in many
industrial applications and can display digits from 0 4 1 1 1 0 1 99
to 9 and few characters like A, B, C, D etc. 5 1
1 1
92
A seven segment display consists of seven LEDs
6 1 1
0 82
organized in the form of a squarish '8 inclined to
the right and a single LED as the dot character. 7 1 1 1 1 1
0 F8
Different characters can be displayed by making ON 8 1
80
the required LED segments.
9 1
0 1
0 0 90
Seven segment displays are of twO types, common
cathode and common anode. 4.1.5(A) Interfacing Seven Segment Display
In common cathode type, the cathode of all LEDs to 8051
are connected together to a single terminal which is
Draw the interfacing diagram of seven segment display
usually labeled as 'COM and the anode of all LEDS
are left open as individual pins labeled as a, b, c, d, e, to8051 microcontroller. W-14, W-15,6 Marks

f,g&hor dot. The circuit diagram shown Fig. 4.1.12 is of an

In common anode type, the anodes of all LEDs are 8051 microcontroller based 0 to 9 counter which
connected together to the single terminal and has a 7 segment LED display interfaced to it in order
cathodes are left open as individual pins. to display the count.

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Microcontroller and Applications 8051 Interfacing

4-9
R3 Table P.2 :Code for Character 'g'
P2.0W Common cathode seven
C1 R4

33p XTAL1
P212w segment LED display
Status of Pins of Seven Segment Display Hex
R5
ystal C2
H XTAL2
P22W R6
Digit
for 'g
Code
8051 P234
R1
dp e C b
RST
Bk2 RT
P2.4Pw
10ur EA
R8 1 0 1
90
P2.5Dww h
Com
R9 Assume the Digit code for 'g is stored in internal
P26w
R10 RAM location 40H.
P27ww
MOV R2, #40HMemory pointer to point
Fig. 4.1.12 : Interfacing
of Seven g
code
Segment LED to Port 2 of 8051
The common cathode seven segment NEXT: MOV A, @R2 ; Load A reg. with digit
display is
connected to the Port 2 of the microcontroller 8051 code of 'g
and R3 to R10are current limiting resistors.
Assume the Digit code are stored in internal Ram
MOV P2, A Send to Port 2 of 8051

from 40H onward, So we will initialize memory ACALL Delay Wait for 1
Sec
pointer using R2 register to read digit code.
SJMP NEXT Send continuously
Program 1:
NEXT: MOV R1, #0AH; Counter to display digit 4.1.5(B) Interfacing Multiplexed 7 Segment
MOV R2, Display with 8051 (4 Digit)
#40H: Memory pointer

UP MOV A, @R2 ; Load A

with digit code A7 segment display has total of 10 pins and these 7
segments may be common anode or common
MOV P2, A Send to Port 2 of 8051
cathode.
ACALL Delay Wait for 1
Sec The middle two pins out of the ten pins i.e. pin
INC R2
Incrernent memory pointer number 3 and pin number 8 are the common
cathode or the common anode and is internally
DNZ R1, UP
short.
SJMP NEXT
While interfacing the multiple 7 segment
displays
After the execution of the above program, the digit 0 with 8051 microcontroller, lot of pins are
required
to 9 will be displayed on the seven segment LED and hence to reduce the number
of pins we
display continuously which will work as up counter. multiplex the seven segments.
For down counter, initialize memory pointer i.e. Here the number of pins required
will be 8 pins for
load R2 with 49H and replace INC R2 with DEC R2 sending the data and 1 pin each to
select seven
instruction. segment displays.
So whiie interfacing seven segments, we
Program 2 : Write an assembly language program to 4 need
8+4= 12 pins of 8051 micro controller.
display g on seven segment display. W-14, 4 Marks
The connections for interfacing a
Soln. : muitiplexed seven
segment system display
with 8051 is
The seven segment display code for common
a Connect the common cathode or
cathode seven segment display is given in the common
Table P.2. anode pins of the 7 segment
with a npn or pnp
transistor respectively.

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Microcontroller and Applications

4-10 8051 Interfacing
Connect each of
the data pins with their Similarly Enable DISP2 and put
respective data pins of each seven data of digít 2 and so
segment i.e. on for DISP3 and DISP4.
a to a,
b to b, so on and finally connect these
data pins with the microcontroller.
We first need to select and
C. switch on the seven
segments via the transistor to send
data to the DISP1

seven segments and

then we need to switch off
the transistor and switch on the next
transistor
and again send the data. C

In multiplexing all seven segment displays are

connected in parallel to one port and only one
display should turn ON at a time, for a short amount DISPS

of time.
Thus this cycle must be repeated to achieve a
fast
rate and due to the persistence of vision of human
eye, all digits seems to glow. DISP4

The main advantages of multiplexingdisplay are:

a. Less number of port pins are required.

A1-R8

b. Power consumption is less.

C. Maximum 24 number of display units can be
interfaced.
The interfacing of four 7 segment display with 8051
microcontroller is shown in Fig. 4.1.13.
The data pins with their respective data pins of each
seven segment ie. a-a, b-b, ..g-g, h-h are
connected to Port 0
the 8051 microcontroller Fig. 4.1.13 : Interfacing of multiplexed
7 segment display with 8051
commonly.

Transistor Q1 drives the first display (DISP1), 4.1.6 LCD (Liquid Crystal Display)
transistor Q2 drives the second display (DISP2),
Transistor Q3 drives the third display (DISP3) and 4.1.6(A) Basics of LCD
transistor Q4 drives the fourth display (DISP4). x 2
Draw interfacing of
16 LCD with 8051 and state
R9 to R12 are the base current limiting resistors of the function of EN and RS pin of
LCD. W-19, 4 Marks
Q1 to Q4.
The LCD Display can be simply connected with an
Suppose we want to display 1 on DISP1, '2' on 8051 microcontroller and can be used in digital
DISP2,'3' on DISP3 and '4' on DISP4. device like digital voltmeter / ammeter, digital
So according to concept of multiplexing we must put clock, home automation displays, status indicator
data corresponding to digit 1, when only DISP1 is display, digital code locks, digital speedometer/
enable. odometer, display for music players etc.

Enable DISP1 by applying a high pulse on base of Q1 2 x 16 LCD is a very common type of LCD display

at DISP1, now put the hex data corresponding to that is used in 8051 based embedded systems and is
Digit 1 on the data lines that is Port0. shown in Fig. 4.1.14.
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Microcontroller and Applications 4-11
4

DB5 DB4 DB3 DB2 DB1

RW DB7 DB6 DBO
RS
DL F X
ABCDEFGHI JKLIAOP 0 0 0 0 X

abcdeshiiklmnor Note
X = Don't care
Fig. 4.1.14 : LCD Character 2 x 16 Module DL : Sets interface data length.
DL = 1, Data is sent or received in 8
bit 5.
2 x 16 LCD display consists of 16 rows and -
length (DB7 DBO)
2
columns of 5 x 7 or 5 x 8 LCD dot matrices. DL = 0, Data is sent or received in 4 bit
It is available in a 16-pin package with back light, (DB7 - DB4)
length
contrast adjustment function and each dot matrix coe
When the 4 bit length is selected, data must be
has 5 x 8 dot resolution.
or received twice.
The pins on the 16-pin connector of the LCD Module
are given below 2
Entry Mode Set
No
PIN Sets the increment/ Decrement and Shift modes
Name Function
the desired settings
1 VSS Ground voltage RS
R/W DB7 DB6| DB5 DB4| DB3 DB2DB1 DR0
2 VCC +5V
0 0 0 0 0 1 I/D
3 VEE Contrast voltage
I/D: Increment/ Decrement the DDRAM address by
4 RS Register Select 0 = Instruction 1 whena character code is written into or read from the
Register,
DDRAM.
1= Data Register
I/D ="0", Decrement
L
5 R/W Read/ Write, to choose write or read
= "1",
mode 0 write mode 1 = read mode
=
I/D Increment
6 EN Enable: 0 = start to latch data to LCD
S :
Shift the entire display either to the right or to left.
1 = =
character, disable S 1, shift toright or left depend on I/D
7 DBO LSB of Data S = 0, display does not shift
DB1 3. Display On/ Off Cursor
9 DB2 Controls the display ON/OFF status, cursor ON/0FF
and Cursor Blink function
10 DB3
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Se
11 DB4
0 0 0 0 1 D C B
12 DB5

13 DB6
D: Controlling display
D = 1, Display is ON
14 DB7 MSB of Data D
=0, Display is 0FF
15 BPL Back Plane Light In this case display data remains in the DDRAM. It
can be displayed
16 GND Ground voltage immediately by setting D=1.
C: Display cursor
4.1.6(B) LCD Initialization
C= 1, Cursor is Displayed
1. Function Set C = 0, Cursor does not display
Sets the interface data length, the number of lines,
and character font
B: The character indicated by the
cursor blinks when B = 1
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Microcontroller r and Applications 4-12 8051 Interfacing

Display
Clear Command Function
execution of clear display instruction sets entry
The OF For switching on LCD, blinking the
mode
mode to increment cursor.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
RSRW 1
Clearing the screen
0 0 0 1

0
0 2 Return home.
Shift Decrement cursor
t Cursor of Display 4

shifts the cursor position or display to the right or 6 Increment cursor

left without writing or reading display data. This
E Display on and also cursor on
function is used to correct or search for the display
80 Force cursor to beginning of the first
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO
line
0 0 0 0 S/C RIL X X CO Force cursor to beginning of second
|0
line
Note : X = Don't care
38 Use two lines and 5 x 7 matrix
R/L Note
|S/C 3
83 Cursor line 1 position
0 0 Shift cursor position to the left
3C Activate second line
0 1 Shift cursor position to the right
1 0 Shift the entire display to the left 0C3 Jump to second line position 3

1 1 Shift the entire display to the right 0C1 Jump to second line position1

While initializing the LCD display, steps must be

4.1.6(C) Interfacing of 2 x 16 LCD
followed given below and these steps are common
for almost all applications. Draw interfacing diagram LCD display with 8051.
of

1. Send 38H to the 8

bit data line for initialization Wite function of RS and Enable pins. S-22, 4 Marks
of LCD
The Fig. 4.1.15 shows the interfacing of a 2 x 16 LCD
2. Send OFH for making LCD ON, cursor ON and
cursor blinking ON. module with 8051 microcontroller.

3. Send 06H for incrementing cursor position. P1.0

PL1
P1.2
4. Send 01H for clearing the display and return 2 Line X 16 Character
P13 LOD Display
the cursor.
11
8 P1.4
0 P1.5 DE
13
Sending data to the LCD 5 P1.6
1 P1. 4
The LCD has pins namely RS, R/W and E is used to
D7 E RW RS GND Vo Vec
6 5 4
P3.3
determine whether a given data input is a command P3.2
or data to be displayed. P3.4

The steps for sending data to the LCD module are

given below.
Fig. 4.1.15:Interfacing of LCD with 8051 Microcontroller
1. Make R/W low. Display Data Ram (DDRAM) stores the display data.
2 Make RS = 0
if data byte is a command and So when we have to display a character on LCD we

make RS = 1 if the data byte is a data to be basically write it into DDRAM.

displayed.
For a 2 x 16 LCD the DDRAM address for first line is
3. Send data byte to the data register.
from 8OH to 8FH and for second line is COH to CFH.
4. Make E pin from high to low. So if we want to display 'H' on the 7th position of
the
S. Repeat above stepsfor sending another data. first line then we will write it at location 87H.
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8051 Interfacing
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;Enable H>L
4.1.6(D) Initializing and sending Data to the CHECK: SETBP3.3

LCD CLR P3,3

Now as you have noticed two types of data is given JB P1.7,CHECK

; Read busy flag again and again
to the LCD i.e. ; till it becomes 0
1. Data to be displayed. ; Return from busy routine
RET
2. Command or special instruction.
So now let us write a subroutine for both the types Alternative CODE in assembly
of data. LCD_BUSY
Subroutine for Data to be Displayed MOV R7,#50H

LCD_DATA
BACK:
SETB P3.4 ;Set RS bít to 1 i.e. select MOV R6,#FFH
data register
CLR P3,2 Write Data to LCD DJNZ R6,S

MOV P1, A ;Character to be displayed is in A DJNZ R6, BACK

RET ;Return from busy routine

register
SETB P3.3 Here we have used delay at the end of both the
subroutines this is done to wait untilthe instruction
CLR P3.3 High to Low pulse on EN to latch the LCD.
iscompletely executed by the
data This willassure that our program gives the LCD the
CALL LCD BUSY Delay so that LCD finishes its time it needs to execute instructions and also makes
our program compatible with any LCD, regardless of
internal operations
how fast or slowit is.
RET
Before you may really use the LCD, you must
Subroutine for Command or Special Instruction. initialize and configure it. This is accomplished by
LCD_COMMAND sending a number of initialization instructions to
CLR P3.4 the LCD.
Clear RS bit i.e. Select command
The first instruction we send must tell the LCD
register
whether we'll be communicating with it with an 8
CLR P3.2 Write command to LCD bit or 4-bit data bus.
MOV P1, A
Command code is in Accumulator Now, we select a 5 x 8 dot character font. These two
SETB P3.3 High toLow pulse on EN to latch the options are selected by sending the command 38H
to the LCD as a command.
data
As you will recall from the
CLR P3.3 Delay so that LCD finishes its internal last section, we
mentioned that the RS line nmust be low if we are
CALL LCD BUSY operations sending a command to the LCD. Thus, to send this
RET 38H command to the LCD we must execute the
Subroutine for LCD Busy following 8051 instructions as a subroutine:
Subroutine in Assembly language
LCD_BUSY
INIT_LCD
SETB P1.7 Make D7th bit of LCD data
MOV A
#01H ;Clearthe display Command
port as I/P
ACALL LCD_COMMAND Write Clear Display Command
CLR P34 Select command register
ACAL LCD_BUSY
SETB P3.2 Reading Enable

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:Set 8-bit, 2 Line, 5x7 Dots ACALL LCD_COMMAND

#38H
MOVA CALL LCD BUSY
COMMAND
LCD,
ACALL MOV A, #06H ; Entry mode, set increment
BUSy
ACALLCD ACALL LCD_COMMAND
Display on Cursor blinking on
;

#OFH
AMOVA, ACALL LCD_BUSY
LCD_COMMAND
ACALL RET
BUSY LCD COMMAND:
CALL LCD
;
Entry mode, set increment ;Clear RS bit i.e. Select command
MOVA, #06H CLR P3.4

LCD_COMMAND 3 register
ACALL

ACALL
LCD_BUSY CLR P3.2 ;Write command to LCD
MOV P1, A ;Command code is in Accumulator
RET
SETB P3.3
41.6(E) Program to display "WELCOME" to CLR P3.3 High to Low pulse on EN to latch
LCD the data
"WELCOME" are LCD finishes its ínternal
Assume the eight characters the CALL LCD BUSY
to 37H.
stored in memory locationstarts from 30H
operations
memory
So, in this program we read character from RET
and send it to LCD. LCD BUSY:

SETB P1.7 Make D7th bit of LCD data port

Program
MOV R2, #07H Initialize byte counter as I/P

MOV R1, #30H Initialize memory pointer CLR P3,4 Select command register

ACALL INIT LCD ; Initialize LCD i.e, 8-bit,2 Line, Reading Enable
SETB P3.2
Dots Cursor blinking, P3.3 Enable H->L
5x7 CHECK: SETB

;Entry mode, set increment CLR P3.3

NEXT: MOVA, @R1 Read Character from memory JB P1.7, CHECK Read busy flag again and again

ACALL LCD_DATA, Write to LCD till it becomes 0

; Incremment menory pointer by

1

INC R1 RET Return from busy routìne

DINZ R2, NEXT Decrenment byte counter by i LCD_DATA:

if0 then go to NEXT SETB P3.4 Set RSbit to 1 ie. select data

SJMP AGÀIN Repeat forever register

INIT LCD: CLR P3.2 Write Data to LCD

Clear the display Command MOV P1, A Character to be displayed is in A

MOV A,
#01H
ACALL LCD COMMAND Write Clear Display Command register
SETB P3.3
ACAL LCD BUSY
High to Lowpulse on EN to latch
2
Line, 5x7 Dots CLR P3.3
MOVA, #38H Set 8-bit
; the data
ACALL LCD COMMAND

CALL LCD BUSY LCD finishes its internai operations

BUSY
ACAL LCD
on
MOV A, #OFH ;Display on Cursor blinking RET
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x;
4.1.6(F) Interfacing 20 x 4 LCD with 8051 Although the program written for the 16 2 display
x 4 LCD display
can be used with the 16 beside we
The 20 x 4 LCD displays 4 lines of 20 characters can only display on the first two lines only.
each as shown in Fig. 4.1.16. There are separate commands
for setting
the cursor
to the required line in these displays and used to set
cursor at
the line address and place the
appropriate line.
Now commands are given below, the line addrecear:
for the 16 x 4/20x 4 LCD display,
1. display the characters on the 15t line send
To

the command 0 x 80
Fig. 4.1.16 : 20 x 4 LCD Display
2. To display the characters on the 2nd line send
There is no any difference in interfacing the the command 0 CO
>x

16 x 2 LCD and the 20 x 4 LCD display in terms of

3. To display the characters on the 3rd line send
hardware pin connections means that the same >x
the command 0 94
interfacing circuit which was built for a 16 x 2 LCD
To display the characters on the 4th line send
display as shown in Fig. 4.2.16 can be used with a 4.
20 x 4 LCD display with no hardware changes the command 0 x D4
needed at all.

The Fig. 4.1.17 shows the interfacing of a 20 x 4 LCD module with 8051 microcontroller.

20 x 4 LCD Display

DB1 DB2 DB3 DB4 DB5 DB6 DB7LED LED

+5 V
VssVocee RS RWEDBO

EA

P3.5
P3,4 +5V
RST
P3.3

8051
Microontroller

P10
P1.]
P12
Pi.3
XTAL1
P1.4
P1.5
P1.6
MHz
L211.0592 XTAL2GND
P17

Fig. 4.1.17 :Interfacing of 20 x 4 LCD display with 8051

4.2 Interfacing of ADC 0808/09 with 8051

State features of ADC 0808. W-19, 2 Marks

Draw the interfacing diagram of ADC with 8051 microcontroller.
S-22, 6 Marks
One of the most commonly used ADC is ADCO808 and its pin diagram is shown in Fig, 4.2.1.

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ADC 0808 sa Successive approximation type with 8

Address Latch Enable ALE
channels i.e. it can directly access 8 single ended
The address is latched on the Low to High transition
analog inputs signals.
AnCO808 does not need the external zero and full
of ALE.
scale adjustments. The interfacing to microprocessors START
is provided by the latched and decoded multiplexer
The ADC's Successive Approximation Register (SAR)
address inputs and latched TTL tri-state outputs. is reset on the positive edge i.e. Low to High of the
Start Conversion pulse.
pn Description of ADC 0808
Whereas the conversion is begun on the falling edge
Address Line A, B, C ie. High to Low of the pulse.
The ADC 0808 has 8-channels and a particular channel OE
Output Enable
is selected by using the address decoder line.
Whenever data has to be read from the ADC, Output
Table 4.4.1 shows the input states for address lines Enable pin has to be pulled high thus enabling the
to select any channel. tri-state outputs, allowing data to be read from the
2 28 IN2
data pins D0-D7 i.e. 2-1 to 2-7.
IN4 27 IN1 End of Conversion (EOC)
2
2 IN5 2
INO This Pin becomes high when the conversion has
2
IN6 26 ADD A ended, so the controller comes to know that the data
22 24 ADD B can now be read from the data pins.
2
START ADD C
Clock
EOC 7 22 ALE
ADCO808 External clock pulses are to be given to the ADC
2 2' MSB
2
either from LM 555 in as table mode or the
Output enable 20
controller can also be used to give the pulses.
10 19
Clock
The total numbers of lines required are:
Voo 11 18
VREF(+) 12 172LSB Data lines :8
GND 16 1 VAEF()
ALE:1
2 15
START:1
Fig. 4.2.1:ADC 0808 pin diagram o EOC:1
Output Enable :1
Table 4.2.1
ADD A to ADD C:3
Analog Address Lines Hence for interfacing ADC 0808 with 8051
Channel B A microcontroller,total 15 port lines are required.
INO 0 We can directly connect the OE pin to Vec Moreover,

1
instead of polling for EOC just put some delay, so
IN1
instead of 15 lines we will require 13 lines.
IN2 0 1
We can also provide the clock through the controller
IN3 0 1 1 thus eliminating the need of external circuit for
clock.
IN4 1 0
But using all signals, the interfacing of ADC 0808
IN5 1 0 1
with 8051 microcontroller is shown in Fig. 4.2.2
IN6 1 1 where Port P2 is used read data by connecting it to
ADC0808 data bus.
IN7 1 1 1

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5V supply Ground

Vcc GND

500 kHz CLK

8051 5.12 V VAEF(O)

0.000 VVREF-) IN7

XTAL 1
SOC N6
P1.0
11.0592MHtz ALE IN5
P1.1
XTAL 2 IN44 0-5V
OE analog
IN3
P1.54 EOC input range
IN2
DB7 MSB
P2.7
P2.6 DB8 INO

P2.5 DB5
+5V NcG ADC
P2.4 DB4 0809
P2.3 DB3 10808
EA
P2.2 DB2
P2.1 DB1
st P2.0 DBO LSB

RST A
ADO
P12
P13 BAD1
Rg AD
8.2K
P14

Fig. 4.2.2 : Interfacing of ADC 0808 with 8051 Microcontroller

Port P1 is used to interface remaining handshaking Calculating Step Size

signals such as OE, ALE, START, EOC, ADD A, B, C
ADC 0808 is an 8
bit ADC i.e. it divides the voltage
etc.
applied at Vref- & Vref. into 28 i.e. 256 steps.
Algorithm to read data from ADC 0808/0809
Step Size = (Vref -Vref)/ 256
1
Start.
Suppose Vref- iS connected to Vce i.e. 5V and Vref. is
2. Select the channel.
connected to the Gnd then the step size will be
3,A Low - High transition on ALE to latch in the
Step size = (5- 0)/256 =
19.53 mv.
address.
on
Program
Start to reset the ADC's
A

Low-High transition
ADC_ DATA
SAR. BIT P2
ADD_ A
BIT
5. A High Low transition on ALE, P1,2

High - Low transition on start to start the

B
6. A ADD BIT P1,3
conversion. ADD C
BIT P1.4
Wait for End of cycle (E0C) pin to become high. ADC START BIT P1.0
8
Make Output Enable pin High.
ADC_ALE BITP1.1
Take Data from the ADC's output ADC OE
BIT P1.1
10. Make Output Enable pin Low. ADC EOC
BIT P1.5
11 Stop
ORG 0000H

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Microcontroller and Applications 4-18 8051 Interfacing

#OFFH ;Configure Port 2 as an
NOV ADCDATA, Write an ALP to generate 1 ms delay. Use Timer 0,
mode 1. Fosc = 12 MHZ. S-22, 4 Marks
;input port
SETB ADC_EOC
;
Set ADC_EOC as an input The DACO808 is an 8-bit monolithic Digital to
;Clear ADC_ALE Analog converter with a full-scale output current
CLR ADC_ALE
settling time of 150 ns and consuming only 33 mW
CLR ADC_START ;
Clear ADC START with + 5V supplies.
CLR ADCOE ;Clear ADC OE For most of the applications, no reference current
(IREF) trimming is required since the full-scale
NEXT:
output current is typically + 1 LSB of 255 IREF/256
Select Channel 0 ie. INO
CLR ADD_À
and the power supply current of the DAC0808 is
CLR ADD_B independent of bit codes.
CLR ADDC The pinout diagram of DAC 0808 is shown in
Fig. 4.3.1.
ACALL DELAY ;Wait for some time
The Fig. 4.3.2, shows the interfacing of DAC 0808
SETB ADC ALE Latch the address to select INO with 8051 microcontroller, where Port 0 is
ACALL DELAY Wait for some time connected to data pins of DAC 0808 i.e. A1 to A8.

SETB ADC_START ; Start the conversion of analog COMP 16|

1NG
;input on INO
2 GND VAEF- 15
ACALL DELAY Wait for Some time
VAEF+ 14
3VEE
CLR ADC ALE
MSB4
O
VCo13 LSB
CLR ADC START
5|A1 A812
REPIT:

JB ADC EOC, REPIT:Wait until EOC from ADC 0808 6A2 A7 11

REPT: 7 A3 A6 10
JNB ADC EOC, REPT 8A4 A59
SETB ADc OE ; Make available converted
Fig. 4.3.1: Pinout of DAC0808
data on D0-D7
ACALL DELAY, Wait for some time
The output of DAC is in the form of current, but we
need voltage as a output, so, current to voltage
MOV A, ADC DATA; Read binary data from DO-D7 converted is used.
of ADC 0808
Calculation of Io i.e. Lour and Vo i.e. Vour
on LCD
ACALL DISPLAYDisplay data lo= K
128 256
SJMP NEXT
VREE
Where, K= Ra
4.3 Interfacing of DAC 0808 with 8051
Vo = Re x I,
DAC to 8051.
Draw and explain the interfacing
of
- A3 Ag As A6 A7 As
S-19, W-19, 4 Marks Rk16*32 64128* 256
Q Draw the interfacing diagram of DAC with 8051
microcontroller. Write an ALP to generate a square
waveform. S-22, 4 Marks

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8051 Interfacing
Microcontroller and Applications 4-19
+5V

EA VoG
+5V
8051
Microcontroller Voc R14

RST P0.0 A1 Vref-wWAa W

Vref
PO.1 A2
Rg
PO.2 A3 Gnd
R,
P0.3 A4 DACO808 W

PO.4 A5
Iout
PO.5 A6
PO.6 A7 Vout
PO.7 A8 Comp

XTAL 1

15pF
+12V
i1.0592MHiz
XTAL2
GND

Fig. 4.3.2: Interfacing of DAC0808 with 8051

Simple Programming in Assembly Language Program 2: Write a program to generate a Stair Step

Voltage from DAC 0808 with stair step voltage from 0 volt
Program 1: Write a program to generate a voltage 2
volt from DAC0808. Assume Vref =5 volt, R,, =5 k. and trough 5 volt, with resolution 0.5 volt each step using LOOK
UP R = 5k.
Table. Assume Vef=5volt, Ry4=5 k, and
R,= 5k.
Soln.: Soln.:
With reference to figure shown in Fig.4.3.2, first we With reference to figure shown in Fig. 4.3.2, first we
have to find out the binary value to generate voltage of have to find out the binary value to generate steps of
2 volt from DAC 0808 as shown. voltage of 1 volt from 0 volt to 5 volt as shown below.
K = Vret/ Ri4 =
5/5k =1 mA K = Vef/ Rq4 = 5/5k = 1 mA
If, we put logic high into A1 through A8 then we
If, we put logic high into A1 through A8 then we have:
have:
I, = 1mA x 0.99 =1 mA I, = 1mA x 0.99 =1 mA
So, So,
Vo = L, x
R=1 mA 5k= 5 voltx
Vo = , x R,= 1 mA x 5k= 5 volt
= =
Voltage Resolution 5/255 0.02 volt =
Voltage Resolution 5/255 = 0.02 volt
If you like to send 2 volt out from your
a DAC, than
you must the value in binary or decimal So, the steps voltages are calculated below.
1. =
Value = 2/0.02 = 100 decimal (64H) Voltage 0 volt 0/0.02 =0 decimal or HEX
Program 2. Voltage 0.5 volt = 0.5/0.02 =
25 decimal or 19H
3 Voltage 1 volt = =
START: MOV A,#100Load value in A
register 1/0.02 50 decimal or 32H
4. Voltage 1.5 volt =
1.5/0.02 =75 decimal or 4BH
MOV PO,A Send it to DAC 0808 to generate
5 =
Voltage 2 volt 2/0.02 = 100 decimal or 64H
voltage of2 volt
6. Voltage 2.5 volt = =
2.5/0.02 125 decimal or 7DH
SJMP START Continuously
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Microcontrollerrand Applications
4-20 8051 Interfacing
=
Voltage 3 volt 3 /0.02 150 decimal or 96H DELI: MOV R2,#255
=
Voltage 3.5i volt 3.5/0.02 175 decimal or AFH
DEL2: DJNZ R2, DEL2
=
Vooltage 4 volt 4/0.02 200 decimal or C8H
=

9 DJNZ R1, DEL1

=
Voltage 4.5 volt 4.5/0.02 = 225 decimal or ElH
J0. RET
s Voltage 5 volt = 5/0.02 = 255 decimal or FFH Program 4 : Write a program to generate a Triangular
Assume all 11 value for 11
step of 0.5 volt are stored Wave from DAC 0808.
external memory from memory location 3000H, So,
Soln.:
need memory pointer to read these value.
oe

For the triangular wave, simply start sending data

Program
from 00 to FFH to DAC with appropriate delay for rising
START:
edge of triangular wave and for falling edge start sending
MOV DPTR, #3000H ;Initialize memory pointer data from FFH to 00 to DAC with same delay to get
MOV R2, #11 ;Initialize byte counter perfect triangular wave.
MOVX A,@DPTR ;Read DAC data from
1P:
Program
; look up table
START: MOVR1, #00H ;Start rising edge of triangular
MOV PO, A :Send it to DACO808 wave
INC DPTR Increment memory pointer by 1
UP: MOV PO, R1
DJNZ R2,UP
Decrement byte counter by 1
ACALL DELAY Add appropriate delay
;if0,go to UP ; Set next value for rising edge
INC RI
CALL DELAY Add delay
CJNE R1, #FFH, UP If not max peak of triangular
SJMP START :Continue the generation of stair
; wave then P

; case wave
ELAY: UP1: MOV PO, R1 ;Start falling edge of triangular
MV RO, #0
ELAY1: MOV R2, #0FH wave
ACALL DELAY Add appropriate delay
DJNZ R2, $
DJNZ RO, DELAY1 DEC R1

RET CNJE R1,#00H, UP1 lfnot min pcak of triangular

wave then UP1

Program 3: Write a program to generate a Square
SJMP START Continuous triangular wave
lave from DAC 0808.
DELAY: MOV P1, #255 subroutine to add delay
oln.:
DEL1: MOV R2, #255
We can send FFH to get High pulse and 00 to get low DEL2: DJNZ R2, DEL2
ulse at the output of DAC 0808 with some delay. The
DJNZ R1, DEL1
llowing is the general program with some approximate
elay. RET

rogram Program 5 : Write a program to generate a Saw tooth

TART: MOV PO,
Wave from DAC 0808.
#0FFH:Send value to get HIGH pulse
ACALL DELAY Remain HIGH for time T1 Soln.:
MOV PO, #00H Send value to get LOW pulse For the saw-tooth wave, simply start sending data
from 00 to FFH to DAC with appropriate delay for rising
ACALL DELAY ;Remain LOWfor time T1

edge of triangular wave and for falling edge start sending

SMP START Continuous Square wave
data 00 to DAC without delay to get perfect saw-tooth
ELAY: MOV R1, #255 subroutine to add delay wave. Repeat the same to get continuous saw tooth
wave.
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4-21
Program Calculate the number of address lines required t
START: MOV R1, #00H 3 Start rising access 16 Kb ROM W-19, 2 Marks
edge of Saw Tooth
as RAM, ROM, PROM,
1wave 1 Every memory chip such
EPROM, EZPROM and DRAM have numbers of pins
UP: MOV PO, R1

ACALL DELAY
and used to accept different kinds of signals.
Add appropriate delay
2. Basically each and every memory device has pins
INC R1 Set next value for rising edge
for address, data, control signals and chip select
CJNE R1, #FFH, UP If not max peak of Saw Tooth signals.
;wave then UP
Address pins
UP1: SJMP START ;
Start falling edge of Saw Address pins are used to read address of the
;Tooth wave memory location from the system address bus
;Continuous Saw Tooth wave transmitted by the microcontroller.
DELAY: MOV R1, #255;subroutine to add delay The numbers of address pins on the memory device
DEL1: MOV R2, #255 is depending on the size of the memory as shown in

DEL2: DNZ R2, DEL2 Table 4.4.1.

Table 4.4.1
DJNZ R1, DEL1

RET No. of Address lines Size of memory in bytes

used
4.4 Memory Interfacing 1 2

2 4
4.4.1 Introduction 3 8
Memory is the storage device which is used to store 4 16
monitor program, userS program or users data. 5 32
So memory is the important element of the
6 64
microcontroller based system, which will allow to
7
store program and data. 128
8 256
The memory consists of the numbers of memory
cells arranged to store data. 512
Each memory cell is used to store1 bit of
the data. 10 1024 1k
Hence, memory must be interfaced with 11 2048 2k
microcontroller to store programs or data of user or 12 4096 ~ 4k
system, so that it can be accessed while reading or
13 8192 8k
writing data or program from/to it.
14 16384 16k
Access time of the memory chip is commonly
15 32768
referred to speed of the memory. 32k
16 65536 64k
4.4.2 Semiconductor Memory 17 131072 128k

Find out the number of address lines required to 18 262144 ~ 256k

access 4KB of RAM. S-19, 2 Marks 19 524288 512k
20 or 1 MB
1048576 1024k

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4- 22 8051
Interfacing
Datapins 4.4.3 Different Memory IC's Available
the data bus depends on the size of the
The size of
each memory location within memory in which data Type of IC Memory Sizes
memory number
is stored and specified in the terms of bits or byte. Address lines x data lines
The standard size of data pins are 1, EPROM 2716
4, 8 etc. 2Kx 8
EPROM 2732 4kx8
s [Chip select] or CE [Chip enable] EPROM 2764 8kx8
CSsignal of the memory chip is an active low signal SRAM 6116 2kx8
and used as an enable pin during read or SRAM
write 6264 8kx 8
operation. SRAM 2114 1kx4
Hence, during every read or write operation,
this
signal must be go low otherwise no read or write
4.4.4 Address Decoding
operation will be performed. Address decoding is the process of generating chip
WR [Write Control Signal] select (CS) signals from the address bus for each
device in the system
The WR signal is an active low input control signal
Using a simple logic gate like AND or NAND gate
which is used to write data to the memory location
address decoder, we can generate chip select (CS)
whose address is available on address lines ifCs signals from the address bus as shown in Fig. 4.4.1.
signal is active.
This signal is generated by the microprocessor or
other master in the system such as DMA controller
4Kx8
or co-processor and available on system control bus.

RD /OE [Read / Output Enable] A0- A11A0- A11

A12
The RD / OE is an active low input control signal A13
A14
which is used to read data from the memory A15 RD WR
RD
location whose address is available on address lines
WR
if CS signal is active.
Fig. 4.4.1: Using NAND Gate as decoder
- This signal is generated by the microprocessor or
other master in the system such as DMA controller To generate chip select (CS) signals, A15-A12 must
or co-processor and available on system control bus. be 0011 and finally address space is 3000H to
Beside these signals described above, some 3FFFFH for 4K x 8 memory.
additional pin also available depending on the type The another digital device that we can use is
of memory such as Vpp and PGM pins that are 74LS138 i.e. 3-8 Decoder which has three input A, B,
available in EPROM for programming as in normal and C which select any one of the eight active low
condition EPROM is read only memory. output i.e. YO to Y7
EPROM can be programmed for that the separate The Address lines A12 to A1s are connected to
EPROM programming hardware is required. 74LS138 ie. 1-3 decoder to generate chip select (CS)
signals is shown in Fig, 4.4.2.

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8051 Interfacing
Microcontroller and Applications 4-23

A15 Voc 4Kx8

G2A G2B G1 YO
Yi b -A11A0 -A11
A0

Y2
A12 A 74LS138
A13 3:8 CS
A14 decoder AD WA
Y5
Y6P AD
WR
Fig. 4.4.2 : Using 74LS138 Decoder
The address map of the both i.e. NAND as decoder and 74LS138 Decoder are given in Table 4.4.2(a) and (b).
Table 4.4.2(a) Address map NAND as decoder
:

A1sA14 A13|A12 A11 A10 Ag| As| A

Ao As A4 A3 Az A1 Ao Address
|0 1 1 0 000 0 0 0 0 03000H
3FFFH
0 1 1 1 1 |11 11 111111
Table 4.4.2 (b) : Address map for 74LS138 decoder

|A1s| A14 A13|A12| A11|A10 Ag| AgA A6As|A4| A3| A2| A1|Ao|Address
1 0 0 0 0 4000H
0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 1 11 1 1 4FFFH

4.4.5 Absolute and Linear Decoding

DO- D7
Techniques
4Kx8
There are two main techniques:
(A) Absolute decoding/ Full Decoding A0 A11A0 - A11
(B) Linear decoding / Partial Decoding A12
A13
A14
4.4.5(A) Absolute Decoding A15 RD WR
RD
WR
Q. Draw interfacing diagram of relay connected to P2.1
Fig. 4.4.3 : Absolute decoding to
of 8051 c. S-22, 2 Marks generate chip select signal
All thehigher address lines of microcontroller or
microprocessor are decoded to generate chip select
4.4.5(B) Linear Decoding
signal to select the memory chip, and the memory In small systems, hardware for the decoding logic
chip is selected only for the specified logic level on can be eliminated by using individual
high-order
these high-order address, no other logic levels can address lines to select memory chips.
select the chip, mostly logic level is low to select
memory chip. This is referred to as linear or partial decoding.

This addressing technique is normally used in large It reduces the cost of the decoding circuit but has
it
a drawback of multiple address ie. shadow
memory systems.
addresses for the same memory location.
Using a simple logic gate like AND or NAND gate
Using a simple logic gate like AND or NAND gate
address decoder, we can generate chip select (CS)
signals from the address bus as shown in Fig. 4.1.3. address decoder, we can generate chip select (CS)
signals from the address bus as shown in Fig. 4.4.4.
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Microcontroller and Applications

4-24 8051 Interfacing

OD700-D7 Sr. Absolute Decoding Linear Decoding

4KX8
No.

3 The memory chip is Hardware for decoding

AO
A11A0- A11
selected only for logic can be elimínated
specified logic level by using individual
A15
on higher order higher-order address
RD WA
address lines, no lines to select memory
RD
other logic levels can chips.
WR
select the memory
a A4.4: Linear decoding to generate chip select signal chip.

A.5(C) Difference between Absolute and 4 Increases the cost Reduces the cost of
of

decoding circuit. decoding circuit.

Linear Decoding
5 Used in large Used in small memory
Differentiate between linear and absolute address memory system. system.
decoding technique. (Any 4 points).

. S-15, S-17, W-17, 4 Marks

Compare absolute decoding and linear decoding
4.4.6 Data, Address and Control Bus of 8051

W-18, 4 Marks State mnaximum size of external memory that can be

interfaced with 8051 uC. Explain it. S-22, 2 Marks
Sr. Absolute Decoding Linear Decoding
No. Q. Define the term bus. Write size of buses in 8051 uc.
S-22, 2 Marks
1 address lines are Not
All all memory
used to specifylocations are used, only I/0 ports P2 and P3 are used for their addressing
memory location to a
subset of address and data transmission.
address physical are needed to
memory location. lines Port 2gives A8-A15 higher order address bus and
address the physical
memory location. Port 3 gives AD0-AD7 multiplexed address/data
bus.
2 Each physical Each physical memory
memory location has has several possible The Octal latch 74LS373 is used to de-multiplexed
a unique address. address. address bus and data bus using ALE signal as shown
in Fig. 4.4.5.

EA(RD) P3.7 RD
Control
{WR) P3.6 WR bus
PSEN PSEN

P2.7 A8- A15

8 bit
Higher order
P2.0 address bus
8051
ALE

PO.7
A0 - A7
AD0 - AD7 74LS373 8 bit Lower order
PO.0 address bus

D0 - D7
Data bus

Fig. 4.4.5: Address, Data and Controi bus of 8051

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4-25
The 8051 microcontroller has two separate These both signals are active at logical zero (0)
reading
signals RD(P3.7) and PSEN. level.

The first one is activated byte from external The 8051 microcontroller has writing signals WR
data
memory (RAM) should be read, while one (P3.6) and this signal is active low.
another is
activated to read byte from external program
memory (ROM).

4.4.7 Interfacing of 8K x 8
Program ROM
x
To interface 8K 8
Program ROM,13 address lines and8 data lines are required.
EA (RD) P3.7
(WA) P3.6 WR
PSEN OE

P2.0- P2.4
8 bit A8- A15 A8- A12
8051
ALE
Program
ROM

-
P0.0- P0.7 ADO AD7 74LS373 B
bt A0 A7

8K x8
(2764)

Voo
DO D7
G2A G2B G1 Yoþ
Y1
Y2
(P2.5) A13 74LS138
(P2.6) A14 3:8
(P2.7) A15 decoder
Y5

Fig. 4.4.6: Interfacing of 8K x 8 External Program ROM

So, we can use A0-A12 address lines and DO-D7 data lines to
interface Program ROM with 8051.
The Latch 74LS373 is used to de-multiplexed AD0-AD7 bus and decoder 74LS138
is used to generate chip select
( CS) signal.

The signal PSEN is connected to 0E of Program ROM.

The complete interfacing of 8K x 8 program ROM with 8051 is shown in Fig. 4.4.6.
The complete memory map of program ROM is given in Table 4.4.3.
Table 4.4.3: Address map 8K x 8 Program ROM

A15A14 A13|A12 A11 A10

A9As| A7A6| As A4 A3 A2
A1 Ao
Address
1 0 0 0 0 0 0 0 8000H
1 0 1 1 1 1 11 1 1 1 1 1
9FFFH

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4- 26 8051 Interfacing

Interfacing of 8K x 8
Data ROM
4.8
x 8 data
To interface
8K ROM, 13 address lines and 8
data lines are required.
e can use A0-A12 address lines and DO-D7 data lines to interface data ROM with 8051.
nhe Latch 74LS373 is used to de-multiplexed
AD0-AD7 bus and decoder 74LS138 is
used to generate chip select
CS signal.

The signal RD is connected to OE of data ROM.

The complete interfacing of 8Kx 8 data ROM with 8051 is shown in Fig. 4.4.7.
EA (AD) P37
(WA) P3.6 W
PSEN

P2.0 - P2
8 bit
A8- A15 A8 A12

8051
ALE
Data
ROM

PO.0- PO7 ADO AD? 74LS373 8 bit A0 A7

8K
x8

DO D7

(P2.5) A 13A 74LS138

P2.6) A14 3:8
(P2.7) A15C decoder

Fig. 4.4.7:Interfacing of 8K x 8 External Data ROM

The complete memory map of data ROM is given in Table 4.4.4.

Table 4,4.4 : Address map 8K x 8 Data ROM

A1s A14| A13|A12 A11 A10 A

Ag| Az| Ac| As A4 As| Az A1
Ao Address
1 0 0 0 8000H
1 1 1 1 1 1 1 1 1 11 1
1|1 9FFFH

4.4.9 Interfacing of 8K x 8 Data ROM and 8K x 8 Program ROM

To interface 8K x 8 data ROM and 8Kx 8program ROM, 13 address lines and 8 data lines are required.

So, we can use A0-A12 address lines and D0-D7 data lines to interface Data ROM and Program ROM with 8051.

The Latch 74LS3 73 is used to de-multiplexed ADO-AD7 bus and decoder 74LS138 is used to generate chip select

CS signals.

The complete interfacing of 8K x 8 data ROM and 8K x 8 program ROM with 8051 is shown in Fig. 4.4.8.

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The complete memory map of program ROM is given in Table 4.4.5(aJ.

Table 4.4.5 (a) : Address map 8K x 8 Program ROM

A1sA14 A13 A12 A11AioAaAnAzA As

A4 A3 A2| A1Ao Address
1 0 0 0 0 0 0 0 0 0 8000H
1 0 1 1 1 1 1 1 1 1
11 1 1 9FFFH

The complete memory map of Data ROM is given in Table 4.4.5(b).

Table 4.4.5(b) : Address map 8Kx 8 Data ROM

A1s A14 A13 A12 A11|A10 A, AgAz| As

AsA4 A3 A2|A1
Ao Address
1 1 0 0 0 0 0 0 0 0 0 A000H
1 BFFFH
1 1 1 1
11 1 1 1
1 1
11 1
EA (RD) P3.7 RD
(WR) P3.6 WR
PSEN OE
P2.0- P24!
8 bit A8 A15
A8- A12 A8- A12

8051
ALE
Data Data
ROM ROM
PO.0-PO: ADO- AD7 74LS373 8 bit A0 - A7 A0- A7

8K x 8 eK x8

8bi! DO D7 DO- 07
G2A G2B G1 YO

(P2,5) A13 Y2
74L8138 Y3
(P2.6) A14 3:8
(P2.7) A15 decoder Y5
Y6

Fig. 4.4.8 :Interfacing of 8K x 8 External Data ROM

and Program ROM

4.4.10 Interfacing of 8K x 8 Data RAM The signal RD of 8051 is connected to OE of data

To interface 8Kx8 data RAM, 13 address lines and RAM.
8
data lines are required.
The signal WR of 8051 is connected to WR
So, we can use A0-A12 address lines and DO-D7 data of data
RAM
lines to interface data RAM with 8051.
The Latch 74LS373 is used to de-multiplexed The comnplete interfacing of 8K x 8 data ROM with
AD0-AD7 bus and decoder 74LS138 is used to 8051 is shown in Fig. 4.4.9.

generate chip select CS signal.

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Microcontroller and Applications 4- 28 8051 Interfacing

EA (RU) P3.7
WA) P36 WR

PSEN
WR
P2.0- P2.4
8 bit A8- A15 A8- A12

8051
ALE
Data
RAM
- AD7 A0- A7
PO.0PO7ADO 74LS373 8 bit

8K x8

Voc
8 bit DOD7
G2A G28 G1 YOF
CS

74LS138 Y2þ
(P2.5) A13A
P2.6) A14B 3:8
(P2.7) A15C decoder

Fig. 4.4.9 : Interfacing of 8K x 8 External Data ROM

The complete memory map of data ROM is given in Table 4.4.6.

Table 4.4.6 : Address map 8K x 8 Data RAM
|A1s|A14 A13|A12|A11 A1o As As
A,|A6 As |A4 A3Az A1|Ao Address
1 0 0 00 0 0 00 00 8000H
1 1 1 1
11 1
11 11 11 1 9FFFH

4.4.11 Interfacing of 64K External RAM and ROM

memory chips with capacity of 64KB each.
When we feel insufficiency of memory then we can add two external
as
I/0 ports P2 and P3 are used for addressing and data transmission shown in Fig. 4.4.10.
The 8051 microcontroller has two separate reading signals RD (P3.7) and PSEN.
When the RD is activated then byte from external data memory (RAM) should be read, while PSEN is activated
then 8051 reads byte from external program memory (ROM) and these signals are active low.
For example, the Fig. 4.4.10 shows the interfacing of RAM and ROM with 8051 and is called Harvard architecture.

PSEN
A9 A13
A12
WA WR
A10
A9
AA
AB

RAM(S4K) ROM(64K)
a8538868 A7
A6 D6

A3

8051

s88389a8

ALE

Fig. 4.4.10 : Interfacing of 64K External RAM and ROM

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memory (ROM), the microcontroller.
when the 8051 microcontroller starts execution from external
generates ALE signal and transmit lower 8 bits of address i.e. A0:A7 on PU.
Now ALE pin is connected to 74HCT573 octal latch.
A SIgnal on the pin ALE, the 74HCT573 octal latch latches higher bits
8 of address A0-A7 on the output pins
of latch which are available on the port.
The higher address byte i.e. A8-A15 is transmitted on Port 2 at the same time.
In this way 16 bit memory address is transmitted to memory device.
as an input, then PSEN signal is generated by the
Now ALE i.e. removed by the 8051, and PO is configured
microcontroller to reads content from memory location whose address is already transmitted.
The Port 0is
used both for data and lower address byte.
is
Same thing is happened when 8051 reads some data from external Data Memory where, addressing
performed in the same way, while reading or writing of data is performed using signals RD or WR.

4.4.12 Interfacing of 4KB RAM and 4KB EPROM

Draw interfacing diagram of 4K byte EPROM and 4K byte RAM to 8051 microcontroler. Daw memory map
W-16, S-17, W-18, 4 Marks

Draw the interfacing diagram of 8 K byte of EPROM and 8 K byte of RAM to 8051 microcontroler. Draw the address

map table for same W-17, 6 Marks

To interface 4K × 8 RAM and 4K x 8 EPROM,12 address lines and 8 data lines are required.
So, we can use A0-A11 address lines and DO-D7 data lines to interface RAM and EPROM with 8051.
The Latch 74LS373 is used to de-multiplexed ADO-AD7 bus and decoder 74LS138 is used to generate chip select
CS signals.
The complete interfacing of 4K x 8 EPROM and 4Kx 8 RAM with 8051 is shown in Fig. 4.4.11.

The complete memory map of 4K EPROM is given in Table 4.4.7(a).

Table 4.4.7(a) : Address map 4K EPROM

A1s A14|A13 A12|A11|A10 Ag Ag Ay A6|As| A4A3 A2A1 Aol Address

1 0 0 0 0 0 0 0 0 8000H

1 1 1 11 1 1 111 1 1 8FFFH

The complete memory map of 4K RAM is given in Table 4.4.7

(a).

Table 4.4.7(b) :Address map 4K RAM

AsA14|A13 A12Aii A10 A9 As A7 As As

A As| Az A
Ao Address

1 0 1 0 00 00 0 0 0 A000H

1 1 0 1 1
1|1 11 1 1 1 11 1 AFFFH

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4-30 8051 Interfacing
EA (BD) Pa7
(WR) P36 W
PSEN

P2.0-P2
8 bit AB-A15 A8-A11 A8-A11
8051
ALE

EPROM RAM
PO.0- PO,7 ADO AD7
74LS373 8bit A0 - A7 A0- Á7

4K x 8 AKx8

Voc
DO- D7 DO D7

A12 =X C2A G2BG1 YOP

Y

(P2.5) A13A 74L8138

Y3
(P2.6)A14B 3:8
(P2.7) A150 decoder
Y6

Fig. 4.4.11:Interfacing of 4K x 8 EPROM and 4K x 8 RAM with 8051

To interface 4K x 8 RAM and 4Kx 8RAM, 12 address lines and 8 data lines are required.

So, we can use A0-A11 address lines and D0-D7 data lines to interface RAM with 8051.

The Latch 74LS373 is used to de-multiplex ADO-AD7 bus and decoder 74LS138 is used to generate chip select
CS signals.
The complete interfacing of 4K>x8 RAM 1 and 4K x 8 RAM 2 with 8051 is shown in Fig. 4.4.12.

The complete memory map of 4K x 8 RAM 1 is given in Table 4.4.8(a).

Table 4.4.8(a) :Address map 4K x 8 RAM 1

A
As AE A
A1 Ao Address
A1s A14 A13 A12 A11
A10 Ag AB A4 A3

0 0 0 0000H

0 1 1 1 1 1 1 1 1 1 1 1 1 OFFFH

The complete memory map of 4K RAM 2 is given in Table 4.4.8(b).

Table 4.4.8(b) : Address map 4K x 8 RAM 2

A1s A14
A13 A12 A11 A10 Ag Ag
A
A6 As A A
A2
A
Ao Address

1 0 0 0 0 0 0 0 0 0 2000H
0

1 0 1 1 1 1 1 1 1 1 1 1 1 1 2FFFH
0 0

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RD RD
E WR WA
PSEN OE
P2,-P2, AgAgt AgAt

ALE
5 4kx 8 4kx8
RAM RAM

AD-AD, G

Po7 74LS373 AoAy

AoAy

D-D D,D,
8 Bit
CS CS

Aq5
A14

A13 A
A2 74LS138
G
A11

Fig. 4.4.12 : Interfacing of two 4K RAM

Interfacing of 8Kbyte EPROM and 8Kbyte RAM
EA (RU) P37

PSEN

A15A8-A12A8A12
8051
ALE
EPROM FARM

PO0 PO7 T4S3738ct A0-A7 AO AT

8K8 8KXS

P2.5) A13-A 748813R

P2.61 Afí4
P27 Af15

Fig. 4.4.13 : Interfacing of 8Kbyte EPROM and 8Kbyte RAM

The complete memory map of 8Kbyte of RAM is given in Table 4.4.9(a).

Table 4.4.9(a) : Address map 8Kbyte EPROM

A1sA14 |A13A12 A11 A10 Ag Ag

A7 |A6 As A4 As A2
A1A Address

1 0 0 0 0 0 0 0 0 0 0 0 0 0 800OH

1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFH

The complete memory map of 8Kbyte EPROM is given in Table 4.4.9(b).

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Table 4.4.9 (b) : Address map

8Kbyte RAM

A15 A14 A13 A12 A11 A10 Ag As Az A6 As A4 A3 Az A1 Ao Address

1 0 1 0 0 0 0 0 0 0 0 A000H
1 1 1 1 1 1 1 1 1 1
11 1 1 1 BFFFH

A.13 Interfacing of 2K x 8 Data RAM

Tointerface 2KB data RAM, 11 address lines and 8 data lines are required.
So.we can use A0-A10 address lines and DO-D7 data lines to interface data RAM with 8051.

The Latch 74LS373 is used to de-multiplexed AD0-AD7 bus and decoder 74LS138 is used to generate chip select

(CS) signal.

The signal RD of 8051 is connected to OE of data RAM.

The signal WR of 8051 is connected to WR of data RAM

The complete interfacing of 2KBdata RAM with 8051 is shown in Fig. 4.4.14.
EA (RD) P3.7 RD OE
WR WR
(WR) P3.6
PSEN

P2.0- P2.4 A10O

8 bit A8 A15 A8-

8051
ALE
2KB
DATA RAM

ADO - AD7
PO
0PO.7 74LS373 3 bit A0- A7

A11 A12
DO D7
8 bit
G2A G2B G1 Yob CS

Y2
(P2.5) A13 74LS138 Y3
(P2.6) A14 3:8
(P2.7) A15 - Y4b
decoder Y5

Fig. 4.1.14: Interfacing of 2K x 8 Data RAM

- The complete memory map of data ROM is given in Table 4.4.10.

Table 4.4.10 :Address map 2KB Data RAM

A15| A14 A13| A12A11 A10 Ag Ag Az As| As A4A3 Az A1 Ao Address

1 0 0 1 0 0 0 0 00 0 9000H
1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 97FFH

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4.4.14 Interfacing of 2K x 8 RAM and 2K x 8 EPROM
Draw the memory map.
Draw Interfacing of 2 Kbyte EPROM and 2 Kbvte RAM to 8051 microcontroller.
S-15, W-15, S-18, 6 Marks
to memory map. S-19, 4 Marks
Sketch interfacing diagram of 2 Kbyte RAM and 2 Kbvte EPROM 8051. Draw the
To interface 2K x 8 RAM and 2Kx 8 EPROM, 11 address lines and 8 data lines are required.

So, we can use A0-A10 address lines and D0-D7 dat lines to interface RAM and EPROM with 8051.
The Latch 74LS373 is used to de-multiplexed ADO-AD7 bus and decoder 74LS138 is used to generate chip select
CS signals.
The complete interfacing of 2K x 8 ROM and 2Kx8 ROM with 8051 is shown in Fig. 4.4.15.

The complete memory map of 2K EPROM is given in Table 4.4.11(a).

EA RO P37
WA) P36
WR

805t
ALE
2KB 2KE
RAM
EPROM

PUD PO.Ao7 4LS373 A-A7

A13
P25) 741.3138
P2.6) A1i
A15
(P27)

Fig. 4.4.15 :Interfacing of 2K RAM and 2K EPROM

Table 4.4.11(a) : Memory Map for 2 Kb RAM

A1s A14|A13 A12 A1n A10| A

As A7
As As A As Az A1 AoAddress

1 0 1 1
00 000 00000 DO00H

1 0 1 1 1 1 111|1 1 1
11 D7FFH

Table 4.4.11(b) : Memory Map for 2 Kb EPROM

A1s A14|A13 A12A11 A10 Ag| Aa A

A6 As| A4| A3 Az A1 Ao Address
1 0 1 0 000 00 0
9000H
1 0 0 1 1 1 1 1 11 1 1
111 97FFH

Review Questions

Q. Draw interfacing diagram of relay with 8051 microcontroler. Write an ALP to turn ON and OFF relay.

Draw the diagram to interface external RAM and ROM with 8051. Mention the pins during interfacing and describe in brief.

Find out the number of address lines required to access 4 KB of RAM.

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4-34 8051 Interfacing
Drawinterfacing diagram of 4 x 4 keyboard matrix with 8051 microcontroller.
Q.

lateh interfacing diagram of 2 Kbyte RAM and 2 Kbyte EPROM to 8051. Draw
the memory map.
Aveteh 8051 interfacing diagram to interface 4 LED's and 4 switches. Inteface switches to port
0 and LED to port 1
.onner nibble.
Develop an ALP to read status of switches and operate LED's as per switch status.

. State features of ADC0808

A
Draw and explain the interfacing of DAC to 8051.
Draw interfacing of 16 x 2 LCD with 8051 state the function of EN and RS pin of
and LCD.
o
Draw the interfacing diagram of Relay connected to P2.1 pin of 8051 microcontroller.
0. Draw the interfacing diagram of LCD Display with 8051.Write
the function of RS and ENABLE pins.
0. Draw the interfacing diagram of ADC with 8051 microcontroller.

Q. Sketch interfacing diagram of 4K byte EPROM and 4K byte of RAM to 8051.

0. Interface ADC 0809 with 8051 and write a program to read data from the device and convert to digital.