VLSI Design and Testing 1 Silicon Semiconductor Technology

Dr. T. THIMMAIAH INSTITUTE OF TECHNOLOGY

Department of Electronics and Communication Engg.

VLSI Design and Testing(BEC602)

CMOS Process Technology

1 Silicon Semiconductor Technology

1.1 Introduction
ˆ Silicon, in its pure (intrinsic) state, is a semiconductor with an electrical resistance that lies
between that of a conductor and an insulator.

ˆ Unlike metals, whose conductivity is primarily due to free electrons, silicon’s electrical
properties can be significantly modified by introducing impurities into its crystal lattice.

ˆ The process of adding impurity atoms to silicon to alter its conductivity is called doping.

ˆ The introduced atoms, known as dopants, can either donate free electrons or create electron
vacancies (holes)

ˆ Certain impurity elements accept electrons from the silicon lattice, creating holes as the
majority charge carriers.

ˆ These dopants are called acceptors, and common examples include boron (B) and gallium
(Ga).

ˆ Other impurity elements contribute free electrons to the silicon lattice, making electrons the
majority charge carriers.

ˆ These dopants are called donors, with common examples being phosphorus (P) and arsenic
(As).

ˆ When n-type and p-type silicon materials are brought together, a transition region known as
a PN junction is formed.

ˆ This junction plays a crucial role in semiconductor devices.

ˆ By arranging multiple PN junctions in specific physical structures, various semiconductor

devices such as diodes, transistors, and integrated circuits (ICs) can be designed.

ˆ Semiconductor fabrication has evolved significantly, allowing precise control over junction
properties, leading to highly efficient and miniaturized electronic components.

1.2 Wafer Processing

ˆ Semiconductor manufacturing begins with silicon wafers, thin disks of single-crystal silicon,
typically 75 mm to 150 mm in diameter and less than 1 mm thick.

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VLSI Design and Testing 1 Silicon Semiconductor Technology

ˆ These wafers are cut from ingots grown using the Czochralski method, the most common
technique for producing high-purity silicon.

1.2.1 Czochralski Method

Figure 1: Czochralski process for manufacturing silicon ingots

ˆ High-purity polycrystalline silicon is melted in a quartz crucible, surrounded by a graphite
radiator, and heated using radio frequency induction.
ˆ The temperature is maintained slightly above 1425 ◦ C, with an inert gas (helium or argon)
preventing contamination.
ˆ A seed crystal is dipped into the melt and slowly withdrawn while rotating.

ˆ The molten silicon solidifies, maintaining the single-crystal structure of the seed.

ˆ The ingot diameter is controlled by the withdrawal rate and rotation speed, with
growth rates ranging from 30 mm h−1 to 180 mm h−1 .

1.2.2 Wafer Slicing and Polishing

ˆ The grown ingot is sliced into wafers using diamond-tipped blades, with thicknesses
between 0.25 mm and 1.0 mm, depending on diameter.
ˆ At least one face is polished to a mirror finish to remove surface irregularities and ensure a
defect-free surface for semiconductor fabrication.

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VLSI Design and Testing 1 Silicon Semiconductor Technology

1.3 Oxidation
ˆ Silicon dioxide (SiO2 ) plays a crucial role in the fabrication of silicon integrated circuits.
ˆ Many manufacturing techniques depend on its insulating and passivating properties, making
reliable SiO2 formation essential.

1.3.1 Oxidation Process

ˆ Silicon oxidation is achieved by heating silicon wafers in an oxidizing atmosphere, such as
oxygen or water vapor.
ˆ The process consumes silicon and results in an SiO2 layer that expands in both vertical
directions.
ˆ The two common oxidation methods are:
1. Wet Oxidation:
– Uses an oxidizing atmosphere containing water vapor.
– Operates at 900 ◦ C to 1000 ◦ C.
– Provides a faster oxidation rate.
2. Dry Oxidation:
– Uses pure oxygen as the oxidizing agent.
– Requires higher temperatures (1200 ◦ C) for acceptable growth rates.
– Produces a denser and higher-quality oxide layer.

1.3.2 Oxide Growth

ˆ Since SiO2 has roughly twice the volume of the consumed silicon, the oxide layer grows
almost equally above and below the original silicon surface.
ˆ This effect is illustrated in n-channel MOS devices, where the field oxide projects in both
directions.

Figure 2: An nMOS transistor showing the growth of field oxide in both vertical directions

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VLSI Design and Testing 1 Silicon Semiconductor Technology

1.4 Selective Diffusion

ˆ Selective diffusion is a process used to introduce controlled amounts of donor or acceptor
impurities into specific areas of a silicon wafer.
ˆ The ability of silicon dioxide (SiO2 ) to act as a diffusion barrier allows precise patterning of
doped regions.
ˆ Selective diffusion involves the following steps:

– Opening windows in an SiO2 layer grown on the wafer surface.

– Removing SiO2 selectively using a suitable etching technique.
– Exposing the silicon to a controlled dopant source to alter its electrical properties.

1.4.1 Photolithography and Etching

The removal of SiO2 is achieved using a process called photolithography, which involves:
ˆ Coating the wafer with a photosensitive resist (PR).

ˆ Exposing PR to ultraviolet (UV) light through a patterned mask.

ˆ Developing the PR to remove unpolymerized areas.

ˆ Etching away the exposed SiO2 , allowing selective diffusion of dopants.

Conventional UV-based lithography limits feature sizes to about 1.5 µm to 2 µm due to diffraction
effects.

Figure 3: Simplified steps involved in the patterning of Si02

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VLSI Design and Testing 1 Silicon Semiconductor Technology

1.4.2 Electron Beam Lithography (EBL)

Electron beam lithography (EBL) has emerged as a more precise technique, achieving line
widths of approximately 0.5 µm. Key advantages of EBL include:
ˆ Direct patterning from digital data without masks.
ˆ High flexibility, allowing different patterns in different wafer regions.
ˆ Quick modifications to design layouts.
However, EBL has limitations, including high equipment costs and long processing times,
which restrict its commercial adoption.

1.4.3 Conclusion
Selective diffusion, enabled by SiO2 masking, is a crucial step in semiconductor fabrication. While
traditional photolithography remains dominant, EBL offers higher resolution at the cost of
speed and expense.

1.5 The Silicon Gate Process

ˆ In addition to single-crystal silicon and silicon dioxide (SiO2 ), polysilicon (polycrystalline
silicon) plays a crucial role in semiconductor fabrication.
ˆ It is used as:
– An interconnect in integrated circuits.
– The gate electrode in MOS transistors.
ˆ The self-aligned nature of polysilicon gates enables precise definition of source and drain
regions, improving circuit performance.

1.5.1 Steps in the Silicon Gate Process

The silicon gate process involves multiple cycles of photomasking and oxide etching, as
illustrated in figure below.

Step 1: Field Oxide Formation

A thick layer of SiO2 (field oxide) is grown over the wafer surface. This oxide is selectively etched
in areas where transistors will be placed.

Step 2: Gate Oxide Growth

A thin, controlled layer of SiO2 , called the gate oxide, is grown on the exposed silicon surface.
This serves as the insulating layer beneath the polysilicon gate.

Step 3: Polysilicon Deposition

A layer of undoped polysilicon is deposited across the wafer. This layer is later etched to form
transistor gates and interconnections.

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VLSI Design and Testing 1 Silicon Semiconductor Technology

Figure 4: Fabrication steps for a silicon gate nMOS transistor

Step 4: Dopant Diffusion

The wafer is exposed to a dopant source, leading to:

ˆ Formation of source and drain junctions in the silicon substrate.

ˆ Doping of polysilicon, reducing its resistivity.

The polysilicon gate acts as a mask, ensuring that the source and drain regions do not extend
beneath it. This self-aligned process enhances device performance.

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VLSI Design and Testing 2 CMOS Technologies

Step 5: Final Processing

ˆ The structure is covered with an SiO2 layer.

ˆ Contact holes are etched for electrical connections.

ˆ A metallic layer (e.g., aluminum) is deposited and etched to complete the circuit.

1.5.2 Conclusion
ˆ The silicon gate process enables precise control over MOS transistor fabrication.

ˆ The use of polysilicon as a gate material allows for self-aligned diffusion, reducing overlap
capacitance and improving circuit speed.

2 CMOS Technologies
2.1 The p-well process
ˆ CMOS (Complementary Metal-Oxide-Semiconductor) technology is a fundamental building
block in modern VLSI (Very Large-Scale Integration) circuits.

ˆ Among the various CMOS fabrication techniques, the p-well process is a widely used
method.

ˆ In this approach, a moderately doped n-type substrate (wafer) is used as the starting
material.

ˆ A p-type well is created in this substrate to accommodate the n-channel MOS transistors,
while the native n-type substrate is used for fabricating p-channel MOS transistors.

ˆ This process allows for the integration of both n-channel and p-channel transistors on the
same wafer, enabling complementary circuit operation.

ˆ The fabrication of CMOS devices involves multiple steps, including photolithography,

diffusion, ion implantation, oxidation, and metallization.

Step 1: P-Well Formation

ˆ The first step involves defining the p-well region using a photolithographic mask.

ˆ The field oxide (FOX) is etched away in the designated p-well regions.

ˆ A deep diffusion or ion implantation process introduces p-type dopants (typically boron) into
the n-type substrate.

ˆ The depth and concentration of the p-well must be carefully controlled, as they influence the
threshold voltage and breakdown voltage of the nMOS transistors.

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VLSI Design and Testing 2 CMOS Technologies

Figure 5: P-Well Formation

Step 2: Thin Oxide Growth

ˆ A thin, high-quality silicon dioxide (SiO2 ) layer is thermally grown on the exposed silicon
surface.

ˆ This oxide layer acts as the gate insulator for MOS transistors.

ˆ The thickness of this layer is crucial for transistor performance and determines the gate
capacitance.

Figure 6: Thin Oxide Growth

Step 3: Polysilicon Gate Formation

ˆ A layer of polycrystalline silicon (polysilicon) is deposited over the entire wafer.

ˆ This layer serves as the gate electrode for MOS transistors.

ˆ Using photolithography and etching, the polysilicon is patterned to define transistor gates and
interconnections.

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VLSI Design and Testing 2 CMOS Technologies

Figure 7: Polysilicon Gate Formation

Step 4: Source and Drain Implantation

ˆ A p-plus (p+ ) mask is used to define regions where p-type dopants will be implanted.

ˆ In the absence of the p+ mask, the remaining thin oxide areas are doped with n-type
impurities, forming n+ regions.

ˆ These diffusion regions serve as the source and drain terminals for nMOS and pMOS
transistors.

ˆ The polysilicon gate acts as a mask, ensuring precise alignment of source and drain regions,
which is known as the self-aligned process.

Figure 8: Source and Drain Implantation

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Step 5: Oxide Deposition and Contact Formation

ˆ A thick insulating layer of silicon dioxide (SiO2 ) is deposited over the entire wafer.

ˆ Photolithography is used to etch contact holes in the oxide layer, exposing selected diffusion
and polysilicon regions.

Figure 9: Oxide Deposition and Contact Formation

Step 6: Metallization
ˆ A thin layer of aluminum or another conductive metal is deposited over the wafer.

ˆ The metal layer is patterned and etched to form interconnections between various circuit
elements.

Figure 10: Metallization

Step 7: Passivation and Final Processing

ˆ A protective passivation layer (such as silicon nitride) is deposited to shield the circuit from
contamination and environmental damage.

ˆ Openings are etched to allow external connections to bonding pads.

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Substrate and Well Connections

Proper biasing of the substrate and well is essential to ensure correct circuit operation and prevent
unwanted effects like latch-up. The connections are as follows:
ˆ The p-well is connected to the negative supply voltage (VSS or ground).

ˆ The n-substrate is connected to the positive supply voltage (VDD ).

ˆ Substrate contacts help minimize parasitic resistance and improve circuit reliability.

Figure 11: p-well substrate contacts: (a) Substrate and Well Connections, (b) Corresponding Layout

2.1.1 Advanced P-Well Processes

1. Retrograde P-Well Process
To overcome limitations of conventional p-well diffusion, an advanced technique called the
retrograde p-well process is used. In this method:
ˆ High-energy boron implantation is used instead of thermal diffusion.

ˆ The implanted dopants remain at a controlled depth, reducing lateral diffusion.

ˆ This enables smaller transistor spacing, improving packing density.

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ˆ Junction depth, sheet resistance, and threshold voltage can be independently controlled.

Figure 12: GE-1ntersil’s “retrograde p-well” process

2. CMOSC Process
The CMOSC process is another enhancement of the p-well CMOS technology. Key features
include:

ˆ Boron implants define p-channel transistors.

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ˆ Phosphorus implants define n-channel transistors.

ˆ Improved control over lateral diffusion reduces leakage currents.

ˆ Enhanced field oxide processing minimizes thinning effects (such as bird’s beak ).

Figure 13: Hewlett- Packard’s CMOSC process

2.1.2 Challenges and Considerations

While the p-well CMOS process offers a practical approach for integrating nMOS and pMOS
transistors, it has some challenges:
ˆ Threshold Voltage Control: P-well doping concentration must be carefully optimized to
achieve the desired threshold voltages.

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ˆ Parasitic Capacitance: The n-transistors in the p-well experience higher source/drain

capacitance, which can affect switching speed.

ˆ Latch-Up Prevention: Proper well connections and substrate contacts are necessary to
prevent latch-up, which can cause circuit failure.

ˆ Area Considerations: The required spacing between p- and n-transistors can increase chip
area, affecting integration density.

2.2 The n-well process

ˆ The n-well process is one of the most commonly used CMOS fabrication techniques.

ˆ It has largely replaced the p-well process due to its compatibility with existing nMOS process
lines, allowing manufacturers to transition from nMOS to CMOS technology efficiently.

ˆ The key advantage of the n-well process is that it enables the integration of both n-channel
and p-channel MOSFETs on a p-type substrate.

ˆ The pMOS transistors are placed within the n-well region, ensuring better noise immunity and
reducing substrate bias effects compared to a single-well approach.

2.2.1 Fabrication Steps of the n-Well CMOS Process

Step 1: Substrate Preparation
ˆ A p-type silicon substrate is used as the base material.

ˆ A thin oxide layer is grown to protect the silicon surface.

Step 2: n-Well Formation

ˆ An n-well mask defines the well regions.

ˆ A phosphorus implant introduces n-type dopants.

ˆ A high-temperature diffusion step ensures proper well depth and uniformity.

Figure 14: n-Well Formation

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Step 3: Active Area Definition

ˆ Field oxide is removed from transistor regions.

ˆ The oxide thickness is adjusted for device isolation.

Step 4: Threshold Voltage Adjustment

ˆ A light p-type doping step adjusts the threshold voltage of transistors.

Step 5: Polysilicon Gate Formation

ˆ A thin oxide layer is grown as gate oxide.

ˆ Polysilicon is deposited, patterned, and etched to form gates.

Figure 15: Polysilicon Gate Formation

Step 6: Source and Drain Formation

ˆ Arsenic (n-type) is implanted for n-channel source and drain.

ˆ Boron (p-type) is implanted for p-channel source and drain.

Step 7: Contact and Metallization

ˆ Contact openings are etched to expose terminals.

ˆ Aluminum is deposited and patterned for interconnections.

Figure 16: Contact and Metallization

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2.2.2 Key Characteristics of the n-Well Process

ˆ pMOS Transistors in n-Well

– p-channel transistors are isolated within the n-well, preventing unwanted interactions
with the p-substrate.
– However, pMOS devices suffer from increased body effect, requiring careful design.

ˆ nMOS Transistors in p-Substrate

– n-channel transistors are directly fabricated in the p-type substrate.

– They exhibit higher electron mobility, leading to faster switching speeds.

2.2.3 Comparison of n-Well and p-Well CMOS Processes

Table 1: Comparison of n-Well and p-Well CMOS Processes

Feature n-Well CMOS p-Well CMOS

Substrate Type p-Type n-Type
Well Type n-Well p-Well
pMOS Location Inside n-Well Directly in n-Substrate
nMOS Location Directly in p-Substrate Inside p-Well
Advantages Compatible with nMOS processes, Lower junction capacitance for pMOS
better noise isolation
Disadvantages Higher body effect for pMOS Requires additional processing for
nMOS
2.2.4 The Berkeley n-Well Process
ˆ The Berkeley n-well CMOS process is often described using the Process Input Description
Language (PIDL), which defines key fabrication steps.

ˆ Some important commands used in PIDL include:

Table 2: Process Input Description Language commands.

Command Function
SUBSTRATE Defines the substrate type and impurity level.
OXIDE Specifies oxide thickness.
DEPOSITION Deposits material layers.
ETCH Removes material to a specified depth.
DOPE Introduces dopants to control electrical properties.
MASK Defines patterned regions for processing.

For instance, polysilicon gate formation involves:

1. Depositing 0.3 µm of polysilicon: DEPO POLY THICK=0.30.

2. Applying a resist layer: DEPO RST THICK=0.5.

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3. Using a mask to define the gate: MASK RST DRST MSI POSI.

4. Etching the exposed polysilicon: ETCH POLY DEPTH=0.6.

5. Removing the resist, leaving the polysilicon gate.

2.3 The Twin-Tub Process

2.3.1 Introduction
ˆ CMOS technology has evolved through various fabrication techniques to improve performance
and design flexibility.

ˆ One such advancement is the Twin-Well or Twin-Tub CMOS Process, which enables
independent optimization of both p-type and n-type transistors.

ˆ This process allows the threshold voltage, body effect, and gain associated with n-channel and
p-channel transistors to be individually optimized, leading to improved circuit performance.

2.3.2 Key Features of the Twin-Well Process

The Twin-Tub process offers several advantages over the conventional p-well process:
ˆ Independent Optimization: The twin-tub approach allows separate control of p-well and
n-well properties, leading to better transistor performance.

ˆ Threshold Voltage Control: The use of separate wells makes it possible to fine-tune the
threshold voltages of both p-type and n-type MOSFETs.

ˆ Improved Body Effect and Gain: The body effect, which influences the threshold voltage,
can be optimized separately for nMOS and pMOS transistors.

ˆ Reduced Latch-up Susceptibility: The process starts with an epitaxial silicon layer to
enhance latch-up immunity by isolating the wells from the substrate.

2.3.3 Process Sequence

ˆ The fabrication sequence of the Twin-Tub CMOS process is similar to the p-well process, with
the key difference being that both p-well and n-well regions are formed independently to
achieve the desired electrical properties.

ˆ The key steps are as follows:

1. Substrate Preparation:

ˆ A lightly doped silicon wafer (typically p-type) is used as the starting material.
ˆ A thin oxide layer is grown to serve as a protective layer.
ˆ An epitaxial silicon layer is deposited to improve performance and minimize latch-up
issues.

2. Twin-Tub Formation:

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ˆ Both p-well and n-well are created by selective ion implantation.

ˆ The process allows separate optimization of the electrical properties of p-channel and
n-channel MOSFETs.

3. Threshold Voltage Adjustment:

ˆ A threshold adjustment implant is introduced to control the transistor threshold voltages.

4. Field Oxidation and Isolation:

ˆ Field oxide is grown to isolate different transistor regions.

ˆ LOCOS (Local Oxidation of Silicon) may be used to create field oxide regions.

5. Polysilicon Deposition and Gate Formation:

ˆ A thin gate oxide layer is thermally grown.

ˆ Polysilicon is deposited and patterned to form the gate electrode.

6. Source and Drain Implantation:

ˆ Arsenic (n-type) is implanted into the p-well to form nMOS source and drain.
ˆ Boron (p-type) is implanted into the n-well to form pMOS source and drain.

7. Contact Cut Definition:

ˆ Openings are etched to allow metal contacts to connect to the source, drain, and gate
terminals.

8. Metallization:

ˆ Metal layers (usually aluminum) are deposited and patterned to create interconnections.
ˆ A passivation layer is deposited for protection.

2.3.4 Advantages of the Twin-Tub Process

ˆ Independent Optimization: The electrical characteristics of nMOS and pMOS transistors
can be separately optimized, unlike the p-well or n-well processes.

ˆ Enhanced Performance: Since both n-well and p-well are present, better control of
parameters such as threshold voltage, body effect, and gain is possible.

ˆ Improved Latch-up Immunity: The epitaxial layer provides additional isolation, reducing
latch-up issues.

2.3.5 Illustration of the Twin-Tub Process

The figure below illustrates the process steps involved in the AT&T-Bell Laboratories twin-tub
process.

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MASK 1 (WELL DEFINITION) WELL REGIONS ARE DEFINED

n-WELL IS IMPLANTED AND SELECTIVELY OXIDIZED

P-WELL IS IMPLANTED

(WELL FORMATION) n-WELL FORMATION (≈ 5µm DEEP)

p-WELL FORMATION (≈ 5µm DEEP)

FIELD - OXIDATION (≈ 1µm THICK)

THICK FIELD OXIDE IS NONSELECTIVELY IMPLANTED WITH

ARGON TO GENERATE A FAST ETCHING SURFACE LAYER

FIELD OXIDE IS ETCHED TO DEFINE THE AREAS

MASK 2 (THINOX DEFINITION)
WHERE GATE OXIDE IS REQUIRED TO BE GROWN

FORMATTON OF GATE OXIDE(≈ 500 Å)

THRESHOLD ADJUSTMENT OF FUTURE p-CHANNEL

MASK 3
DEVICES BY SELECTIVE IMPLANTATION OF BORON

POLYSILICON DEPOSITION

MASK 4 (POLYSILICON PATTERNING) POLYSILICON iS PATTERNED

BORON IMPLANT FOR FORMATION OF p+ REGIONS

MASK 5 PHOSPHOROUS IS IMPLANTED FOR FORMATION OF n+ REGONS

PASSIVATION

MASK 6 CONTACT CUT

ALUMINIUM DEPOSITED OVER THE WHOLE OF WAFER

MASK 7 PATTERNING OF ALUMINIUM

MASK 8 CUTS FOR BONDING PADS

Figure 17: AT&T Bell Laboratories’ twin-tub CMOS process steps

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2.3.6 Final Structure

The figure below presents the final twin-tub CMOS structure, highlighting the independently
optimized p-well and n-well regions, including the required substrate contacts.

Figure 18: Twin-tub process cross-section and layout of an inverter

2.3.7 Conclusion
ˆ The twin-tub CMOS process offers significant advantages over the conventional p-well process.

ˆ The independent formation of p-well and n-well allows better control over transistor
parameters such as threshold voltage, gain, and body effect.

ˆ Moreover, the inclusion of an epitaxial layer enhances the process by improving latch-up
immunity, making the twin-tub process ideal for high-performance CMOS applications.

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2.4 Silicon on Insulator (SOI) CMOS Technology

2.4.1 Introduction
ˆ Silicon on Insulator (SOI) CMOS technology is an advanced fabrication process that offers
several advantages over traditional bulk silicon CMOS technologies.

ˆ These advantages include higher device density, elimination of latch-up problems, and reduced
parasitic capacitances.

2.4.2 SOI CMOS Process Steps

1. Substrate Preparation:

ˆ A thin layer (7–8 µm) of lightly doped n-type silicon is epitaxially grown on an insulating
substrate, such as sapphire.

Figure 19: Substrate Preparation

2. Island Formation:

ˆ An anisotropic etch is used to remove silicon except in areas where diffusion regions (n or
p) are needed.
ˆ This creates isolated silicon “islands” for device formation.

Figure 20: Island Formation

3. Doping for p-Islands:

ˆ The n-islands are masked with photoresist, and a p-type dopant (e.g., boron) is
implanted to form p-islands.
ˆ These p-islands will become the n-channel devices.

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Figure 21: Doping for p-Islands

4. Doping for n-Islands:

ˆ The p-islands are masked, and an n-type dopant (e.g., phosphorus) is implanted to form
n-islands.
ˆ These n-islands will become the p-channel devices.

Figure 22: Doping for n-Islands

5. Gate Oxide Formation:

ˆ A thin gate oxide (500–600 Å) is grown over the silicon structures using thermal
oxidation.

Figure 23: Gate Oxide Formation

6. Polysilicon Deposition:

ˆ A polysilicon film is deposited over the oxide and doped with phosphorus to reduce
resistivity.
ˆ The polysilicon is then patterned and etched to define the gate regions.

Figure 24: Polysilicon Deposition

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7. Source/Drain Formation for n-Channel Devices:

ˆ The n-islands are masked, and an n-type dopant (e.g., phosphorus) is implanted to form
the source and drain regions of the n-channel devices.
ˆ The polysilicon gate blocks dopant implantation in the gate region.

Figure 25: Source/Drain Formation for n-Channel Devices

8. Source/Drain Formation for p-Channel Devices:

ˆ The p-islands are masked, and a p-type dopant (e.g., boron) is implanted to form the
source and drain regions of the p-channel devices.
ˆ The polysilicon gate blocks dopant implantation in the gate region.

Figure 26: Source/Drain Formation for p-Channel Devices

9. Insulator Deposition and Metallization:

ˆ A layer of phosphorus glass or silicon dioxide is deposited over the structure.

ˆ Contact cuts are etched, and aluminum is evaporated and patterned to form
interconnects.

Figure 27: Insulator Deposition and Metallization

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10. Passivation:

ˆ A final passivation layer of phosphorus glass is deposited and etched over bonding pad
locations.

2.4.3 Advantages of SOI Technology

ˆ Higher Density: The absence of wells allows for denser device structures compared to bulk
silicon. Direct n-to-p connections are also possible.

ˆ Lower Parasitic Capacitances: The insulating substrate reduces parasitic junction

capacitances, enabling faster circuit operation.

ˆ No Latch-Up: The isolation of n- and p-transistors by the insulating substrate eliminates

latch-up issues.

ˆ No Field-Inversion Problems: The insulating substrate prevents field-inversion problems

common in bulk silicon.

ˆ No Body Effect: The absence of a conducting substrate eliminates body effect problems.

ˆ Enhanced Radiation Tolerance: SOI devices are more resistant to radiation, making them
suitable for aerospace and high-radiation environments.

2.4.4 Challenges of SOI Technology

ˆ Input Protection: The absence of substrate diodes makes input protection more challenging.

ˆ Lower Device Gains: Device gains are lower, requiring larger I/O structures.

ˆ Higher Cost: Single crystal sapphire or spinel substrates are significantly more expensive
than silicon.

ˆ Less Developed Processing Techniques: SOI processing techniques are less mature
compared to bulk silicon, leading to higher complexity and cost.

ˆ Preferential Etch Requirements: To improve yield, preferential etching is often used to

taper island edges, adding complexity to the process.

2.4.5 Comparison of Etch Techniques

ˆ Isotropic Etch: Creates rounded sidewalls but is less precise for dense structures.

ˆ Anisotropic Etch: Produces vertical sidewalls with no undercut, but can create high step
heights for metal or polysilicon runners.

ˆ Preferential Etch: Tapers island edges to minimize step heights, improving yield and ease of
metallization.

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VLSI Design and Testing 3 Layout Design Rules

Figure 28: Classification of etching process

2.4.6 Conclusion
ˆ SOI CMOS technology offers significant performance advantages, including higher speed, lower
power consumption, and enhanced radiation tolerance.

ˆ However, its higher cost and processing complexity have limited its widespread adoption.

ˆ Despite these challenges, SOI remains a promising technology for high-performance and
specialized applications, such as aerospace, military, and high-speed computing.

3 Layout Design Rules

3.1 Introduction
ˆ Layout design rules, also known as design rules, serve as guidelines for preparing the
photomasks used in the fabrication of integrated circuits (ICs).

ˆ These rules act as a critical communication bridge between the circuit designer and the
process engineer, ensuring that the manufacturing process is both efficient and reliable.

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VLSI Design and Testing 3 Layout Design Rules

ˆ The primary objective of layout design rules is to achieve the highest possible yield while
maintaining a compact geometry without compromising circuit reliability. A trade-off exists:

– Conservative rules ⇒ Higher reliability but may limit performance.

– Aggressive rules ⇒ Potential performance gains but may reduce fabrication yield.

3.1.1 Purpose of Design Rules

Design rules define geometric constraints for layout artwork, ensuring that the processed wafer
maintains the intended topology and geometry of the design. It is important to note:
ˆ Design rules do not represent a strict boundary between correct and incorrect fabrication.

ˆ A layout that violates some design rules may still function, but frequent violations increase the
risk of fabrication failures.

3.1.2 Key Design Rule Constraints

Two critical aspects of design rules include:
1. Line Widths:

ˆ Too narrow: May cause discontinuities, leading to circuit failure.

ˆ Too close: Can result in short circuits between adjacent conductive paths.

2. Interlayer Registration:

ˆ Ensures proper alignment between different material layers in the fabrication process.
ˆ Incorrect spacing between layers can cause electrical and manufacturing defects.

3.1.3 Types of Design Rules

Several approaches exist for defining design rules:
1. Micron-Based Rules:

ˆ Specifies minimum feature sizes and spacings in absolute micron values (e.g.,
minimum thinox width = 4 µm).
ˆ Commonly used in industrial fabrication processes.

2. Alpha (α) and Beta (β) Rules:

ˆ Uses β as a reference for feature sizes and α as the minimum required grid spacing.
ˆ These parameters are related by a constant factor.

3. Lambda (λ)-Based Rules:

ˆ Introduced by Mead and Conway, lambda-based rules use a single parameter (λ) to
define all feature sizes.
ˆ Enables scaling of circuit layouts across different technology nodes.

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VLSI Design and Testing 3 Layout Design Rules

ˆ Allows rules to be expressed compactly, often on a single page.

ˆ However, λ-based scaling is only an approximation and may not be suitable for
commercial circuits.

3.1.4 Derivation of Lambda-Based Rules

A representative example of how lambda (λ)-based rules are derived from micron-based rules is
shown in table below.
Table 3: Derivation of Lambda-Based Rules from Micron Rules

Mask Feature Micron Rule (µm) Lambda Rule (λ)

Thinox Minimum thinox width 4µm 2λ
Minimum thinox spacing 4µm 2λ
Minimum p-thinox to n-thinox spacing 8µm 4λ
Polysilicon Minimum poly width 3.75µm 2λ
Minimum poly spacing 3.75µm 2λ
Minimum gate poly width (p) 4.5µm 3λ
Minimum gate poly width (n) 4µm 2λ
Minimum gate poly extension 3.5µm 2λ
Aluminum Minimum Al width 4.5µm 3λ
Minimum Al spacing 4.5µm 3λ

3.1.5 Practical Considerations

ˆ Deviating from design rules may not always lead to failure, but frequent violations
increase the likelihood of fabrication issues.

ˆ While λ-rules offer a simplified abstraction, modern symbolic techniques allow designers to
work without worrying about the specifics of design rules.

3.2 Layer Representations in CMOS Processes

3.2.1 Introduction
ˆ The advances in CMOS fabrication processes have made them increasingly complex, making it
difficult to visualize all the mask levels involved in actual IC fabrication.

ˆ However, the design process can be abstracted into a manageable number of conceptual
layout levels, which represent the physical features observed in the final silicon wafer.

ˆ At a sufficiently high conceptual level, all CMOS processes include the following features:

– Two different substrates

– Doped regions forming both p- and n-transistors

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VLSI Design and Testing 3 Layout Design Rules

– Transistor gate electrodes

– Interconnection paths
– Interlayer contacts

3.2.2 Layer Representations

Different representation techniques are used to depict various layers in CMOS processes. These
techniques include:

ˆ A color scheme proposed by JPL

ˆ A modified color scheme distinguishing between nMOS and CMOS structures

ˆ Stipple patterns

ˆ Line styles

ˆ A combination of the above

Some of these representations are illustrated in following tables.

1. JPL and Mead-Conway Layer Representation

Table 4: JPL/Mead-Conway Layer Representation for p-well CMOS Process

Layer JPL Color Symbolic Rep- Comments

resentation
p-well Brown - Inside brown is p-well, out-
side is n-type substrate
Thin oxide Green n-transistor Thin oxide may not cross a
well boundary
Poly Red Polysilicon Generally n
p Yellow p-transistor Inside is p
Metal1 Light blue Metal1 -
Metal2 Dark blue Metal2 -
Contact cut Black Contact -
Overglass - - -

2. Alternate Layer Representations

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VLSI Design and Testing 3 Layout Design Rules

Table 5: Alternate Layer Representations for p-well CMOS Process

Layer Alternate Color CIF Code

p-well Brown CW
Thin oxide Red CD
Poly Green CP
p Purple CS
Metal1 Tan CM
Metal2 Dark blue CN
Contact Black CC
Overglass white stipples CG

3. CIF Representation of Process Descriptions

ˆ The CIF (Caltech Intermediate Form) layer names used by JPL for bulk CMOS are presented
in table below.

ˆ CIF version 2.0 uses up to four alphanumeric characters to describe a mask level.

ˆ The first letter represents the process class (e.g., ’C’ for bulk CMOS), followed by a second
character identifying the layer type.

Table 6: First Character Representation of CIF for Process Description

Process CIF Character

n-channel MOS N
p-channel MOS P
Bulk CMOS processes C
Silicon-on-Insulator (SOI) processes S

Mask Levels in CMOS and SOI Processes

ˆ In n-well bulk CMOS, the only difference from p-well CMOS is the reversal of well and
original substrate roles.

ˆ Different process lines may use different combinations of n-well, p-well, or twin-tub masks
to define the process.

ˆ Understanding the specific set of masks used in a process is crucial when designing interface
formats.

ˆ For example, an n-mask (reverse of a p-mask) may be used to denote n-transistors.

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VLSI Design and Testing 3 Layout Design Rules

SOI vs. Bulk CMOS

ˆ The mask levels in Silicon-on-Insulator (SOI) processes are conceptually simpler.

ˆ The visible geometry corresponds directly to the design features, such as n-regions and
p-regions.

ˆ The key difference between SOI and bulk CMOS is the absence of wells in SOI.

The Role of Symbolic Design

ˆ To simplify bulk CMOS design, symbolic-level representations are encouraged.

ˆ This approach allows designers to manipulate n- and p-transistors directly without

worrying about specific design rules.

ˆ The benefits of symbolic design include:

– Eliminating the need for explicit layout design rules.

– Enabling the next generation of automatically performance-optimized circuits.

3.3 Lambda-based p-well rules

To standardize layout design, lambda-based rules define:

ˆ Minimum feature sizes.

ˆ Spacing requirements.

ˆ Overlap constraints.

Table below summarizes the lambda-based layout rules for the p-well process.

Table 7: Lambda-based layout rules

NO. MASK FEATURE DIMENSION

1 Thinox A1. Minimum thinox width 2λ
A2. Minimum thinox spacing n+ /p+ to n+ /p+ 2λ
A3. Minimum p-thinox to n-thinox spacing 8λ
2 p-well B1. Minimum p-well width 4λ
B2. Minimum p-well spacing (wells at same potential) 2λ
B3. Minimum p-well spacing (wells at different potential) 6λ
B4. Minimum distance to internal thinox 3λ
B5. Minimum distance to external thinox 5λ
Continued on next page

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VLSI Design and Testing 3 Layout Design Rules

Continued from previous page

NO. MASK FEATURE DIMENSION
3 Poly C1. Minimum poly width 2λ
C2. Minimum poly spacing 2λ
C3. Minimum poly to thinox spacing λ
C4. Minimum poly gate extension 2λ
C5. Minimum thinox source/drain extension 2λ
4 p-plus D1. Minimum overlap of thinox 1.5 - 2λ
D2. Minimum p-plus spacing 2λ
D3. Minimum gate overlap or distance to gate edge 1.5 - 2λ
D4. Minimum spacing to unrelated thinox 1.5 - 2λ
5 Contact E1. Minimum contact area 2λ × 2λ
E2. Minimum contact to contact spacing 2λ
E3. Minimum overlap of thinox or poly over contact λ
E4. Minimum spacing to gate poly 2λ
E5. n- source/drain contact
E6. p- source/drain contact
E7. VSS contact
E8. VDD contact
E9. Split contact VSS
E10. Split contact VDD
6 Metal F1. Minimum metal width 2-3λ
F2. Minimum metal spacing 3λ
F3. Minimum metal overlap of contact λ

Note: For E5 - E10, See the pictorial representation shown in following section.

3.3.1 Pictorial Representations

Figure 29: Mask 1: Thinox

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VLSI Design and Testing 3 Layout Design Rules

Figure 30: Mask 2: p-well

Figure 31: Mask 3: Polysilicon

Figure 32: Mask 4: p - plus

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VLSI Design and Testing 3 Layout Design Rules

Figure 33: Mask 5: Contact

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VLSI Design and Testing 3 Layout Design Rules

Figure 34: Mask 6: Metal

3.3.2 Key Considerations

1. Well Spacing and Separation
ˆ The p-well is a deep diffusion requiring sufficient spacing to prevent electrical shorts.

ˆ The inside clearance must account for field oxide transitions across the well boundary.

ˆ The thin oxide layer should not cross a well boundary to prevent electrical shorts.

2. Transistor Layout Rules

ˆ The source and drain diffusion is self-aligned to the gate using the poly region.

ˆ The gate extension must be at least 1.5–2λ beyond the diffusion edge.

ˆ Thin oxide regions not forming a transistor should be kept separated by 0.5–1λ.

3. Contact Design in CMOS Layout

There are several types of contacts:

ˆ Metal-to-diffusion (n or p).

ˆ Metal-to-polysilicon.

ˆ VDD . and VSS . substrate contacts.

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VLSI Design and Testing 3 Layout Design Rules

ˆ Split (merged) contacts for better conductivity.

Each well must be tied to the correct supply voltage:

ˆ p-well → VSS .

ˆ n-well → VDD .

4. Poly Doping Considerations

ˆ In p-well CMOS processes, poly is usually doped n-type.

ˆ Doping variations can increase poly sheet resistance.

5. Guard Rings for Noise Isolation

ˆ Guard rings collect injected minority carriers.

ˆ p+ guard rings in the n-substrate are tied to VSS .

ˆ n+ guard rings in the p-well are tied to VDD .

3.4 Lambda-Based SOI Rules

ˆ Table below presents a set of lambda rules for CMOS SOI technology.

ˆ An interesting aspect of these rules is that, apart from a few exceptions such as the n-device
to n-device spacing rule, implant rules, metal-to-metal spacing rule, and contact
rules, most of the layout constraints follow a consistent scaling factor.

ˆ The primary value that designers need to keep in mind is 2λ.

ˆ One significant application of the 2λ spacing rule is to ensure sufficient separation between the
island edge and unrelated polysilicon.

ˆ This rule is crucial in preventing electrical shorts between polysilicon and island edges, which
could occur due to thin or faulty oxide coverage over the islands.

Table 8: Lambda-Based Layout Rules for SOI

NO. MASK FEATURE DIMENSION

1 Island Minimum island width 2λ
p-device to n-device spacing 2λ
n-device to n-device spacing 3λ
p-device to p-device spacing 3λ
2 Implant Implant/island overlap λ
Implant/island spacing λ
Continued on next page

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VLSI Design and Testing 3 Layout Design Rules

Continued from previous page

NO. MASK FEATURE DIMENSION
3 Poly Minimum poly width 2λ
Minimum poly-poly spacing 2λ
Minimum poly to island 2λ
Minimum island edge to poly spacing 2λ
Minimum poly extension over island 2λ
4 Contact Distance over poly edge λ
Distance over island edge λ
Distance from island edge λ
Distance from non-contacted feature 2λ
Contact width on island 2λ
Contact width on poly 2λ
5 Metal Minimum metal width 3λ
Minimum metal spacing 2λ
Minimum metal overlap of contact λ

ˆ These lambda-based rules offer a systematic approach to SOI layout design, ensuring proper
electrical isolation and manufacturability.

ˆ The 2λ rule for poly-to-island edge separation is especially important to prevent electrical
shorts due to fabrication imperfections.

3.4.1 Pictorial Representation

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VLSI Design and Testing 3 Layout Design Rules

Figure 35: Lambda - based rules for SOI

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VLSI Design and Testing 3 Layout Design Rules

3.5 Double Metal Design Rules

ˆ In modern VLSI design, the use of multiple metal layers improves routing efficiency and
enhances signal integrity.

ˆ The second metal layer (Metal2) works in conjunction with the first metal layer (Metal1) to
provide additional connectivity.

ˆ However, specific design rules must be followed to prevent issues such as broken conductors or
shorts due to the vertical topology.

ˆ Tables below present typical rules for the interaction between Metal2 and Metal1 in a
two-layer metal process.

ˆ The increased width and separation requirements for Metal2 ensure robustness against process
variations, reducing the likelihood of open circuits and unintended shorts between adjacent
wires.

Table 9: Double Metal Rules - Micron-Based (Suggested Lambda Rules)

Layer Width Spacing

Metal1 3 µm (2λ) 4 µm (3λ)
Metal2 5 µm (4λ) 5 µm (4λ)
Via 3 µm × 3 µm (2λ × 2λ) 3 µm (2λ)
Cut 3 µm × 3 µm (2λ × 2λ) 3 µm (2λ)
Cut-Via space - 3 µm (2λ)

Table 10: Metal1, Metal2, and Via Constructs

Layer Size
Metal 1 5µm × 5µm (4λ × 4λ)
Via 3µm × 3µm (2λ × 2λ)
Metal2 7µm × 7µm (5λ × 5λ)

ˆ The use of multiple metal layers enhances circuit performance and allows for higher routing
densities.

ˆ However, careful adherence to these design rules ensures that fabrication issues such as open
circuits and short circuits are minimized.

3.6 Design Rules — Summary

ˆ In commercial VLSI designs, lambda-based design rules are often insufficient to describe the
complexities of high-performance circuits.

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VLSI Design and Testing 3 Layout Design Rules

ˆ Additional rules are required to ensure manufacturability and performance optimization.

ˆ Some of the key additional rules found in advanced fabrication processes include:

1. Polysilicon Extension: The extension of polysilicon in the direction that metal wires
exit a contact.
2. Differing Gate Lengths: Variations in gate lengths between p-transistors and
n-transistors.
3. Gate Poly Extensions: Different gate poly extension lengths depending on the device
length or the device construction.

ˆ While it is possible to worst-case these rules, doing so often results in inefficient designs.

ˆ A more effective approach is to implement systems that automatically synthesize the correct
geometry from an intermediate design representation.

ˆ Symbolic design techniques provide a solution for developing generic CMOS circuits that can
be adapted to a wide range of fabrication processes.

ˆ Instead of relying solely on fixed design rules, these techniques allow for the abstraction of key
design constraints and the automated generation of optimized layouts.

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