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Interrupt of 8086 microprocessor_4

The document discusses the control signals and bus commands of the 8086 microprocessor, including the role of the 8288 and 8289 in bus arbitration and queue status signals. It also explains the concept of interrupts, detailing hardware and software interrupts, their types, and the interrupt vector table. Additionally, it outlines the performance of both hardware and software interrupts, including specific interrupt types and their associated functions.

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Ranju samanta
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2 views

Interrupt of 8086 microprocessor_4

The document discusses the control signals and bus commands of the 8086 microprocessor, including the role of the 8288 and 8289 in bus arbitration and queue status signals. It also explains the concept of interrupts, detailing hardware and software interrupts, their types, and the interrupt vector table. Additionally, it outlines the performance of both hardware and software interrupts, including specific interrupt types and their associated functions.

Uploaded by

Ranju samanta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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· In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.

· The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3
signals provide the same functions as those described for the minimum system mode.

· This set of bus commands and control signals is compatible with the Multibus
and industry standard for interfacing microprocessor systems.
· The output of 8289 are bus arbitration signals:

Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority
in (BPRN), bus request (BREQ) and bus clock (BCLK).

· They correspond to the bus exchange signals of the Multibus and are used to lock
other processor off the system bus during the execution of an instruction by the 8086.
· In this way the processor can be assured of uninterrupted access to common
system resources such as global memory.

· Queue Status Signals: Two new signals that are produced by the 8086 in the
maximum- mode system are queue status outputs QS0 and QS1. Together they form
a 2-bit queue status code, QS1QS0.
· Following table shows the four different queue status.

· Local Bus Control Signal – Request / Grant Signals: In a maximum mode


configuration, the minimum mode HOLD, HLDA interface is also changed

QS1 QS0 Queue Status


0 (Low) 0 Queue Empty. The queue has been reinitiated as a
result of the execution of a transfer instruction.
0 1 First Byte. The byte taken from the queue was the
first byte of the instruction.
1 0 Queue Empty. The queue has been reinitiated as a
result of the execution of a transfer instruction.
1 1 (High) Subsequent Byte. The byte taken from the queue
was the subsequent byte of the instruction.

· . These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1,
respectively. They provide a prioritized bus access mechanism for accessing the local
bus.

Interrupts

Definition: The meaning of ‘interrupts’ is to break the sequence of operation. While the CPU
is executing a program, on ‘interrupt’ breaks the normal sequence of execution of
instructions, diverts its execution to some other program called Interrupt Service Routine
(ISR).After executing ISR , the control is transferred back again to the main program.
Interrupt processing is an alternative to polling.
Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that
provide or require data at relatively low data transfer rate.
Types of Interrupts: There are two types of Interrupts in 8086. They
are: (i)Hardware Interrupts and
(ii)Software Interrupts

(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support


hardware interrupts through:

· Two pins that allow interrupt requests, INTR and NMI

· One pin that acknowledges, INTA, the interrupt requested on INTR.

INTR and NMI:


· INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled
using STI/CLI instructions or using more complicated method of updating the FLAGS
register with the help of the POPF instruction.

· When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps
to interrupt processing routine address of which is stored in location 4 * <interrupt
type>. Interrupt processing routine should return with the IRET instruction.

· NMI is a non-maskable interrupt. Interrupt is processed in the same way as the


INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing
routine is stored in location 0008h. This interrupt has higher priority than the maskable
interrupt.

· – Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be
caused by:
· INT instruction - breakpoint interrupt. This is a type 3 interrupt.
· INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
· INTO instruction - interrupt on overflow
· Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt
processing routine.

· Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape
opcode (type 7).

· Software interrupt processing is the same as for the hardware interrupts.

· - Ex: INT n (Software Instructions)

· Control is provided through:

o IF and TF flag bits

o IRET and IRETD


Performance of Software Interrupts

1. It decrements SP by 2 and pushes the flag register on the stack.


2. Disables INTR by clearing the IF.
3. It resets the TF in the flag Register.
5. It decrements SP by 2 and pushes CS on the stack.
6. It decrements SP by 2 and pushes IP on the stack.
6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Table

Functions associated with INT00 to INT04

INT 00 (divide error)

· INT00 is invoked by the microprocessor whenever there is an attempt to divide a


number by zero.
· ISR is responsible for displaying the message “Divide Error” on the screen
INT 01

· For single stepping the trap flag must be 1

· After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4


bytes for CS: IP of the ISR.

· The job of ISR is to dump the registers on to the screen

INT 02 (Non maskable Interrupt)

· When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps
to physical memory location 00008 to fetch CS:IP of the ISR associated with NMI.

INT 03 (break point)

· A break point is used to examine the CPU and memory after the execution of a group
of Instructions.

· It is one byte instruction whereas other instructions of the form “INT nn” are 2
byte instructions.

INT 04 (Signed number overflow)

· There is an instruction associated with this INT 0 (interrupt on overflow).

· If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU
will activate INT 04 if 0F = 1.

· In case where 0F = 0, the INT 0 is not executed but is bypassed and acts as a NOP.

Performance of Hardware Interrupts

· NMI : Non maskable interrupts - TYPE 2 Interrupt

· INTR : Interrupt request - Between 20H and FFH


Interrupt Priority Structure

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