IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

4, APRIL 2014 1799

Waveform Equations, Output Power, and Power

Conversion Efficiency for Class-E Inverter
Outside Nominal Operation
Tomoharu Nagashima, Student Member, IEEE, Xiuqin Wei, Member, IEEE, Tadashi Suetsugu, Senior Member, IEEE,
Marian K. Kazimierczuk, Fellow, IEEE, and Hiroo Sekiya, Senior Member, IEEE

Abstract—This paper presents analytical expressions for switching circuits. Most of these papers focused on the class-E
steady-state waveforms, output power, and power conversion ef- switching circuits satisfying the class-E zero-voltage switching
ficiency for the class-E inverter outside the class-E zero-voltage and zero-derivative switching (ZVS/ZDS) conditions, which
switching and zero-derivative switching conditions. The analytical
expressions in this paper include the MOSFET-body-diode effect.
are called “nominal conditions.” When considering the class-E
By carrying out PSpice simulations and circuit experiments, it is inverter applications, however, it is important to obtain the
shown that the analytical predictions agree with the simulated and analytical expressions of waveforms, output power, and power
experimental results quantitatively, which indicates the validity conversion efficiency outside nominal operation. For example,
of the analytical expressions. Additionally, the switching-pattern the inductive component of coupled coil pair varies drastically
distribution maps are also given by using the analytical waveform by changing the distance between primary coil and secondary
equations.
one in wireless power transfer applications [8]. The PWM-
Index Terms—Class-E inverter, class-E zero-voltage switching control class-E inverter [9] works at any duty ratio, which
and zero-derivative switching (ZVS/ZDS) conditions, nominal op- means the outside nominal conditions. Additionally, the off-
eration, output power, power conversion efficiency, waveform
equations. nominal-operation class-E inverter [10], [11] also works outside
the nominal conditions.
I. I NTRODUCTION Analyses of the class-E inverter outside nominal operations
have been carried out recently. These analyses are classified
I N RECENT years, the resonant class-D [1], class-DE [2],
and class-E [3]–[22] inverters have been widely used in
various applications. The class-E inverter is a well-known
into two approaches. One is a frequency-domain analysis [12]–
[14], and the other is a time-domain one [15]–[17]. In [12],
the frequency-domain analysis of the class-E inverter outside
resonant inverter that can operate with high power conver-
sion efficiency at high frequencies. Since the introduction of nominal operations was presented. Because of the frequency-
the class-E inverter [3], many analytical descriptions of this domain analysis, however, the switching pattern should be fixed
circuit have appeared. Additionally, many applications of the prior to calculations. Therefore, effects of the MOSFET body
class-E inverter, such as dc–dc converter [4], inverter with diode cannot be considered because the MOSFET body diode
impedance inverter [5], lamp ballast [6], high-power-factor turns on and off autonomously. In [15]–[17], the time-domain
inverter [7], wireless power transfer system [8], and so on, were analyses of the class-E inverter outside nominal operations were
proposed. These applications are transformed into the basic presented. In [16] and [17], turn-on effect of the MOSFET body
class-E inverter topology for their designs. Therefore, it can be diode on the waveform equations is considered. However, the
stated that the analytical expressions in the class-E inverter are switch-voltage recovery during the ON state of the MOSFET
very useful and applicable for many applications of not only body diode is not considered.
the class-E inverter but also other topologies of the class-E In [18], an adjusting method of the load network for achiev-
ing the class-E ZVS/ZDS conditions is introduced. This method
Manuscript received July 12, 2012; revised October 30, 2012, January 29, is very useful for designs of the class-E inverters. In [18],
2013, and April 27, 2013; accepted May 26, 2013. Date of publication June 11, the switch-voltage recovery during ON state of the MOSFET
2013; date of current version September 19, 2013. This work was supported
in part by the Scholarship Foundation and Grant-in-Aid for Scientific Research
body diode is illustrated, which indicates the importance of the
(23760253) of JSPS, by the Support Center for Advanced Telecommunications MOSFET-body-diode effect in the class-E inverter operation. In
Technology Research, and by the Telecommunications Advancement Founda- the previous papers, however, there is no analytical expression
tion, Japan.
T. Nagashima and H. Sekiya are with the Graduate School of Ad-
including the switch-voltage recovery. For comprehending the
vanced Integration Science, Chiba University, Chiba 263-8522, Japan (e-mail: operation of the class-E inverter in a wide region of parameters,
[email protected]; [email protected]). it is important to consider the MOSFET-body-diode effect
X. Wei and T. Suetsugu are with the Department of Electronics Engineering
and Computer Science, Fukuoka University, Fukuoka 814-0180, Japan (e-mail: completely, namely, not only its turn-on but turn-off, in the
[email protected]; [email protected]). analysis.
M. K. Kazimierczuk is with the Department of Electrical Engineering, There is an idea that the behavior of class-E inverter outside
Wright State University, Dayton, OH 45435-0001 USA (e-mail: marian.
[email protected]). nominal operation can be comprehended by using circuit sim-
Digital Object Identifier 10.1109/TIE.2013.2267693 ulators. In the class-E inverter, however, it takes a long time

0278-0046 © 2013 IEEE

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1800 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

to converge the dc-supply current, which flows through the RF

choke, in transient analysis because the time constant of the
RF choke is high. Generally, inverters with high-Q resonant
filter also have a long transient-response time. Therefore, it
leads to a high calculation cost for obtaining the steady-state
waveforms of the class-E inverter by using the circuit simula-
tors. In addition, circuit simulators give waveforms at a fixed Fig. 1. (a) Circuit topology of the class-E inverter. (b) Equivalent circuit of
set of parameters. It is hard to comprehend the circuit behavior the class-E inverter.
according to any parameter variations by using circuit simula-
tors. For these reasons, it is useful for designers to obtain the
analytical expressions of steady-state waveforms outside nom-
inal operations. Additionally, an analysis has many advantages
compared with the simulation. Analytical expressions cultivate
designer’s fundamental understanding and intuition. By using
the analytical expressions, much additional information can be
obtained easily.
This paper, which was previously presented in part at ISCAS
Fig. 2. Example waveforms in the class-E inverter satisfying nominal condi-
2011 [17],1 presents analytical expressions for steady-state tions for D = 0.5.
waveforms, output power, and power conversion efficiency of
the class-E inverter outside the class-E ZVS/ZDS conditions at factors in the class-E inverter include conduction losses in the
a high Q and any duty ratio, taking into account the MOSFET- ESRs and the switch on-resistance, the conditions for obtaining
body-diode effect. By considering the switch-voltage recovery the maximum power conversion efficiency are not the same
during the MOSFET-body-diode ON state, the applicable pa- as those for the class-E ZVS/ZDS conditions. Therefore, the
rameter range of the analytical expressions in this paper is much class-E ZVS/ZDS conditions are called “nominal conditions,”
wider than that of the previous analytical expressions. The and the conditions for obtaining the maximum power conver-
analytical expressions in this paper cover all the results of [15]– sion efficiency are called “optimal conditions” [18].
[17]. By carrying out the PSpice simulations and the circuit Fig. 2 depicts example waveforms in the class-E inverter at
experiments, it is shown that the analytical predictions agree nominal operation for D = 0.5. In the class-E inverter, switch S
with the simulated and experimental results quantitatively, is driven by an input signal vg . During the switch-off interval,
which validates the accuracy of our analytical expressions. the difference of currents through the dc-feed inductance and
Additionally, the switching-pattern distribution maps are also the resonant filter flows through the shunt capacitance CS . The
shown, which can be obtained from the waveform equations. current through the shunt capacitance produces the switch volt-
age vS . Because the class-E inverter usually has a resonant filter
with high quality factor Q, the output current io is regarded as
II. C IRCUIT D ESCRIPTION AND P RINCIPLE O PERATION a sinusoidal waveform. Additionally, the output filter produces
Fig. 1(a) shows a circuit topology of the class-E inverter. It is a phase-shift φ between the input signal and the output current,
composed of dc-supply voltage source VDD , dc-feed inductance as shown in Fig. 2.
LC , MOSFET as a switching device S, shunt capacitance
CS , and series-resonant filter L0 −C0 −R. The class-E inverter III. WAVEFORM E QUATIONS O UTSIDE
achieves high-power conversion efficiency at high frequencies N OMINAL C ONDITIONS
because it satisfies the ZVS/ZDS conditions simultaneously at The analytical steady-state waveform equations for the
the switch turn-on instant. Switching loss is minimized because class-E inverter outside nominal conditions are given in this
of the ZVS and jump-less currents at turn-on instant. The class- section. Note that all the equations in [17] are renewed as new
E ZVS/ZDS conditions are expressed as ones.
⎡ ⎤
vS (2πD)

⎢  ⎥ A. Switching Patterns
⎣ dvS (θ)  ⎦=0 (1)
dθ  
Fig. 3 shows the switch voltage and current waveforms of
θ=2πD
the class-E inverter outside nominal operation. We classify the
where vS is the voltage across the switching device S and D is switching patterns into three cases, as shown in Fig. 3. Fig. 3(a)
the switch-off duty ratio at the switch. In real circuits, there are shows that the switch voltage does not reach zero during switch-
the equivalent series resistances (ESRs) of the passive elements off interval. This switching pattern is called “Case 1” in this
and the MOSFET switch on-resistance. Because the power-loss paper. In this case, the turn-on switching loss occurs at turn-on
instant. When the switch voltage reaches zero prior to turn-on
1 In this paper, Case 3 waveforms, which are defined in Fig. 3(c), are newly switching instant, the MOSFET antiparallel body diode turns
considered, and new plots Figs. 6 and 7 can be obtained. For including Case 3, on at θ = θ1 , as shown in Fig. 3(b), where θ = ωt represents
all the equations are renewed. Additionally, this paper shows the switching-
pattern distributions, the new experimental and PSpice simulation results, and the angular time. This switching pattern is called “Case 2,” in
the application of the analytical expressions. which the ZVS is achieved at θ = 2πD. The on-resistance of
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NAGASHIMA et al.: CLASS-E INVERTER OUTSIDE NOMINAL OPERATION 1801

6) The circuit operations are considered in the interval 0 ≤

θ < 2π. The switch is in the OFF state for 0 ≤ θ < 2πD
and in the ON state for 2πD ≤ θ < 2π.
7) The MOSFET body diode turns on at θ = θ1 and turns
off at θ = θ2 for 0 < θ1 ≤ θ2 < 2πD. When θ1 and/or θ2
does not appear during switch-off interval, this analysis
gives θ1 = 2πD and/or θ2 = 2πD, respectively.
8) The parasitic capacitances of the inductors are ignored.
Fig. 3. Switch voltage and current waveforms of the class-E inverter. By the aforementioned assumptions, the equivalent circuit is
(a) Case 1. (b) Case 2. (c) Case 3. obtained as shown in Fig. 1(b).

the MOSFET body diode is, however, much larger than that of
the MOSFET. Therefore, the large conduction loss occurs in C. Waveform Equations
this case. There is also a case that the switch voltage returns
This section introduces only the resulting equations, and
to positive at θ = θ2 via MOSFET-body-diode ON state, as
the detailed analysis procedure is shown in the Appendix.
shown in Fig. 3(c), which is called “Case 3.” In this case,
Additionally, the classifications of the switching patterns and
both the turn-on switching loss and the conduction loss in the
the derivations of θ1 and θ2 are discussed in Section IV. From
MOSFET body diode occur. The switching patterns are closely
assumption 4, the output current is
related to the amplitude and the phase shift of the output current
because the switch voltage is expressed as the integration of
io = Im sin(θ + φ). (2)
the difference of the dc-supply current and output current.
Therefore, if the inverter parameters, such as load resistance,
In (2), Im is the amplitude of the output current
resonant capacitance and inductance, switch-off duty ratio, and
so on, vary from the nominal conditions, the amplitude and the 2πβVDD
phase shift of the output current also vary, and the change of the Im = (3)
A2 BQR(αδ + γβ)
switching pattern occurs. The relationship between the switch
waveform and output-filter parameters are shown in [18]. It can where
be stated from [18] that it is not easy to predict which switching
pattern appears for a certain set of parameters. α = k1 cos2 φ + k2 sin φ cos φ + k3 (4)
In the previous papers, the steady-state waveform equations
β = k4 cos φ + k5 sin φ (5)
in [12] and [15] are valid only for Case 1. The steady-state
waveform equations in Cases 1 and 2 are given in [16] and γ = k6 cos φ + k7 sin φ (6)
[17]. There are, however, no analytical steady-state waveform 1 1
equations, which are valid for Cases 1, 2, and 3. δ = θ12 + θ22 + 2π 2 D2 − 2πDθ2 . (7)
2 2
In addition, the coefficients k in (4)–(7) are
B. Assumptions and Parameters
1 1 1 1
First, the following parameters are defined. k1 = cos(2θ1 ) − cos θ1 + cos(4πD) + cos(2θ2 ) +
√ 2 2 2 2
1) A = f0 /f = ω0 /ω = 1/ω L0 C0 : the ratio of the reso- − cos θ2 cos(2πD) + sin θ2 sin(2πD) (8)
nant frequency to the operating frequency.
1 1 1
2) B = C0 /CS : the ratio of the resonant capacitance to the k2 = − sin(2θ1 ) + sin θ1 − sin(4πD) − sin(2θ2 )
2 2 2
shunt capacitance.
3) D: the switch-off duty ratio of switch S. + sin θ2 cos(2πD) + cos θ2 sin(2πD) (9)
4) Q = ωL0 /R: the loaded Q factor. 1 1 1
k3 = − cos(2θ1 ) − cos(4πD) − cos(2θ2 )
For obtaining the waveform equations, the analysis is based 4 4 4
π 3
on the following assumptions for simplification. + 2 + − sin θ2 sin(2πD), (10)
A BQ 4
1) The MOSFET works as an ideal switch device, i.e., it
has zero on-resistance, infinite off-resistance, and zero k4 = − θ1 cos θ1 + sin θ1 + (θ2 − 2πD) cos(2πD)
switching time. + sin(2πD) − sin θ2 (11)
2) The MOSFET body diode also works as an ideal switch k5 = θ1 sin θ1 + cos θ1 + (2πD − θ2 ) sin(2πD)
device. Therefore, it has zero forward voltage drop, infi-
nite off-resistance, and zero switching time. + cos(2πD) − cos θ2 − 1 (12)
3) The dc-feed inductance LC is high enough so that the k6 = sin θ1 + sin(2πD) − sin θ2
current through the dc-feed inductor is constant. + (θ2 − 2πD) cos θ2 − θ1 (13)
4) The loaded Q factor is high enough to generate a pure
sinusoidal output current io for any parameters. k7 = cos θ1 + cos(2πD) + (2πD − θ2 ) sin θ2 − cos θ2 − 1.
5) All the passive elements are linear and have zero ESR. (14)
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1802 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

Additionally, phase shift φ is obtained by solving an algebraic

equation for tan φ

(k4 k3 +k5 k10 ) tan3 φ+(k2 k4 +k3 k9 −k3 k5 +k4 k10 ) tan2 φ
+ (k1 k4 −k2 k5 +k4 k9 +k5 k8 +k3 k4 +k5 k10 ) tan φ
+ (k4 k8 −k1 k5 −k3 k5 +k4 k10 ) = 0 (15)

where
1 1
k8 = − sin(2θ1 ) + sin θ1 − sin(4πD) − sin(2θ2 )
2 2
+ cos θ2 sin(2πD) + sin θ2 cos(2πD) (16)
1 1 1
k9 = cos(2θ2 ) − cos(2θ1 ) + cos θ1 − cos(4πD) Fig. 4. Flowchart for obtaining θ1 and θ2 .
2 2 2
1 θ2 = 2πD are the same as those in [16] and [17]. The analytical
− + cos θ2 cos(2πD) − sin θ2 sin(2πD)
2 steady-state waveform equations in this paper cover all the
− cos2 θ2 + sin2 θ2 (17) results of [15]–[17].
θ1 θ2 1 1
k10 = − + + sin(2θ2 )+ sin(4πD)
2 2 4 4 IV. D ERIVATIONS OF θ1 AND θ2
1
− sin(2θ2 ) − πD − sin θ2 cos(2πD) The waveform equations given in Section III are valid for
4 all the switching patterns in Cases 1, 2, and 3. For obtaining
(1 − A2 )π the waveforms, however, θ1 and θ2 should be determined. This
+ sin θ2 cos θ2 + . (18)
A2 B section introduces an algorithm for obtaining the values of θ1
and θ2 . Fig. 4 shows the flowchart for obtaining θ1 and θ2 .
The switch voltage is expressed as (19), shown at the bottom First, the waveforms for θ1 = θ2 = 2πD are considered.
of the page, where IDD is the dc component of the current After substituting θ1 = θ2 = 2πD into (19), we calculate the
through the dc-feed inductor, which is given by phase shift from (15) and the switch voltage with zero deriva-
2παVDD tive. θa is defined as the instant when the zero-derivative switch
IDD = 2
. (20) voltage appears. Therefore, we have
A BQR(αδ + γβ)

dvS1  1
The current through the shunt capacitance is = iC (θa ) = 0, for 0 < θa ≤ 2πD. (23)
⎧ dθ θ=θa ωCS S
⎪ iC = IDD −Im sin(θ+φ), for 0 ≤ θ < θ1
⎨ S1
iCS2 = 0, for θ1 ≤ θ < θ2 The solution of (23) can be obtained analytically as
iC S =
⎪
⎩ i C S3
= I DD −I m sin(θ+φ), for θ2 ≤ θ < 2πD 
for 2πD ≤ θ < 2π. IDD
iCS4 = 0, θa = sin−1 − φ, for 0 < θa ≤ 2πD. (24)
(21) Im
The current through the switch is When there is no solution of θa or
⎧
⎪ iS1 = 0, for 0 ≤ θ < θ1
⎨ vS1 (θa ) > 0 for all θa (25)
iS2 = IDD − Im sin(θ + φ), for θ1 ≤ θ < θ2
iS =
⎪
⎩ iS3 = 0, for θ2 ≤ θ < 2πD
the switching pattern is classified as Case 1, and θ1 = θ2 =
iS4 = IDD − Im sin(θ + φ), for 2πD ≤ θ < 2π
(22) 2πD can be obtained.
When the switching pattern is not for Case 1, only θ2 = 2πD
where iS2 describes the current through the MOSFET body is substituted into (19). Additionally, the angular time for the
diode. zero-switch-voltage appearance is calculated from
Note that the equations for θ1 = θ2 = 2πD are the same
as those given in [15]. Additionally, the equations for only vS1 (θb ) = 0. (26)

⎧
⎪ v = A2 BQR {IDD θ + Im [cos(θ + φ) − cos φ]} , for 0 ≤ θ < θ1
⎨ S1
vS2 = 0, for θ1 ≤ θ < θ2
vs = (19)
⎪
⎩ vS3 = A2 BQR {IDD (θ − θ2 ) + Im [cos(θ + φ) − cos(θ2 + φ)]} , for θ2 ≤ θ < 2πD
vS4 = 0, for 2πD ≤ θ < 2π
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NAGASHIMA et al.: CLASS-E INVERTER OUTSIDE NOMINAL OPERATION 1803

The power loss in rLC is

2
PLC = rLC IDD . (31)

The power loss in rCS is

⎡θ ⎤
2π 1 
2πD
rC r
i2CS dθ = S ⎣ i2CS dθ+ i2CS dθ⎦
C
PC S = S
2π 2π
Fig. 5. Equivalent circuit of class-E inverter for power-loss calculations. 0 0 θ2

This equation is solved numerically. Newton’s method is ap- rC  2

= S IDD (θ1 −θ2 +2πD)
plied to solve the algebraic equation numerically in this paper. 2π
When the current through the MOSFET body diode satisfies + 2IDD Im [cos(θ1 +φ)−cos φ+cos(2πD+φ)

iS2 (2πD) ≤ 0 (27) − cos(θ2 +φ)]

2
Im
the switching pattern is classified as Case 2, and θ1 = θb and + [2θ1 −2θ2 +4πD−sin(2θ1 +2φ)
4
θ2 = 2πD are obtained.
When the switching pattern belongs to neither Case 1 nor 2, − sin(4πD+2φ)+sin(2θ2 +2φ)]} . (32)
it is classified as Case 3. In Case 3, θ1 and θ2 are obtained by
solving The power loss in rL0 C0 is
 
vS1 (θ1 ) 2π 2
= 0. (28) rL C rL0 C0 Im
iS (θ2 ) PL0 C 0 = 0 0 i2o dθ = . (33)
2π 2
0
Following this algorithm, it is possible to obtain the values of
θ1 and θ2 and to comprehend the switching pattern for given Additionally, power losses in the MOSFET should be consid-
parameters simultaneously. ered. In Cases 1 and 3, the turn-on switching losses occur,
which is expressed as
V. O UTPUT P OWER AND P OWER C ONVERSION E FFICIENCY 1 1  2  − 2 
Psw = CS f vS2 (2πD− ) = CS f vS1 θ1 +vS3 (2πD− )
2 2
A2 BQR  2 2
In this section, analytical expressions for the output power
and the power conversion efficiency are derived by using the = θ1 IDD +2θ1 IDD Im [cos(θ1 +φ)−cos φ]
waveform equations given in Section III. In real circuits, the 4π
+ Im2
[cos(θ1 +φ)−cos φ]2
power losses occur in ESRs of passive elements, MOSFET on-
+ (2πD−θ2 )2 IDD2
resistance, and MOSFET body diode. It is assumed that the
+ 2Im IDD {(2πD−θ2 ) [cos(2πD+φ)
parasitic resistances and MOSFET-body-diode forward voltage
− cos(θ2 +φ)]}

drop are small enough not to affect the waveforms [2], [16],
[17]. Fig. 5 shows the equivalent circuit model of the class-E + Im [cos(2πD+φ)−cos(θ2 +φ)]2 (34)
2

inverter for the power-loss calculations. In this paper, the power

losses in MOSFET on-resistance rS ; ESRs of dc-feed induc- where vS1 (θ1− ) and vS3 (2πD− ) are the switch voltages just
tance rLC , shunt capacitance rCS , and resonant network rL0 C0 ; prior to turn on. It can be confirmed that PSW = 0 for θ1 =
and MOSFET body diode are considered. 2πD and θ2 = 2πD, which are Case 2 switching pattern condi-
The output power Po is tions, because of vS1 (θ1 ) = 0. Conversely, PSW is not equal to
zero for θ = 2πD. Namely, (34) can express the switching loss
2π 2
R RIm of all the switching patterns. In the Cases 2 and 3 switching
Po = i2o dθ = . (29) patterns, the MOSFET body diode turns on, and the conduction
2π 2
0 loss in the MOSFET body diode should be considered. The
The conduction loss in the MOSFET on-resistance rS is MOSFET-body-diode conduction loss is

2π 2π 2π θ2

rS rS 1 1
PS = i2S dθ = i2S dθ PD = Vd iS dθ = Vd iS dθ
2π 2π 2π 2π
0 2πD 0 θ1

rS Vd
= 2
2π(1−D)IDD +2IDD Im [cos φ−cos(2πD + φ)] = {IDD (θ2 −θ1 )+Im [cos(θ2 +φ)−cos(θ1 +φ)]}
2π 2π
 (35)
I2
+ m [4π(1−D)+sin(4πD + 2φ)−sin 2φ] .
4 where Vd is the forward voltage drop of the MOSFET body diode.
(30) It can be confirmed from (35) that PD = 0 for θ1 = θ2 = 2πD.
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1804 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

From the aforementioned considerations, the total power loss experimental measurements, respectively. In [17, Table I], the
of the class-E inverter is output power was obtained from

Vo2
Ptotal = PS + PCS + PLC + PL0 C0 + PD + Psw . (36) Po = (38)
R
From (3), (20), (29), and (36), the power conversion efficiency where Vo is a root-mean-square value of the output voltage,
can be obtained analytically as (37), shown at the bottom of the which was measured by Agilent 3458A. In addition, the power
page. Note that this power conversion efficiency expression is conversion efficiency was measured by
valid for all the switching patterns.
Po Vo2
η= = (39)
PI RVDD IDD
VI. E XPERIMENTAL V ERIFICATION
where PI is the dc-supply power and VDD and IDD are mea-
A. Nominal State sured by Iwatsu VOAC7523. The analytical and the experi-
For validating the analytical expressions, PSpice simulations mental waveforms for nominal conditions were presented in
and circuit experiments were carried out. The design specifi- [17, Fig. 4]. It is shown in [17, Fig. 4] that the class-E ZVS/ZDS
cations for nominal operation were given as follows: operat- conditions had been achieved in this state. We define the state in
ing frequency fnom = 1 MHz, dc-supply voltage VDD = 5 V, [17, Table I and Fig. 4] as the “nominal state.” At the following
output resistance Rnom = 5 Ω, switch-off duty ratio D = 0.5, measurements, some parameters varied from the nominal state.
and loaded quality factor Q = 10. First, we carry out the design
of the class-E inverter with the nominal conditions in (1) for
B. Output Power and Power Conversion Efficiency
θ1 = θ2 = 2πD. By using design equations in [19], A = 0.94
and B = 0.62 are obtained. From these values, the element The output power and the power conversion efficiency as
values are obtained as LC = 34.67 μH, L0 = 7.96 μH, CS = a function of A were shown in [17, Fig. 5]. It is shown in
5.84 nF, and C0 = 3.60 nF. An IRF530 MOSFET device was [17, Fig. 5] that both the output power and the power conversion
used in the circuit experiment. Therefore, rS = 0.16 Ω and efficiency are sensitive to the operating frequency. Generally,
Vd = 0.7 V were obtained from the IRF530 MOSFET data the maximum output power can be obtained for A < 1. This is
sheet. All element values including ESR values were measured because the output resonant filter works as an inductive filter for
by HP4284A LCR impedance meter. In experimental circuits, the nominal conditions [20]. Conversely, the maximum power
the shunt capacitance was composed of the MOSFET drain-to- conversion efficiency was obtained for A = 0.897, which can
source capacitance and external capacitance connected in par- be obtained by solving ∂η/∂A = 0.
allel. The IRF530 MOSFET drain-to-source capacitance was Fig. 6 shows the output power and the power conversion effi-
estimated as 500 pF, which is also obtained from the data sheet. ciency as a function of CS /CSnom . Compared with [17, Fig. 5],
The analytical predictions and experimental measurements for it is seen that the power conversion efficiency is almost constant
satisfying the class-E ZVS/ZDS conditions were given in for CS variations. The output power is also not sensitive to the
[17, Table I]. In the PSpice simulations, the element values and CS variations compared with [17, Fig. 5]. For CS /CSnom < 1,
the ESR ones are the same as the analytical predictions and the the Case 3 switching pattern appears. It is shown in Fig. 6 that

Po
η=
Po + Ptotal
 2
α  
= 4πR 2 4πrS (1 − D) + 4πrLC + 2rCS (θ1 − θ2 + 2πD) + A2 BQR(2πD − θ2 )2 + θ12
β

α
+4 {2rS [cos φ − cos(2πD + φ)] + 2rCS [cos(θ1 + φ) − cos φ + cos(2πD + φ) − cos(θ2 + φ)]
β

+A2 BQRθ1 [cos(θ1 + φ) − cos φ] + A2 BQR(2πD − θ2 ) [cos(2πD + φ) − cos(θ2 + φ)]
+ 4πR + 4πrL0 C0 + rS [4π(1 − D) + sin(4πD + 2φ) − sin 2φ]
+ rCS [2θ1 − 2θ2 + 4πD − sin(2θ1 + 2φ) − sin(4πD + 2φ) + sin(2θ2 + 2φ) − sin 2φ]
 
+ 2A2 BQR [cos(θ1 + φ) − cos φ]2 + [cos(2πD + φ) − cos(θ2 + φ)]2
 
A2 BQR(αδ + γβ) α
+ cos(θ2 + φ) − cos(θ1 + φ) + (θ2 − θ1 ) (37)
πβVDD β
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NAGASHIMA et al.: CLASS-E INVERTER OUTSIDE NOMINAL OPERATION 1805

TABLE I
C OMPUTATION T IMES BY U SING A NALYTICAL E XPRESSIONS
AND PS PICE S IMULATION

existence of the voltage and the current fall times and switching
delay. It is shown in Fig. 7(a) that the analytical plots and
experimental ones agreed with the plots from PSpice simu-
lations using ideal switch and those with MOSFET model,
Fig. 6. Output power and power conversion efficiency as functions of respectively. From the aforementioned results, it is stated that
CS /CSnom . (a) Output power.(b) Power conversion efficiency. the difference between analytical and experimental results for
small D appears because the analytical model does not consider
the voltage and current fall times and switching delay.
It is shown in [17, Fig. 5] and Figs. 6 and 7 that the analytical
predictions agreed with the PSpice simulated results and the
experimental measurements quantitatively, which validated the
accuracy and effectiveness of the analytical expressions in this
paper.
Additionally, it is shown in Figs. 6 and 7 that the Case 3
regions appear in wide region near the nominal-condition point.
These results also indicate the importance of including the
Case 3 switching pattern in the analysis for class-E inverter
outside nominal operations.
Table I gives the computation times for drawing Figs. 6 and 7
Fig. 7. Output power and power conversion efficiency as functions of D. by using the analytical expressions and PSpice simulations. The
(a) Output power. (b) Power conversion efficiency.
computations were carried out on the computer whose speci-
fications are as follows: CPU, Intel Core2 Extreme 3.00-GHz
the analytical expressions of the output power and the power Processor; memory, 3.25 GB; and operating system, Windows
conversion efficiency are valid for the Case 3 switching pattern. XP Professional version 2002 Service Pack 3. The C-language
Fig. 6(a) also shows the previous analytical result, which can program was used for calculations by using analytical expres-
be obtained by using the analytical expression of the output sions. PSpice version 16.0 was used as a circuit simulator.
power in [17]. In [17], the Case 3 parameter region is recog- The number of plotting points in Figs. 6 and 7 is 500. In the
nized as the Case 1 parameter region. It is shown in Fig. 6(a) PSpice simulations, 200 μs was set as the run time, with 10-ns
that the previous analytical results are far from the measured maximum step size for the PSpice transient analysis, and the
ones as decreasing CS /CSnom and the results from the analyt- parametric sweep mode was used. It is shown in Table I that
ical expression obtained in this paper agree with the measured the computation cost when the analytical expressions are used
ones well. This result indicates that the analytical expressions in is much lower than that for PSpice-simulation usage.
this paper provide more accurate predictions than the previous
analytical ones, which is the usefulness of considering the
Case 3 waveform in the class-E inverter analysis outside nomi- VII. D ISTRIBUTION OF S WITCHING PATTERNS
nal operations.
Fig. 7 shows the output power and the power conversion Because the switching pattern can be obtained as shown in
efficiency as a function of D. It is shown in Fig. 7 that PSpice Section IV, it is possible to obtain switching-pattern distribution
simulated and experimental results agreed with the analytical maps, which is one of the applications of the analytical expres-
predictions well for D > 0.3. Additionally, both the output sions. From the switching-pattern distribution maps, a lot of
power and the power conversion efficiency are almost constant information can be obtained. Fig. 8 shows the switching-pattern
around the nominal state. However, differences of the output distributions on the C0 /C0nom − CS /CSnom and f /fnom − D
power between the analytical results and the PSpice simulated planes. For obtaining these figures, CS and D are calculated
and experimental ones appear for D < 0.3. by solving the boundary condition between Cases 1 and 2
Fig. 7(a) also shows the simulation result using the ideal numerically for fixed C0 and f , respectively, which is
switch model. The PSpice simulation using the ideal switch
gives the switch waveform without voltage and current fall vS1 (2πD) = 0, for θ1 = θ2 = 2πD. (40)
times and switching delay. On the other hand, using the
MOSFET model includes the voltage and current fall times We can follow the boundary curve by solving the boundary
and switching delay. Namely, the difference between the ideal condition by varying the resonant capacitance C0 and the
switch and the MOSFET model in PSpice simulations is the frequency f , respectively. Similarly, the boundary conditions
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1806 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

Fig. 8. Distributions of switching patterns. (a) C0 /C0nom − CS /CSnom

plane. (b) f /fnom − D plane.

between Cases 2 and 3 and between Cases 1 and 3 are ex-

pressed as

iS2 (2πD) = 0, for θ2 = 2πD (41)

vS1 (θa ) = 0, for θ1 = θ2 = 2πD. (42) Fig. 9. Waveforms obtained from analytical expressions (dashed line), PSpice
simulations (dotted line), and circuit experiments (solid line). (a) Case 1 for
Note that θa in (42) is the nearest value to 2πD in (24). C0 /C0nom = 0.95 and CS /CSnom = 1. (b) Case 2 for C0 /C0nom = 1.2
It is obviously seen from the boundary conditions in and CS /CSnom = 0.6. (c) Case 3 for C0 /C0nom = 0.95 and CS /CSnom =
0.4. (d) Another class-E switching condition for f /fnom = 1.14 and D =
(40)–(42) that a point, at which three boundary curves cross, 0.75.
satisfies the nominal conditions. This can be confirmed from
Fig. 8. Additionally, it is also shown in Fig. 8 that not only and another class-E switching conditions. Each parameter is
Case 2 but also Case 3 switching patterns occupy wide regions, marked on Fig. 8. It is shown in Fig. 9(b) and (c) that the ana-
which have never been described in the analytical expressions lytical waveform equations in this paper express the MOSFET-
in the previous papers. The analytical expressions in this paper body-diode effect accurately. It can be confirmed from Fig. 9
cover much wider parameter region than those in the previous that all the switching patterns of the analytical waveforms
papers. agreed with those of simulated and experimental ones. These
It is shown in Fig. 8(a) that the ZVS region, namely, Case 2 results show the validity of the switching-pattern distribution
region, appears only for C0 /C0nom > 1.0 and there is no ZVS map in Fig. 8 and the accuracy of the analytical waveform
region for CS /CSnom > 1.05. In [18], the adjusting method of expressions.
the load network for achieving the class-E ZVS/ZDS conditions
is introduced. This method is very useful for the design of
VIII. A PPLICATION OF A NALYTICAL
the class-E inverter. In addition, the Case 3 switching pattern
E XPRESSIONS —D ESIGN OF C LASS -E I NVERTER W ITH
is considered in this method, which indicates the importance
I NDUCTIVE I MPEDANCE I NVERTER
of including Case 3 switching pattern in the class-E inverter
operations. In [18], however, the adjusting strategies are shown It is generally stated that the analytical expressions have a
qualitatively and not quantitatively. Switching-pattern distribu- potential to be the basement of many applications, such as
tion maps like Fig. 8(a) give the quantitative adjustment criteria control, new topology, and so on. The analytical expressions
on any parameter plane, which enhance the adjusting method presented in this paper are valid for wide parameter region,
in [18]. which includes not only the nominal-condition parameters but
It is shown in Fig. 8(b) that there are two sets of param- also outside nominal-condition ones. Therefore, the application
eters, which satisfy the class-E ZVS/ZDS conditions on the area of the analytical expressions presented in this paper is very
f /fnom − D plane. Additionally, it is also shown in Fig. 8(b) wide. Many class-E switching circuits [4]–[8] are transformed
that the ZVS region appears only for 1.00 < f /fnom < 1.11 into the basic class-E inverter (as shown in Fig. 1) for their
and 0.48 < D < 0.72. Because both f and D are controllable designs. From this point of view, it can be also stated that the
parameters, this figure gives important information for the analytical expressions presented in this paper are very useful
inverter control. It is shown in Fig. 8(b) that the FM and PWM and applicable for many applications of the class-E switching
control [2], [9] is one of the good strategies to control the output circuits.
power of the class-E inverter with achieving the ZVS. In this section, the analytical expressions derived in this
From the aforementioned examples and discussions, it can be paper are applied to the design of the class-E inverter with an
stated that the analytical expressions obtained in this paper are inductive impedance inverter. Fig. 10(a) shows the class-E in-
powerful tools for obtaining a lot of information on the class-E verter with an inductive impedance inverter [5]. The inductance
inverter. Lp acts as an impedance inverter. In the basic class-E inverter
Fig. 9 shows the analytical, PSpice simulated, and experi- as shown in Fig. 1, it is known that the ZVS is achieved when
mental waveforms for the Cases 1, 2, and 3 switching patterns the load resistance varies in the region of 0 ≤ R ≤ Rnom [21].
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NAGASHIMA et al.: CLASS-E INVERTER OUTSIDE NOMINAL OPERATION 1807

Fig. 10. Class-E inverter with an inductive impedance inverter. (a) Circuit of
the inverter. (b) Equivalent circuit of the inverter.

The purpose of Lp addition is to achieve the ZVS for all load

variations. By transforming the Lp − Ro parallel circuit into
its equivalent LS − Req series circuit, the equivalent circuit
of Fig. 10(a) is the same as the basic topology of the class-E
inverter as shown in Fig. 10(b). Therefore, the analytical expres-
sions in this paper can be easily applied to the operation com-
prehension of the class-E inverter with an inductive impedance
inverter. In this section, the design specifications are the same
as in Section VI. The design values for nominal operation were
derived by using the design equations in [5] and [19], which are
C0nom = 7.20 nF, CSnom = 11.7 nF, Lrsnom = 3.58 μH, and
Lpnom = 0.796 μH.
From [5], the relationships among the component values of
Fig. 11. Switching-pattern distributions for the class-E inverter with inductive
the parallel and series circuits at the operating frequency f are impedance inverter. (a) Switching-pattern distribution on Leq /Leqnom and
Req /Reqnom plane and the variation of Leq and Req against Ro . (b) ZVS
Ro X Lp region at any Ro on Lrs /Lrsnom and Lp /Lpnom plane. (c) Switching-pattern
Req = ! "2 X LS = ! X "2 (43) distribution on Lp /Lpnom and Ro /Ronom plane at Lrs /Lrsnom = 1.07.
Ro Lp
1+ X Lp 1+ Ro
(d) Switching-pattern distribution on Lrs /Lrsnom and Ro /Ronom plane at
Lp /Lpnom = 0.7.

where XLp = ωLp and XLS = ωLS . In [5], the inverters were
designed for satisfying Req ≤ Reqnom for any Ro . Because
Req ≤ Reqnom is achieved for all load variations, it was stated
that the class-E inverter with an inductive impedance inverter
can keep ZVS for all load variations. The variations of XLS for
Ro variations were, however, not considered in [5].
Fig. 11(a) shows the switching-pattern distribution on the
Leq /Leqnom and Req /Reqnom plane, where Leq = Lrs + LS
as shown in Fig. 10(b). The line on Fig. 11(a) expresses
Leq /Leqnom and Req /Reqnom values for 0 ≤ Ro ≤ ∞ varia-
tions. It is seen from Fig. 11(a) that Req is always less than
Fig. 12. Analytical (dashed line), PSpice simulation (dotted line), and ex-
Reqnom for Ro variation. However, the non-ZVS region appears perimental (solid line) waveforms of the class-E inverter with an inductive
for 0 ≤ Ro < Ronom because the reactance XLS becomes impedance inverter for Ro = Ronom /2 = 2.5 Ω. (a) With design values from
smaller than that of the design value for 0 ≤ Ro < Ronom . [5] and [19] for Lrs = 3.58 μH and Lp = 0.796 μH. (b) With design values
obtained from this paper design for Lrs = 3.83 μH and Lp = 0.716 μH.
Fig. 11(b) shows the parameter region on Lrs /Lrsnom and
Lp /Lpnom plane where the inverter always achieves the ZVS
for 0 ≤ Ro ≤ 1000 · Ronom . This figure is obtained by check- Lrs /Lrsnom and Ro /Ronom plane at Lp /Lpnom = 0.7, respec-
ing the switching-pattern distribution maps in increments of tively. It can be confirmed from these figures that the class-E
0.01 · Ronom for 0 ≤ Ro < 10 · Ronom and 2 · Ronom for 10 · inverter with an inductive impedance inverter achieves the
Ronom ≤ Ro ≤ 1000 · Ronom , namely, 1495 switching-pattern ZVS condition regardless of load resistance. As a result, it
distribution maps were drawn and checked. By using the ana- is possible to design the ZVS inverters when Lrs and Lp
lytical expressions in this paper, Fig. 11(b) can be obtained in are fixed in the dotted-region value in Fig. 11(b). For exam-
a short time. We would like to emphasize that it is too hard ple, when Lrs = 1.07 × Lrsnom = 3.83 μH and Lp = 0.9 ×
to obtain the same result in actual time if we use the circuit Lpnom = 0.716 μH, the inverter always achieves the ZVS
simulator for checking the switching conditions. It is seen from regardless of load resistance Ro . Fig. 12 shows the analyti-
Fig. 11(b) that, if the inductance values Lrs and Lp are in the cal, PSpice simulation, and experimental waveforms for Ro =
dotted region, namely, slightly changed from the nominal value, Ronom /2 = 2.5 Ω. Fig. 12(a) shows waveforms for Lrs =
the ZVS can be achieved regardless of Ro . 3.58 μH, Lp = 0.796 μH, C0 = 7.20 nF, and CS = 11.7 nF,
Fig. 11(c) and (d) shows the switching-pattern distributions which were obtained from the design equations in [5] and [19].
on Lp /Lpnom and Ro /Ronom plane at Lrs /Lrsnom = 1.07 and It is seen from this figure that the switch waveform did not
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1808 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

satisfy the ZVS condition, although it was thought in [5] that the
ZVS can be achieved at any load resistances. Fig. 12(b) shows
waveforms for Lrs = 3.83 μH, Lp = 0.716 μH, C0 = 7.20 nF,
and CS = 11.7 nF, which were obtained from this paper design.
It is seen from this figure that the inverter achieved ZVS.
We confirmed that the inverter with this paper design values
always achieved ZVS at any load resistances by both PSpice
simulations and circuit experiments. In addition, all the ana- Fig. 13. Circuit topology of the class-E inverter for the analysis.
lytical waveforms in Fig. 12 showed quantitative agreements
with experimental and simulation waveforms, which showed 4, the dc voltage drop across the choke inductor LC is zero.
the validity of Fig. 11 and the effectiveness of the presented Therefore, the dc-supply voltage is
analytical expressions. 2π
1
VDD = vS dθ
2π
IX. C ONCLUSION 0

This paper has presented the analytical expressions for A2 BQR  IDD  2 
= θ1 + θ22 + 4π 2 D2 − 2πDθ2
steady-state waveforms, output power, and power conversion 2π 2
efficiency for the class-E inverter outside the class-E ZVS/ZDS + Im [sin(θ1 + φ) − sin φ − θ1 cos φ
switching conditions at a high Q and any duty ratio. By + sin(2πD + φ) − sin(θ2 + φ)
considering the switch-voltage recovery during the MOSFET- 
body-diode ON state, the applicable parameter range of the + (θ2 − 2πD) cos(θ2 + φ)] .
analytical expressions is much wider than that of the previous (45)
analytical expressions. The analytical expressions in this paper
cover all the results in [15]–[17]. It is shown that the analytical Now, L0 is divided into Lr and Lx , where Lr = 1/ω02 C0 , as
predictions agreed with the simulated and experimental results shown in Fig. 13. Therefore, the impedance of the resonant
quantitatively, which indicates the validity of the analytical ex- circuit C0 − Lr is zero at the operating frequency. By applying
pressions. Additionally, the switching-pattern distribution maps Fourier analyses, the voltage amplitudes on R and Lx are
are shown, which can be obtained from the waveform equations 2π
obtained in this paper. From the distribution maps, we can 1
Vo = RIm = vS sin(θ + φ)dθ
obtain the strategies of the quantitative load-network-parameter π
0
adjustment for achieving the class-E ZVS/ZDS conditions and #
the control strategies satisfying the ZVS condition. From the A2 BQR
= IDD [sin(θ1 + φ) − θ1 cos(θ1 + φ) − sin φ
results in this paper, it can be stated that the analytical expres- π
sions obtained in this paper are powerful tools for obtaining a
+ (θ2 − 2πD) cos(2πD + φ)
lot of information on the class-E inverter.
+ sin(2πD + φ) − sin(θ2 + φ)]

1 1
A PPENDIX + Im cos(2θ2+2φ)− cos(2θ1+2φ)
D ERIVATION OF Im , IDD , AND φ 4 4
1
While the switch is in the OFF state, the current through the +cos φ cos(θ1 + φ)+ cos 2φ
4
shunt capacitance is given by (21). While the switch is in the 1
ON state and OFF state, the current through the switch is given − cos2 φ − cos(4πD + 2φ)
4
by (22). The voltage across the switch is given by (44), shown 1
at the bottom of the page. + cos(2θ2 + 2φ)
4
From (44), (19) is obtained. There are three unknown pa- + cos(θ2 + φ) cos(2πD + φ)
rameters in (19), which are IDD , Im , and φ. These three un- $
known parameters can be obtained from the analytical process − cos (θ2 + φ)
2
(46)
described in the following discussion. Because of assumption

⎧
⎪ %θ
⎪
⎪ vS1 = 1
[IDD − Im sin(θ + φ)] dθ, for 0 ≤ θ < θ1
⎪
⎪ ωCS
 θ ⎪
⎨ 0
1 vS2 = 0, for 0 ≤ θ < θ1
vS = iCS dθ = (44)
ωCS ⎪
⎪ %θ
⎪
⎪ vS3 = 1
[IDD − Im sin(θ + φ)] dθ, for θ2 ≤ θ < 2πD
0
⎪
⎪ ωCS
⎩ θ2
vS4 = 0, for 2πD ≤ θ < 2π
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NAGASHIMA et al.: CLASS-E INVERTER OUTSIDE NOMINAL OPERATION 1809

2π [4] I. Boonyaroonate and S. Mori, “Analysis and design of class E isolated
1 dc/dc converter using class E low dv/dt PWM synchronous rectifier,”
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0 [5] M. K. Kazimierczuk and X. T. Bui, “Class-E amplifier with an inductive
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A BQR 166, Apr. 1990.
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 high-power-factor inverter driving piezoelectric ceramic transducer for
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+ (k3 k5 −k2 k4 −k5 k9 −k4 k10 ) sin2 φ cos φ = 0. (52)

By dividing (52) by cos3 φ, (15) can be derived.

R EFERENCES Tomoharu Nagashima (S’11) was born in Saitama,

[1] C. Branas, F. J. Azcondo, and R. Zane, “Power-mode control of multi- Japan, on February 4, 1989. He received the B.E. and
M.E. degrees from Chiba University, Chiba, Japan,
phase resonant electronic ballast,” IEEE Trans. Ind. Electron., vol. 59,
in 2011 and 2012, respectively, where he is currently
no. 4, pp. 1770–1778, Apr. 2012.
working toward the Ph.D. degree.
[2] H. Sekiya, H. Koizumi, S. Mori, I. Sasase, J. Lu, and T. Yahagi,
“FM/PWM control scheme in class DE inverter,” IEEE Trans. Circuits His current research interests are resonant
dc/dc power converters, dc/ac inverters, and high-
Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1250–1260, Jul. 2004.
frequency high-efficiency tuned power amplifiers.
[3] N. O. Sokal and A. D. Sokal, “Class E-A new class of high-efficiency
tuned single-ended switching power amplifiers,” IEEE J. Solid-State Cir-
cuits, vol. SSC-10, no. 3, pp. 168–176, Jun. 1975.
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1810 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 4, APRIL 2014

Xiuqin Wei (S’10–M’12) was born in Fujian, China, Marian K. Kazimierczuk (M’91–SM’91–F’04)
on December 7, 1983. She received the B.E. degree received the M.S., Ph.D., and D.Sci. degrees in elec-
from Fuzhou University, Fuzhou, China, in 2005 tronics engineering from the Department of Elec-
and the Ph.D. degree from Chiba University, Chiba, tronics, Technical University of Warsaw, Warsaw,
Japan, in 2012. Poland, in 1971, 1978, and 1984, respectively.
Since April 2012, she has been with Fukuoka Since 1985, he has been with the Department
University, Fukuoka, Japan, where she is currently an of Electrical Engineering, Wright State University,
Assistant Professor with the Department of Electron- Dayton, OH, USA, where he is currently a Profes-
ics Engineering and Computer Science. Her research sor. His research interests are high-frequency high-
interests include high-frequency power amplifiers. efficiency switching mode tuned power amplifiers,
resonant and PWM dc/dc power converters, dc/ac
inverters, high-frequency rectifiers, electronic ballasts, modeling and control
of converters, high-frequency magnetics, and power semiconductor devices.

Tadashi Suetsugu (S’92–M’95–SM’02) received

the B.E., M.E., and Ph.D. degrees in electrical en- Hiroo Sekiya (S’97–M’01–SM’11) was born in
gineering from the Department of Electrical Engi- Tokyo, Japan, on July 5, 1973. He received the B.E.,
neering, Keio University, Yokohama, Japan, in 1990, M.E., and Ph.D. degrees in electrical engineering
1992, and 1995, respectively. from Keio University, Yokohama, Japan, in 1996,
He is currently a Professor with the Depart- 1998, and 2001, respectively.
ment of Electronics Engineering and Computer Since April 2001, he has been with Chiba Univer-
Science, Fukuoka University, Fukuoka, Japan. His sity, Chiba, Japan, where he is currently an Assistant
research interests are high-frequency high-efficiency Professor with the Graduate School of Advanced
switching-mode tuned power amplifiers, resonant Integration Science. His research interests include
dc/dc power converters, dc/ac inverters, high- high-frequency high-efficiency tuned power ampli-
frequency rectifiers, numerical simulation of switching circuits, and power line fiers, resonant dc/dc power converters, dc/ac invert-
communications. ers, and digital signal processing for wireless communications.

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