50 mA/500 mA, High Efficiency, Ultralow

Power Step-Down Regulator

Data Sheet ADP5300
FEATURES TYPICAL APPLICATION CIRCUIT
Input supply voltage range: 2.15 V to 6.50 V VIN = 2.15 TO 6.50V 2.2µH VOUT
PVIN SW
Operates down to 2.00 V voltage 10µF
Ultralow 180 nA quiescent current ADP5300 10µF
ON
Selectable output voltage of 0.8 V to 5.0 V EN PGND
OFF
±1.5% output accuracy over full temperature range in PWM
PWM mode HYS SYNC/MODE FB

Selectable hysteresis mode or PWM operation mode STOP

VOUTOK
VID0: 1.2V VID8: 2.5V
SW STOP VID1: 1.5V VID9: 2.6V
Output current AGND VID
VID2: 1.8V VID10: 2.7V
VID3: 2.0V VID11: 2.8V
Up to 50 mA in hysteresis mode R0
VID4: 2.1V VID12: 2.9V
EPAD VID5: 2.2V VID13: 3.0V

13366-001
Up to 500 mA in PWM mode VID6: 2.3V VID14: 3.3V
VID7: 2.4V VID15: 3.6V
VOUTOK flag monitors the output voltage
Ultrafast stop switching control Figure 1.
100% duty cycle operation mode
2.0 MHz typical switching frequency in PWM mode with
optional SYNC clock range from 1.5 MHz to 2.5 MHz
Quick output discharge (QOD) option
UVLO, OCP, and TSD protection
10-lead, 3 mm × 3 mm LFCSP
−40°C to +125°C operating temperature range
APPLICATIONS
Energy (gas and water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supplies
GENERAL DESCRIPTION
The ADP5300 is a high efficiency, ultralow quiescent current The ADP5300 contains a VOUTOK flag, which monitors the
step-down regulator that draws only 180 nA quiescent current output voltage and runs at a 2 MHz switching frequency in
to regulate the output. PWM mode. SYNC/MODE can be synchronized to an external
The ADP5300 runs from an input supply voltage range of 2.15 V clock from 1.5 MHz to 2.5 MHz.
to 6.50 V, allowing the use of multiple alkaline or NiMH, Li-Ion The ADP5300 includes an STOP pin that can disable the regulator
cells, or other power sources. The output voltage is selectable from switching temporarily, in this way a quiet system environment
0.8 V to 5.0 V by an external VID resistor and factory fuse. The can be achieved to benefit noise sensitive circuitry, such as data
total solution requires only four tiny external components. conversion, RF data transmission, and analog sensing.
The ADP5300 can operate between hysteresis mode and pulse- Other key features in the ADP5300 include separate enabling,
width modulation (PWM) mode via the SYNC/MODE pin. The QOD, and safety features such as overcurrent protection (OCP),
regulator in hysteresis mode achieves excellent efficiency at a thermal shutdown (TSD), and input undervoltage lockout (UVLO).
power of less than 1 mW and provides up to 50 mA of output The ADP5300 is available in a 10-lead, 3 mm × 3 mm LFCSP
current. The regulator in PWM mode produces a lower output rated for a −40°C to +125°C operating temperature range.
ripple and supplies up to 500 mA of output current. The flexible
configuration capability during operation of the device enables Multifunction pin names may be referenced by their relevant
very efficient power management to meet both the longest battery function only.
life and low system noise requirements.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADP5300 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Short-Circuit Protection............................................................ 15
Applications ....................................................................................... 1 Soft Start ...................................................................................... 15
Typical Application Circuit ............................................................. 1 Startup with Precharged Output .............................................. 15
General Description ......................................................................... 1 100% Duty Operation ................................................................ 15
Revision History ............................................................................... 2 Active Discharge ......................................................................... 15
Detailed Functional Block Diagram .............................................. 3 VOUTOK Function ................................................................... 15
Specifications..................................................................................... 4 Stop Switching ............................................................................ 16
Absolute Maximum Ratings ............................................................ 6 Thermal Shutdown .................................................................... 16
Thermal Resistance ...................................................................... 6 Applications Information .............................................................. 17
ESD Caution .................................................................................. 6 External Component Selection ................................................ 17
Pin Configuration and Function Descriptions ............................. 7 Selecting the Inductor ................................................................ 17
Typical Performance Characteristics ............................................. 8 Output Capacitor........................................................................ 17
Theory of Operation ...................................................................... 14 Input Capacitor ........................................................................... 18
Buck Regulator Operational Modes......................................... 14 Efficiency ..................................................................................... 18
Osillator and Synchronization .................................................. 14 Circuit Board Layout Recommendations ............................... 18
Adjustable and Fixed Output Voltages .................................... 14 Typical Application Circuits ......................................................... 19
Undervoltage Lockout (UVLO) ............................................... 15 Factory Programmable Options ................................................... 20
Enable/Disable ............................................................................ 15 Outline Dimensions ....................................................................... 21
Current Limit .............................................................................. 15 Ordering Guide .......................................................................... 21

REVISION HISTORY
11/2017—Rev A. to Rev. B
Change to Figure 44 ....................................................................... 19
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21

6/2016—Rev. 0 to Rev. A
Changes to Features Section and General Description Section....... 1
Change to SYNC Clock Range Parameter, Table 1 ...................... 4
Change to Table 4 ............................................................................. 7
Change to Oscillator and Synchronization Section ................... 14
Changes to Table 8 .......................................................................... 20
Changes to Ordering Guide .......................................................... 21

8/2015—Revision 0: Initial Version

Rev. B | Page 2 of 21
Data Sheet ADP5300

DETAILED FUNCTIONAL BLOCK DIAGRAM

PVIN
PVIN
VOUTOK 90%
87% DRIVER
ILIM_PWM
FB
SW

ILIM_HYS
CONTROL –0.6A (PWM)
1.2V LOGIC 0A (HYS)
FORCE SLEEP
0.4V
STOP

PWM PVIN

SLOPE Σ
DRIVER
COMPENSATION PGND
STANDBY
0.808V
0.8V

FB

INTERNAL
FEEDBACK
RESISTOR
0.8V VID
DIVIDER
V TO I

MODE
1.2V
0.4V SOFT
AGND
START
EN BAND GAP BIAS
AND
PVIN HOUSEKEEPING
UVLO
2.06V
2.00V
1.2V
0.4V SYNC 2MHz
SYNC/ OSC
MODE MODE
KEEP ALIVE BLOCK

13366-002
Figure 2.

Rev. B | Page 3 of 21
ADP5300 Data Sheet

SPECIFICATIONS
VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.

Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.15 6.50 V
SHUTDOWN CURRENT ISHUTDOWN 18 40 nA VEN = 0 V, −40°C ≤ TJ ≤ +85°C
18 130 nA VEN = 0 V, −40°C ≤ TJ ≤ +125°C
QUIESCENT CURRENT
Operating Quiescent Current in IQ_HYS 180 260 nA −40°C ≤ TJ ≤ +85°C
Hysteresis Mode
180 350 nA −40°C ≤ TJ ≤ +125°C
570 1400 nA 100% duty cycle operation,
VIN = 3.0 V, VOUT set to 3.3 V
Operating Quiescent Current in IQ-HYS2 2.3 3.2 µA VIN = 3.6 V, VSTOP = 3.6 V
Hysteresis Mode
Operating Quiescent Current in PWM IQ_PWM 425 630 µA
Mode
UNDERVOLTAGE LOCKOUT UVLO
UVLO Threshold
Rising VUVLO_RISING 2.06 2.14 V
Falling VUVLO_FALLING 1.90 2.00 V
OSCILLATOR CIRCUIT
Switching Frequency in PWM Mode fSW 1.7 2.0 2.3 MHz
Feedback (FB) Threshold of Frequency VOSC_FOLD 0.3 V
Fold
SYNCHRONIZATION THRESHOLD
SYNC Clock Range SYNCCLOCK 1.5 2.5 MHz
SYNC High Level Threshold SYNCHIGH 1.2 V
SYNC Low Level Threshold SYNCLOW 0.4 V
SYNC Duty Cycle Range SYNCDUTY 100 1/fSW − 150 ns
SYNC/MODE Leakage Current ISYNC_LEAKAGE 50 150 nA VSYNC/MODE = 3.6 V
MODE TRANSITION
Transition Delay from Hysteresis Mode tHYS_TO_PWM 20 Clock cycles SYNC/MODE goes logic high
to PWM Mode from logic low
EN PIN
Input Voltage Threshold
High VIH 1.2 V
Low VIL 0.4 V
Input Leakage Current IEN_LEAKAGE 25 nA
STOP Switching
PWM Switching Stop Delay tSTOP-RISE-DELAY 10 ns STOP goes logic high from low
PWM Switching Resume Delay tSTOP-FALL-DELAY 20 ns STOP goes logic low from high
FB PIN
Output Options by VID Resistor VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory
options
PWM Mode
Fixed VID Code Voltage Accuracy VFB_PWM_FIX −0.6 +0.6 % TJ = 25°C, output voltage setting
via factory fuse
−1.2 +1.2 % −40°C ≤ TJ ≤ +125°C
Adjustable VID Code Voltage VFB_PWM_ADJ −1.5 +1.5 % Output voltage setting via VID
Accuracy resistor

Rev. B | Page 4 of 21
Data Sheet ADP5300
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Hysteresis Mode
Fixed VID Code Threshold Accuracy VFB_HYS_FIX −0.75 +0.75 % TJ = 25°C
from Active Mode to Standby Mode
−2.5 +2.5 % −40°C ≤ TJ ≤ +125°C
Adjustable VID Code Threshold VFB_HYS_ADJ −3 +3 % −40°C ≤ TJ ≤ +125°C
Accuracy from Active Mode to
Standby Mode
Hysteresis of Threshold Accuracy VFB_HYS (HYS) 1 %
from Active Mode to Standby Mode
Feedback Bias Current IFB 66 95 nA Output Option 0, VOUT = 2.5 V
25 45 nA Output Option 1, VOUT = 1.3 V
SW PIN
High-Side Power FET On Resistance RDS (ON) H 386 520 mΩ Pin to pin measurement
Low-Side Power FET On Resistance RDS (ON) L 299 470 mΩ Pin to pin measurement
Current Limit in PWM Mode ILIM_PWM 800 1000 1200 mA SYNC/MODE = high
Peak Current in Hysteresis Mode ILIM_HYS 265 mA SYNC/MODE = low
Minimum On Time tMIN_ON 40 70 ns
VOUTOK PIN
Monitor Threshold VOUTOK (RISE) 87 90 93 %
Monitor Hysteresis VOUTOK (HYS) 3 %
Monitor Rising Delay tVOUTOK_RISE 40 µs
Monitor Falling Delay tVOUTOK_FALL 10 µs
Leakage Current IVOUTOK_LEAKAGE 0.1 1 µA
Output Low Voltage VOUTOK_LOW 50 80 mV IVOUTOK = 100 µA
SOFT START
Default Soft Start Time tSS 350 µs Factory trim, 1 bit (350 µs and
2800 µs)
Start-Up Delay tSTART_DELAY 2 ms Delay from the EN pin being
pulled high
COUT DISCHARGE SWITCH ON RESISTANCE RDIS 290 Ω
THERMAL SHUTDOWN
Threshold TSHDN 142 °C
Hysteresis THYS 127 °C

Rev. B | Page 5 of 21
ADP5300 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. THERMAL RESISTANCE
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
PVIN to PGND −0.3 V to +7 V soldered in a circuit board for surface-mount packages. θJC is
SW to PGND −0.3 V to PVIN + 0.3 V the thermal resistance from the operating portion of the device
FB to AGND −0.3 V to +7 V to the outside surface of the package (case) closest to the device
VID to AGND −0.3 V to +7 V mounting area.
EN to AGND −0.3 V to +7 V
Table 3. Thermal Resistance
VOUTOK to AGND −0.3 V to +7 V
SYNC/MODE to AGND −0.3 V to +7 V Package Type θJA θJC Unit
STOP to AGND −0.3 V to +7 V 10-Lead, 3 mm × 3 mm LFCSP 57 0.86 °C/W
PGND to AGND −0.3 V to +0.3 V
Storage Temperate Range −65°C to +150°C
ESD CAUTION
Operating Temperature Range −40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. B | Page 6 of 21
Data Sheet ADP5300

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EN 1 10 PVIN
STOP 2 9 SW
ADP5300
SYNC/MODE 3 TOP VIEW 8 PGND
(Not to Scale)
VID 4 7 AGND
FB 5 6 VOUTOK

NOTES

13366-003
1. THE EXPOSED PAD MUST BE SOLDERED TO A
LARGE EXTERNAL COPPER GROUND PLANE
UNDERNEATH THE IC FOR THERMAL DISSIPATION.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 EN Enable Input for the Regulator. Set to logic low to disable the regulator.
2 STOP Stop Switching Input Signal. When this pin is logic high, the regulator stops the regulator switching. When this
pin is logic low, the regulator resumes the regulator switching.
3 SYNC/MODE Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock,
connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz.
PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM mode.
When this pin is logic low, the regulator operates in hysteresis mode.
4 VID Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the output
voltage of the regulator (see Table 5).
5 FB Feedback Sensing Input for the Regulator.
6 VOUTOK Output Power-Good Signal. This open-drain output is the power-good signal for the output voltage.
7 AGND Analog Ground.
8 PGND Power Ground.
9 SW Switching Node Output for the Regulator.
10 PVIN Power Input for the Regulator.
EPAD Exposed Pad. The exposed pad must be soldered to a large external copper ground plane underneath the IC for
thermal dissipation.

Rev. B | Page 7 of 21
ADP5300 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.6 V, VOUT = 2.5 V, L = 2.2 µH, CIN = COUT = 10 µF, fSW = 2 MHz, TA = 25°C, unless otherwise noted.
100 100

90
90

80
80
EFFICIENCY (%)

EFFICIENCY (%)
70
70
60
VIN = 2.5V 60 VIN = 2.5V
50 VIN = 3.0V VIN = 3.0V
VIN = 3.6V VIN = 3.6V
VIN = 4.2V 50 VIN = 4.2V
40 VIN = 5.0V VIN = 5.0V
VIN = 6.0V VIN = 6.0V
30 40
13366-004

13366-007
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V

100 100

90
90

80
EFFICIENCY (%)

EFFICIENCY (%)

80

70

70
60 VIN = 2.5V
VIN = 3.0V VIN = 3.0V
VIN = 3.6V VIN = 3.6V
VIN = 4.2V 60 VIN = 4.2V
50
VIN = 5.0V VIN = 5.0V
VIN = 6.0V VIN = 6.0V
40 50
13366-005

13366-008
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V

100 100

90

90 80

70
EFFICIENCY (%)

EFFICIENCY (%)

80 60

50

70 40
VIN = 2.5V
30 VIN = 3.0V
VIN = 3.6V VIN = 3.6V
60 VIN = 4.2V 20
VIN = 4.2V
VIN = 5.0V VIN = 5.0V
10
VIN = 6.0V VIN = 6.0V
50 0
13366-009
13366-006

0.001 0.01 0.1 1 10 0 100 200 300 400 500

LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V Figure 9. PWM Efficiency vs. Load Current, VOUT = 1.2 V

Rev. B | Page 8 of 21
Data Sheet ADP5300
100 100

90 90

80 80

70 70
EFFICIENCY (%)

EFFICIENCY (%)
60 60

50 50

40 40
VIN = 2.5V VIN = 2.5V
30 VIN = 3.0V 30 VIN = 3.0V
VIN = 3.6V VIN = 3.6V
20 20
VIN = 4.2V VIN = 4.2V
10 VIN = 5.0V 10 VIN = 5.0V
VIN = 6.0V VIN = 6.0V
0 0

13366-010

13366-013
0 100 200 300 400 500 0 100 200 300 400 500
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 10. PWM Efficiency vs. Load Current, VOUT = 1.5 V Figure 13. PWM Efficiency vs. Load Current, VOUT = 1.8 V

100 100

90 90

80 80

70 70
EFFICIENCY (%)

EFFICIENCY (%)
60 60

50 50

40 40

30 VIN = 3.0V 30
VIN = 3.6V VIN = 3.6V
20 20 VIN = 4.2V
VIN = 4.2V
VIN = 5.0V VIN = 5.0V
10 10
VIN = 6.0V VIN = 6.0V
0 0

13366-014
13366-011

0 100 200 300 400 500 0 100 200 300 400 500
LOAD CURRENT (mA) LOAD CURRENT (mA)

Figure 11. PWM Efficiency vs. Load Current, VOUT = 2.5 V Figure 14. PWM Efficiency vs. Load Current, VOUT = 3.3 V

160 350

140 –40ºC –40ºC

+25ºC +25ºC
300 +85ºC
+85ºC
QUIESCENT CURRENT (nA)
SHUTDOWN CURRENT (nA)

120 +125ºC +125ºC

100 250

80

200
60

40
150

20

0 100
13366-015
13366-012

2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
VIN (V) VIN (V)

Figure 12. Shutdown Current vs. VIN, EN = Low Figure 15. Hysteresis Quiescent Current vs. VIN, SYNC/MODE = Low

Rev. B | Page 9 of 21
ADP5300 Data Sheet
801 810

808
ACTIVE TO STANDBY
806

FEEDBACK VOLTAGE (mV)

FEEDBACK VOLTAGE (mV)

800
804
STANDBY TO ACTIVE
802
799
800

798

798 796

794

792

13366-019
797

13366-016
–40 25 85 125 –40 25 85 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 16. Feedback Voltage vs. Temperature, PWM Mode Figure 19. Feedback Voltage vs. Temperature, Hysteresis Mode

700 400

–40ºC –40ºC
600 +25ºC 350 +25ºC
+125ºC +125ºC
HIGH-SIDE RDS (ON) H (mΩ)

LOW-SIDE RDS (ON) L (mΩ)

500 300

400 250

300 200

200 150

100 100
13366-017

13366-020
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
VIN (V) VIN (V)

Figure 17. High-Side RDS (ON) H vs. VIN Figure 20. Low-Side RDS (ON) L vs. VIN

1090 1200

1150 –40ºC
+25ºC
1040 +125ºC
PEAK CURRENT LIMIT (mA)

PEAK CURRENT LIMIT (mA)

1100

990 1050

1000

940
950

900
890

850
13366-018

840 800
13366-021

–40 25 85 125 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
TEMPERATURE (°C) VIN (V)

Figure 18. Peak Current Limit vs. Temperature Figure 21. Peak Current Limit vs. VIN

Rev. B | Page 10 of 21
Data Sheet ADP5300
2.10 2.3

–40ºC
2.08
2.2 +25ºC

SWITCHING FREQUENCY (kHz)

RISING +125ºC
2.06
UVLO THRESHOLD (V)

2.1

2.04
2.0
2.02

1.9
2.00 FALLING

1.98 1.8

1.96

13366-022
1.7

13366-025
–40 25 85 125 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
TEMPERATURE (°C) VIN (V)

Figure 22. UVLO Threshold, Rising and Falling vs. Temperature Figure 25. Switching Frequency vs. VIN

VOUT 1

VOUT (AC)
1

SW
IL

2 4

IL

4 2

SW
13366-023

13366-026
CH1 100mV CH2 2.00V M 200µs A CH4 140mA CH1 10.0mV CH2 2.00V M 400ns A CH2 2.72V
CH4 500mA Ω T 39.60% CH4 200mA Ω T 90.60%

Figure 23. Steady Waveform of Hysteresis Mode, ILOAD = 1 mA Figure 26. Steady Waveform of PWM Mode, ILOAD = 300 mA
(IL is the Inductor Current) (IL is the Inductor Current)

VIN VIN

3 VOUT

VOUT
1 1
IL IL
4 4

SW SW
2
2
13366-024

13366-027

CH1 1.00V CH2 5.00V M 200µs A CH1 1.22V CH1 500mV CH2 5.00V M 100µs A CH1 1.05V
CH3 2.00V CH4 500mA Ω T 50.60% CH3 2.00V CH4 500mA Ω T 40.00%

Figure 24. Soft Start, ILOAD = 300 mA Figure 27. Soft Start with Precharge Function
(IL is the Inductor Current) (IL is the Inductor Current)

Rev. B | Page 11 of 21
ADP5300 Data Sheet

VOUT (AC)

1 1
VOUT (AC)

IOUT

IOUT
4 4

13366-028

13366-031
CH1 50.0mV M 200µs A CH4 111mA CH1 50.0mV M 200µs A CH4 308mA
CH4 50.0mA Ω T 20.80% CH4 200mA Ω T 20.40%

Figure 28. Load Transient of Hysteresis Mode, ILOAD from 0 mA to 50 mA Figure 31. Load Transient of PWM Mode, ILOAD from 125 mA to 375 mA

1 1
VOUT (AC) VOUT (AC)

VIN VIN

IL
4 3
IL
4 SW

2 2
SW
13366-029

13366-032
CH1 50.0mV CH2 5.00V M 2.00ms A CH3 4.72V CH1 10.0mV CH2 5.00V M 2.00ms A CH3 4.28V
CH3 2.00V CH4 500mA Ω T 30.00% CH3 2.00V CH4 500mA Ω T 30.20%

Figure 29. Line Transient of Hysteresis Mode, ILOAD = 10 µA Figure 32. Line Transient of PWM Mode, ILOAD = 500 mA
(IL is the Inductor Current) (IL is the Inductor Current)

VIN

VOUT
VOUT 1
VOUTOK
3

1
IL SW
4 2
13366-033
13366-030

CH1 1.00V M 10.0ms A CH3 4.80V CH1 1.00V CH2 2.00V M 200µs A CH1 1.32V
CH3 1.00V CH4 200mA Ω T 40.20% CH3 1.00V T 40.00%

Figure 30. Input Voltage Ramp Up and Ramp Down in Hysteresis Mode Figure 33. VOUTOK Function
(IL is the Inductor Current)

Rev. B | Page 12 of 21
Data Sheet ADP5300
VOUT

VOUT
1 1
IL
IL

4 4

SW SW

2 2

13366-036
13366-034
CH1 2.00V CH2 2.00V M 10.0µs A CH1 1.44V CH1 2.00V CH2 2.00V M 1.00ms A CH1 1.44V
CH4 500mA Ω T 40.20% CH4 500mA Ω T 40.20%

Figure 34. Output Short Protection Figure 37. Output Short Recovery
(IL is the Inductor Current) (IL is the Inductor Current)

EN

1
SYNC/
MODE 3 VOUT

SW
2 1

2
SW

13366-037
13366-035

CH1 2.00V CH2 2.00V M 400ns A CH2 1.40V CH1 1.00V CH2 2.00V M 4.00ms A CH3 1.64V
T 50.00% CH3 2.00V T 40.00%

Figure 35. Synchronized to 2.5 MHz Figure 38. Quick Output Discharge Function

1
VOUT VOUT
1

SYNC/MODE VSTOP
3 3

SW
SW

2 2
13366-137
13366-136

CH1 100mV CH2 2.00V M 20.0µs A CH3 1.56V CH1 2.00V B

W CH2 2.00V M 100ms A CH3 520mV
CH3 2.00V BW T 39.80% CH3 2.00V B
W

Figure 36. Hysteresis Mode to PWM Mode with 10 mA Load Current Figure 39. STOP Switching Function

Rev. B | Page 13 of 21
ADP5300 Data Sheet

THEORY OF OPERATION
The ADP5300 is a high efficient, ultralow quiescent current, The user can alternate between hysteresis mode and PWM mode
step-down regulator in a 10-lead LFCSP package to meet during operation. The flexible configuration capability during
demanding performance and board space requirements. The operation of the device enables efficient power management to
device enables direct connection to a wide input voltage range of meet high efficiency and low output ripple requirements when
2.15 V to 6.50 V, allowing the use of multiple alkaline/NiMH or, the system switches between active mode and standby mode.
Li-Ion cells and other power sources.
OSILLATOR AND SYNCHRONIZATION
BUCK REGULATOR OPERATIONAL MODES
The ADP5300 operates at a 2 MHz switching frequency typical
PWM Mode in PWM operation mode.
In PWM mode, the buck regulator in the ADP5300 operates at
a fixed frequency that is set by an internal oscillator. At the start The switching frequency of the ADP5300 can be synchronized
of each oscillator cycle, the high-side MOSFET switch turns on to an external clock with a frequency range from 1.5 MHz to
and sends a positive voltage across the inductor. The inductor 2.5 MHz. The ADP5300 automatically detects the presence of an
current increases until the current sense signal exceeds the peak external clock applied to the SYNC/MODE pin, and the switching
inductor current threshold, which turns off the high-side MOSFET frequency transitions to the frequency of the external clock.
switch. This threshold is set by the error amplifier output. During When the external clock signal stops, the device automatically
the high-side MOSFET off time, the inductor current decreases switches back to the internal clock.
through the low-side MOSFET until the next oscillator clock ADJUSTABLE AND FIXED OUTPUT VOLTAGES
pulse starts a new cycle. The ADP5300 provides adjustable output voltage settings by
Hysteresis Mode connecting one resistor through the VID pin to AGND. The
In hysteresis mode, the buck regulator in the ADP5300 charges VID detection circuitry works in the start-up period, and the
the output voltage slightly higher than its nominal output voltage voltage ID code is sampled and held in the internal register and
with PWM pulses by regulating the constant peak inductor does not change until the next power recycle. Furthermore, the
current. When the output voltage increases until the output ADP5300 provides a fixed output voltage programmed via the
sense signal exceeds the hysteresis upper threshold, the regulator factory fuse. In this condition, connect the VID pin to the
enters standby mode. In standby mode, the high-side and low-side PVIN pin.
MOSFETs and a majority of the circuitry are disabled to allow a For the output voltage settings, the feedback resistor divider is
low quiescent current as well as high efficiency performance. built into the ADP5300, and the feedback pin (FB) must be tied
During standby mode, the output capacitor supplies energy into directly to the output. An ultralow power voltage reference and
the load, and the output voltage decreases until it falls below the an integrated high impedance (50 MΩ typical) feedback divider
hysteresis comparator lower threshold. The buck regulator wakes network contribute to the low quiescent current. Table 5 lists the
up and generates the PWM pulses to charge the output again. output voltage options by the VID pin configurations. A 1%
accuracy resistor through VID to ground is recommended.
Because the output voltage occasionally enters standby mode
and then recovers, the output voltage ripple in hysteresis mode Table 5. Output Voltage (VOUT) Options by the VID Pin
is larger than the ripple in PWM mode. VOUT (V)
Mode Selection VID Configuration Factory Option 0 Factory Option 1
Short to Ground 3.0 3.1
The ADP5300 includes the SYNC/MODE pin to allow flexible
Short to PVIN 2.5 1.3
configuration in hysteresis mode or PWM mode.
RVID = 499 kΩ 3.6 5.0
When a logic high level is applied to the SYNC/MODE pin, the RVID = 316 kΩ 3.3 4.5
buck regulator is forced to operate in PWM mode. In PWM mode, RVID = 226 kΩ 2.9 4.2
the regulator can supply up to 500 mA of output current. The RVID = 174 kΩ 2.8 3.9
regulator can provide lower output ripple and output noise in RVID = 127 kΩ 2.7 3.4
PWM mode, which is useful for noise sensitive applications. RVID = 97.6 kΩ 2.6 3.2
When a logic low level is applied to the SYNC/MODE pin, the RVID = 76.8 kΩ 2.4 1.9
buck regulator is forced to operate in hysteresis mode. In hysteresis RVID = 56.2 kΩ 2.3 1.7
mode, the regulator draws only 180 nA of quiescent current RVID = 43 kΩ 2.2 1.6
typical to regulate the output under zero load, which allows the RVID = 32.4 kΩ 2.1 1.4
regulator to act as a keep-alive power supply in a battery-powered RVID = 25.5 kΩ 2.0 1.1
system. In hysteresis mode, the regulator supplies up to 50 mA of RVID = 19.6 kΩ 1.8 1.0
output current with a relatively large output ripple compared to RVID = 15 kΩ 1.5 0.9
PWM mode. RVID = 11.8 kΩ 1.2 0.8

Rev. B | Page 14 of 21
Data Sheet ADP5300
UNDERVOLTAGE LOCKOUT (UVLO) STARTUP WITH PRECHARGED OUTPUT
The undervoltage lockout circuitry monitors the input voltage The buck regulators in the ADP5300 include a precharged start-up
level on the PVIN pin. If the input voltage falls below 2.00 V feature to protect the low-side MOSFET from damage during
(typical), the regulator turns off. After the input voltage rises startup. If the output voltage is precharged before the regulator
above 2.06 V (typical), the soft start period initiates, and when turns on, the regulator prevents reverse inductor current, which
the EN pin is high, the regulator enables. discharges the output capacitor, until the internal soft start
reference voltage exceeds the precharged voltage on the FB pin.
ENABLE/DISABLE
The ADP5300 includes a separate enable (EN) pin. A logic high 100% DUTY OPERATION
on the EN pin starts the regulator. Due to the low quiescent current When the input voltage approaches the output voltage, the
design, it is typical for the regulator to start switching after a ADP5300 stops switching and enters 100% duty cycle operation. It
delay of a few milliseconds from the EN pin being pulled high. connects the output via the inductor and the internal high-side
A logic low on the EN pin immediately disables the regulator power switch to the input. When the input voltage is charged
and brings the regulator into extremely low current consumption. again and the required duty cycle falls to 95% typical, the buck
immediately restarts switching and regulation without allowing
CURRENT LIMIT overshoot on the output voltage. In hysteresis mode, the ADP5300
The buck regulators in the ADP5300 have protection circuitry draws an ultralow quiescent current of only 570 nA typical
that limits the direction and the amount of current to a certain during 100% duty cycle operation.
level that flows through the high-side MOSFET and the low- ACTIVE DISCHARGE
side MOSFET in cycle-by-cycle mode. The positive current
limit on the high-side MOSFET limits the amount of current The regulator in the ADP5300 integrates an optional, factory
that can flow from the input to the output. The negative current programmable discharge switch from the switching node to
limit on the low-side MOSFET prevents the inductor current ground. This switch turns on when its associated regulator is
from reversing direction and flowing out of the load. disabled, which helps discharge the output capacitor quickly.
The typical value of the discharge switch is 290 Ω for the
SHORT-CIRCUIT PROTECTION regulator.
The buck regulators in the ADP5300 include frequency foldback to By default, the discharge function is not enabled. The factory
prevent current runaway on a hard short. When the output voltage fuse can enable the active discharge function.
at the feedback (FB) pin falls below 0.3 V typical, indicating the
possibility of a hard short at the output, the switching frequency VOUTOK FUNCTION
(in PWM mode) is reduced to one-fourth of the internal The ADP5300 includes an open-drain, power-good output
oscillator frequency. The reduction in the switching frequency (VOUTOK pin) that is active high when the buck regulator
allows more time for the inductor to discharge, preventing a operates normally. By default, the VOUTOK pin monitors the
runaway of output current. output voltage. A logic high on the VOUTOK pin indicates that
the regulated output voltage of the buck regulator is above 90%
SOFT START
(typical) of its nominal output. When the regulated output voltage
The ADP5300 has an internal soft start function that ramps up of the buck regulator falls below 87% (typical) of its nominal
the output voltage in a controlled manner upon startup, thereby output for a delay time greater than approximately 10 µs, the
limiting the inrush current. This feature prevents possible input VOUTOK pin goes low.
voltage drops when a battery or a high impedance power source
is connected to the input of the device. The default typical soft
start time is 350 µs for the regulator.
A different soft start time (2800 µs) can be programmed for
ADP5300 by the factory fuse.

Rev. B | Page 15 of 21
ADP5300 Data Sheet
STOP SWITCHING 2.540V

The ADP5300 includes a stop input pin (STOP) that can 2.500V
temporarily stop the regulator switching in hysteresis mode. DC TO DC OUTPUT

When a logic high level is applied to the STOP pin, the buck 2.175V TO VOUTOK THRESHOLD

regulator is forced to stop switching immediately. When a logic

DC TO DC SWITCHING
low level is applied to the STOP pin, the buck regulator resumes
switching. Note that tens of nanoseconds delay time exists from 10ms OF mA

when the STOP signal goes high to fully stop switching. 2µA
OUTPUT LOAD

In some battery-powered systems, the microcontroller unit STOP SIGNAL

(MCU) can command the regulator to stop switching via the

13366-040
VOUTOK FLAG
STOP signal, and the regulator then relies on the output
capacitor to supply the load. In this period, a quiet system
environment can be achieved which benefits the noise sensitive Figure 40. STOP Switching Operation Status
circuitry, such as data conversion, RF data transmission, and THERMAL SHUTDOWN
analog sensing. After the noise sensitive circuitry completes its
If the ADP5300 junction temperature exceeds 142°C, the thermal
task, the MCU can control the regulator and resume switching
shutdown circuit turns off the IC except for the internal linear
regulation mode. If needed, the VOUTOK signal can monitor
regulator. Extreme junction temperatures can be the result of
the output voltage in the event it dips too low to latch up the
high current operation, poor circuit board design, or high ambient
system. Figure 40 shows the STOP switching operation status in
temperature. A 15°C hysteresis is included so that the ADP5300
ADP5300.
does not return to operation after thermal shutdown until the
When the regulator is enabled with EN pin pulled high, the junction temperature falls below 127°C. When the device exits
STOP signal control is valid, and when EN pin is logic low, the thermal shutdown, a soft start initiates for each enabled channel.
STOP signal is ignored.

Rev. B | Page 16 of 21
Data Sheet ADP5300

APPLICATIONS INFORMATION
This section describes the external components selection for the A minimum requirement of the dc current rating of the inductor
ADP5300. The typical application circuit is shown in Figure 41. is for it to be equal to the maximum load current plus half of the
VIN = 2.15V TO 6.50V 2.2µH VOUT = 1.8V
inductor current ripple (ΔIL), as shown by the following equations:
PVIN SW
10µF  1 – VOUT 
MLCC ADP5300 10µF  
VIN 

MLCC
ΔI L  VOUT
EN PGND R2
 L  f SW 
1MΩ  
 
SYNC/MODE
FB
I PK  I LOAD(MAX)   L 
ΔI
STOP
VOUTOK  2 
AGND VID
R1
Use the inductor series from the different vendors shown in Table 6.
19.6kΩ
EPAD
OUTPUT CAPACITOR

13366-041
Output capacitance is required to minimize the voltage overshoot,
Figure 41. Typical Application Circuit
the voltage undershoot, and the ripple voltage present on the
EXTERNAL COMPONENT SELECTION output. Capacitors with low equivalent series resistance (ESR)
The ADP5300 is optimized for operation with a 2.2 μH values produce the lowest output ripple. Furthermore, use
inductor and 10 μF output capacitors for various output capacitors such as X5R and X7R dielectric capacitors. Do not
voltages using the closed-loop compensation and adaptive slope use Y5V and Z5U capacitors, because they are unsuitable
compensation circuits. The selection of components depends choices due to their large capacitance variation over temperature
on the efficiency, the load current transient, and other application and their dc bias voltage changes. Because ESR is important,
requirements. The trade-offs among performance parameters, select the capacitor using the following equation:
such as efficiency and transient response, are made by varying V RIPPLE
ESR COUT 
the choice of external components. I L
SELECTING THE INDUCTOR where:
The high switching frequency of the ADP5300 allows the use of ESRCOUT is the ESR of the chosen capacitor.
small surface-mount power inductors. The dc resistance (DCR) VRIPPLE is the peak-to-peak output voltage ripple.
value of the selected inductor affects efficiency. In addition, it is Increasing the output capacitor value has no effect on stability
recommended to select a multilayer inductor rather than a and may reduce output ripple and enhance load transient response.
magnetic iron inductor because the high switching frequency When choosing the output capacitor value, it is important to
increases the core temperature rise and enlarges the core loss. account for the loss of capacitance due to output voltage dc bias.
Use the capacitor series from the different vendors shown in Table 7.

Table 6. Recommended Inductors

Vendor Model Inductance (μH) Dimensions (mm) DCR (mΩ) ISAT1 (A)
TDK MLP2016V2R2MT0S1 2.2 2.0 × 1.6 × 0.85 280 1.0
Wurth 74479889222 2.2 2.5 × 2.0 × 1.2 250 1.7
Coilcraft LPS3314-222MR 2.2 3.3 × 3.3 × 1.3 100 1.5
1
ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.

Table 7. Input and Output Capacitors

Vendor Model Capacitance (μF) Size
Murata GRM188D71A106MA73 10 0603
Murata GRM21BR71A106KE51 10 0805
Murata GRM31CR71A106KA01 10 1206

Rev. B | Page 17 of 21
ADP5300 Data Sheet
INPUT CAPACITOR Driver Losses
An input capacitor is required to reduce the input voltage Driver losses are associated with the current drawn by the driver to
ripple, input ripple current, and source impedance. Place the turn on and turn off the power devices at the switching frequency.
input capacitor as close as possible to the PVIN pin. A low ESR Each time a power device gate is turned on and turned off, the
X7R or X5R capacitor is highly recommended to minimize the driver transfers a charge from the input supply to the gate, and
input voltage ripple. Use the following equation to determine then from the gate to ground.
the rms input current: Estimate driver losses using the following equation:
VOUT (VIN − VOUT ) PDRIVER = (CGATE_H + CGATE_L) × VIN2 × fSW
I RMS ≥ I LOAD( MAX )
VIN where:
CGATE_H is the gate capacitance of the internal high-side switch.
For most applications, a 10 µF capacitor is sufficient. The input
CGATE_L is the gate capacitance of the internal low-side switch.
capacitor can be increased without any limit for improved input
fSW is the switching frequency in PWM mode.
voltage filtering.
The typical values for the gate capacitances are 69 pF for CGATE_H
EFFICIENCY and 31 pF for CGATE_L.
Efficiency is the ratio of output power to input power. The high
Transition Losses
efficiency of the ADP5300 has two distinct advantages. First,
only a small amount of power is lost in the dc-to-dc converter Transition losses occur because the P-channel switch cannot
package, which in turn reduces thermal constraints. Second, the turn on or turn off instantaneously. In the middle of a switch
high efficiency delivers the maximum output power for the node transition, the power switch provides all of the inductor
given input power, thereby extending battery life in portable current. The source to drain voltage of the power switch is half
applications. of the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
Power Switch Conduction Losses
twice for each switching cycle.
Power switch dc conduction losses are caused by the flow of
Use the following equation to estimate transition losses:
output current through the high-side, P-channel power switch
and the low-side, N-channel synchronous rectifier, which have PTRAN = VIN/2 × IOUT × (tR + tF) × fSW
internal resistances (RDS (ON)) associated with them. The amount where:
of power loss is approximated by tR is the rise time of the SW node.
PSW_COND = (RDS (ON) H × D + RDS (ON) L × (1 − D)) × IOUT2 tF is the fall time of the SW node.
where: The typical value for the rise and fall times, tR and tF, is 2 ns.
VOUT CIRCUIT BOARD LAYOUT RECOMMENDATIONS
D=
VIN
10µF
The internal resistance of the power switches increases with 10V/XR5
0603
temperature and with the input voltage decrease.
Inductor Losses
Inductor conduction losses are caused by the flow of current
through the inductor, which has an internal DCR associated
L1–2.2µH

ADP5300
0603

with it. Larger size inductors have smaller DCR, which can TOP VIEW
5.7
decrease inductor conduction losses. Inductor core losses relate
to the magnetic permeability of the core material. Because the
ADP5300 is a high switching frequency dc-to-dc regulator,
shielded ferrite core material is recommended because of its low
core losses and low electromagnetic interference (EMI). 10µF
6.3V/XR5
0603
To estimate the total amount of power lost in the inductor, use
13366-042

the following equation:

4.6
PL = DCR × IOUT2 + Core Losses
Figure 42. Typical PCB Layout

Rev. B | Page 18 of 21
Data Sheet ADP5300

TYPICAL APPLICATION CIRCUITS

The ADP5300 can be used as a keep-alive, ultralow power step- controlled by a microcontroller or a processor (see Figure 44).
down regulator to extend the battery life (see Figure 43), and as The STOP switching function can achieve a quiet system
a battery-powered equipment or wireless sensor network environment for a noise sensitive application.

VIN = 3.0V TO 4.2V 2.2µH VOUT = 3.0V

PVIN SW ADC/RF/AFE
Li-Ion
BATTERY 10µF
ADP5300 10µF

EN PGND

VID FB R1
1MΩ
MCU
VOUTOK
(ALWAYS ON)
STOP
SYNC/MODE
AGND

13366-043
Figure 43. Typical ADP5300 Application with Li-Ion Battery and STOP Switching Functionality

VIN = 2.0V TO 3.0V 2.2µH VOUT = 1.8V

PVIN SW ADC/RF/AFE
TWO ALKALINE
OR NiMH 10µF
ADP5300 10µF
BATTERIES

EN PGND

VID FB R1
R1 1MΩ
19.6kΩ MCU
1% VOUTOK
(ALWAYS ON)
STOP
SYNC/MODE
AGND

13366-044
Figure 44. Typical ADP5300 Application with Two Alkaline/NiMH Batteries

Rev. B | Page 19 of 21
ADP5300 Data Sheet

FACTORY PROGRAMMABLE OPTIONS

To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative.

Table 8. Output Voltage VID Setting Options

Option Description
Option 0 VID resistor to set the output voltage as: 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, 3.6 V, or 3.3 V.
Option 1 VID resistor to set the output voltage as: 0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V, 3.1 V, 3.2 V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, or 5.0 V.

Table 9. Output Discharge Functionality Options

Option Description
Option 0 Output discharge function disabled for buck regulator (default)
Option 1 Output discharge function enabled form buck regulator

Table 10. Soft-Start Timer Options

Option Description
Option 0 350 µs (default)
Option 1 2800 µs

Rev. B | Page 20 of 21
Data Sheet ADP5300

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)

2.48
2.38
3.10
2.23
3.00 SQ
2.90 0.50 BSC
6 10

PIN 1 INDEX EXPOSED 1.74

AREA PAD
1.64
0.50 1.49
0.40
0.30
5 1 0.20 MIN
PIN 1
TOP VIEW BOTTOM VIE W INDIC ATOR AREA OPTIONS
(SEE DETAIL A)

0.80 FOR PROPER CONNECTION OF

0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.70 0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
0.30

02-07-2017-C
PLANE 0.20 REF
PKG-004362

0.25
0.20

Figure 45. 10-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters

ORDERING GUIDE
Package
Model 1 Temperature Range Package Description Option
ADP5300ACPZ-1-R7 −40°C to +125°C 10-Lead LFCSP, Output Voltage Option 0 with Output Discharge CP-10-9
ADP5300ACPZ-2-R7 −40°C to +125°C 10-Lead LFCSP, Output Voltage Option 0 without Output Discharge CP-10-9
ADP5300ACPZ-3-R7 −40°C to +125°C 10-Lead LFCSP, Output Voltage Option 1 without Output Discharge CP-10-9
ADP5300ACPZ-4-R7 −40°C to +125°C 10-Lead LFCSP, 3.6 V Fixed Output without Output Discharge, 2800 μs Soft Start Time CP-10-9
ADP5300-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13366-0-11/17(B)

Rev. B | Page 21 of 21