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SRAM

The document provides an in-depth explanation of the 6T SRAM cell structure, its operations including read, write, and hold, and the importance of transistor sizing for stability. It discusses the trade-offs between read stability and write-ability, as well as techniques to enhance SRAM performance and the impact of reducing bitline capacitance. Key parameters such as cell ratio and pull-up ratio are highlighted for effective design.

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1 views

SRAM

The document provides an in-depth explanation of the 6T SRAM cell structure, its operations including read, write, and hold, and the importance of transistor sizing for stability. It discusses the trade-offs between read stability and write-ability, as well as techniques to enhance SRAM performance and the impact of reducing bitline capacitance. Key parameters such as cell ratio and pull-up ratio are highlighted for effective design.

Uploaded by

p23.anurag
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital CMOS Design [IEC-405]

Prof. R.K. Chauhan (MMMUT)

6T-SRAM Cell

Q1. Draw and explain the basic structure of a 6T SRAM cell.


Answer: The 6T SRAM (Static Random Access Memory) cell is a fundamental digital memory
component composed of six transistors: four forming two cross-coupled inverters that store a
single bit, and two access transistors that control read/write operations. In the figure given
below shows two cross-coupled CMOS inverters (4 transistors: N1, N2, P1, P2) and Two
access transistors (A1, A2). Two bitlines (BL, BLB) are connected to the source of access
transistors and One wordline (WL) connected to the gate of access transistors. The cell stores
a single bit at nodes Q (data) and Qn (complementary data).

Q2. Mention the control signal status during Read/Write and hold operations.
Answer:
Control Various Operations
Signal Hold Read-0 Read-1 Write-0 Write-1
Word Line 0 1 1 1 1
(WL)
Bitline X 1 1 0 1
(BL)
Bitline bar X 1 1 1 0
(BLB)

1
Digital CMOS Design [IEC-405]
Prof. R.K. Chauhan (MMMUT)

Q3. What happens during the hold operation of a 6T SRAM cell?


Answer: During hold mode:
• The wordline (WL) is kept low (0V), because of which the access transistors (A1, A2)
are turned OFF, the cell is disconnected from the bitlines (BL,BLB).
• The cross-coupled inverters maintain the stored value through positive feedback.
The cell consumes minimal static power (only leakage current) during hold operations.

Q4. How does the read operation work in a 6T SRAM cell?


Answer: The read operation follows these steps:
• Wordline (WL) is activated (high) ; Bitlines (BL, BLB) are precharged to VDD
• Access transistors (A1, A2) connect the cell to bitlines (BL and BLB)
• Depending on the stored value, one bitline begins to discharge and a sense amplifier
detects the differential voltage between bitlines.
• The read completes before the discharging bitline drops too low

Q5. How does the write operation work in a 6T SRAM cell?


Answer: The write operation follows these steps:
• Wordline (WL) is activated (high)
• Bitlines are driven to the desired complementary values: BL = data to be written
BLB = complement of data
• Access transistors force the new values into the cell
The cross-coupled inverters switch to the new state if the access transistors are strong enough

Q6. What should be the sizing (W/L ratio) of each transistor for the stability of read and write
data?
Answer. Stability of stored data relies on careful transistor sizing. To keep the stable data
during design process following ratio is maintained:
𝑊𝑊 𝑊𝑊 𝑊𝑊
� � >� � >� �
𝐿𝐿 𝑁𝑁1 𝐿𝐿 𝐴𝐴1 𝐿𝐿 𝑃𝑃1
Similarly
𝑊𝑊 𝑊𝑊 𝑊𝑊
� � >� � >� �
𝐿𝐿 𝑁𝑁2 𝐿𝐿 𝐴𝐴2 𝐿𝐿 𝑃𝑃2

Q7. Explain the term “CR and PR” used in SRAM cell. Also discuss Read and Write operation
of 6T SRAM cell with proper example and sizing parameters.
Answer: Since channel length is kept constant according to the choice of technology node, the
term “Cell Ratio” is often used. It is defined as the ratio of width of two transistors. During
design process, one can Typically maintain a cell ratio (CR = width of pull-down NMOS/width
of access transistor) of 2 to 2.5 and a pull-up ratio (PR = width of pull-up PMOS/width of
access transistor) of 1 to 1.5.

The read operation begins with both bitlines (BL and BLB) precharged to VDD. When the
wordline is activated, the access transistors connect the storage nodes to the bitlines. If the cell
stores a "1" (Q=VDD, Qn=0), the bitline connected to QB begins discharging through the access
2
Digital CMOS Design [IEC-405]
Prof. R.K. Chauhan (MMMUT)

transistor and the pull-down NMOS of the inverter, while the other bitline remains at VDD. A
sense amplifier detects this differential voltage to determine the stored value. For read stability,
the cell ratio must be sufficiently high (>1.5) to prevent the "0" node from being pulled up
above the switching threshold during reading, which could flip the stored bit. In a 65nm
technology example, access transistors might be sized at W/L=120nm/60nm while pull-down
NMOS transistors could be W/L=270nm/60nm, yielding a cell ratio of 2.25.

For the write operation, the bitlines are driven to complementary values representing the data
to be written. When the wordline is activated, the access transistors connect these values to the
storage nodes. For example, to write a "0" to a cell currently storing a "1," BL is driven low
while BLB is driven high. The access transistor connected to BL must be strong enough to
overcome the PMOS pull-up transistor and force node Q to discharge. Write-ability requires a
pull-up ratio below 1.8, allowing the access transistors to overpower the pull-up transistors. In
our 65nm example, pull-up PMOS transistors might be sized at W/L=100nm/60nm, giving a
pull-up ratio of 0.83. This carefully balanced sizing ensures reliable operation across process
variations, temperature fluctuations, and voltage changes while minimizing area
(approximately 0.5μm² per cell) and power consumption. The fundamental trade-off in 6T
SRAM design is between read stability (favoring stronger pull-down transistors) and write-
ability (favoring weaker pull-up transistors), requiring careful optimization based on
application requirements.

Q8. What is the trade-off between read stability and write-ability?


Answer: The fundamental trade-off is:
For better read stability: Need stronger pull-down transistors (higher CR)
For better write-ability: Need weaker pull-up transistors (lower PR)
However, weaker pull-ups compromise hold stability and noise margins
Stronger pull-downs increase cell area
This creates a delicate balance that must be optimized based on application requirements,
process variations, and operating conditions.

Q9: List some of the techniques used to enhance SRAM memory performance?
Answer: The primary techniques used to enhance SRAM memory performance include:
• Better sense amplifiers help in improving sensitivity
• Implementing column multiplexing
• Utilizing self-timing circuits
• Employing differential signaling
• Implementing power management techniques like power gating
• Using assist techniques like negative bitline, wordline boosting, and body biasing
• Increasing the number of ports for simultaneous access
• Implementing hierarchical bitlines and wordlines

Q10: How does reducing the bitline capacitance improve SRAM performance?
Answer: Reducing bitline capacitance improves SRAM performance by:
• Decreasing the RC time constant of the bitline, allowing for faster charging and
discharging
• Enabling faster voltage development during read operations

3
Digital CMOS Design [IEC-405]
Prof. R.K. Chauhan (MMMUT)

• Reducing the time required for the sense amplifier to detect the differential voltage
• Lowering the power consumption during precharge and discharge cycles
• Improving overall read access time, which is often the limiting factor in SRAM
performance

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