Digital Signal Processor: Architecture
Digital Signal Processor: Architecture
ABSTRACT:A digital signal processor (DSP) is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processingDigital signal processing algorithms typically require a large number of mathematical operations to be performed quickly and repeatedly on a set of data. Signals (perhaps from audio or video sensors) are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints on latency; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable. Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power supply and space constraints. A specialized digital signal processor, however, will tend to provide a lower-cost solution, with better performance, lower latency, and no requirements for specialized cooling or large batteries. The architecture of a digital signal processor is optimized specifically for digital signal processing. Most also support some of the features as an applications processor or microcontroller, since signal processing is rarely the only task of a system. Some useful features for optimizing DSP algorithms are outlined below.
Architecture
By the standards of general-purpose processors, DSP instruction sets are often highly irregular. One implication for software architecture is that hand-optimized assembly-code routines are commonly packaged into libraries for re-use, instead of relying on advanced compiler technologies to handle essential algorithms. Hardware features visible through DSP instruction sets commonly include: Hardware modulo addressing, allowing circular buffers to be implemented without having to constantly test for wrapping. A memory architecture designed for streaming data, using DMA extensively and expecting code to be written to know about cache hierarchies and the associated delays. Driving multiple arithmetic units may require memory architectures to support several accesses per instruction cycle Separate program and data memories (Harvard architecture), and sometimes concurrent access on multiple data busses Special SIMD (single instruction, multiple data) operations Some processors use VLIW techniques so each instruction drives multiple arithmetic units in parallel Special arithmetic operations, such as fast multiplyaccumulates (MACs). Many fundamental DSP algorithms, such as FIR filters or theFast Fourier transform (FFT) depend heavily on multiply accumulate performance.
Program flow
Floating-point unit integrated directly into the datapath Pipelined architecture Highly parallel multiplieraccumulators (MAC units) Hardware-controlled looping, to reduce or eliminate the overhead required for looping operations DSP APPLICADTIONS:
Medical
Military
Mechanical
Motor control, process control, oil and mineral prospectin ADVANTAGES: Accuracy can be controlled by choosing word length Repeatable Sensitivity to electrical noise is minimal Dynamic range can be controlled using floating point numbers Flexibility can be achieved with software implementations Non-linear and time-varying operations are easier to implement Digital storage is cheap Digital information can be encrypted for security Price/performance and reduced time-to-market