Unit5_imp
Unit5_imp
Astable Multivibrator
The two states of circuit are only stable for a limited time and the circuit switches between
them with the output alternating between positive and negative saturation values.
Analysis of this circuit starts with the assumption that at time t=0 the output has just switched
to state 1, and the transition would have occurred.
An op-amp Astable multivibrator is also called as free running oscillator. The basic principle of
generation of square wave is to force an op-amp to operate in the saturation region (±Vsat).
A fraction β =R2/(R1+R2) of the output is feedback to the positive input terminal of op-amp.
The charge in the capacitor increases & decreases upto a threshold value called ±βVsat. The
charge in the capacitor triggers the op-amp to stay either at +Vsat or –Vsat.
Asymmetrical square wave can also be generated with the help of Zener diodes. Astable multi
vibrator do not require a external trigger pulse for its operation & output toggles from one state
to another and does not contain a stable state.
Astable multi vibrator is mainly used in timing applications & waveforms generators.
Design
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor as T=2RCln
(R1+2R2)/R1
2. To simplify the above expression, the value of R1 & R2 should be taken as R2 = 1.16R
Such that fo simplifies to fo =1/2RC.
Design:
From the above figure, three 5k internal resistors act as voltage divider providing bias voltage
of 2/3 Vcc to the upper comparator & 1/3 Vcc to the lower comparator. It is possible to vary
time electronically by applying a modulation voltage to the control voltage input terminal (5).
The output of the control FF is high. This means that the output is low because of power
amplifier which is basically an inverter. Q = 1; Output = 0
The trigger passes through (Vcc/3) the output of the lower comparator goes high & sets the
FF.Q = 1; Q = 0
(iii) At the Positive going trigger pulse: It passes through 2/3Vcc, the output of the upper
comparator goes high and resets the FF. Q = 0; Q = 1 The reset input (pin 4) provides a
mechanism to reset the FF in a manner which overrides the effect of any instruction coming to
FF from lower comparator.
Monostable Operation:
Model Graph:
Initially when the output is low, i.e. the circuit is in a stable state, transistor Q 1 is ON &
capacitor C is shorted to ground. The output remains low. During negative going trigger pulse,
transistor Q1 is OFF, which releases the short circuit across the external capacitor C & drives the
output high. Now the capacitor C starts charging toward Vcc through RA. When the voltage
across the capacitor equals 2/3 V cc, upper comparator switches from low to high. i.e. Q = 0, the
transistor Q1 = OFF ; the output is high.
Since C is unclamped, voltage across it rises exponentially through R towards V cc with a time
constant RC (fig b) as shown in below. After the time period, the upper comparator resets the
FF, i.e. Q = 1, Q1 = ON; the output is low.[i.e discharging the capacitor C to ground potential
(fig c)]. The voltage across the capacitor as in fig (b) is given by
If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately discharged. The
output now will be as in figure (d & e). If the reset is released output will still remain low until a
negative going trigger pulse is again applied at pin 2.
Initially, when the output is high :Capacitor C starts charging toward Vcc through RA&
RB.However, as soon as voltage across the capacitor equals 2/3 Vcc. Upper comparator triggers
the FF & output switches low.
Capacitor C starts discharging through RB and transistor Q1, when the voltage across C equals
1/3 Vcc, lower comparator output triggers the FF & the output goes High. Then cycle repeats.
The capacitor is periodically charged & discharged between 2/3 V cc & 1/3 Vcc respectively. The
time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc equal to the time the output is
high & is given by
Equation 4 indicates that the frequency f0 is independent of the supply voltage V cc. Often the
term duty cycle is used in conjunction with the astable multivibrator. The duty cycle is the ratio
of the time tc during which the output is high to the total time period T. It is generally expressed
as a percentage.
It consists of two current sources, two comparators, two buffers, one FF and a sine wave
converter.
Pin description:
Sine wave output is available at this pin. The amplitude of this sine wave is 0.22 Vcc. Where ±
5V ≤ Vcc ≤ ± 15 V.
Triangular wave is available at this pin. The amplitude of the triangular wave is 0.33Vcc.
Where ± 5V ≤ Vcc ≤ ± 15 V.
The symmetry of all the output wave forms & 50% duty cycle for the square wave output is
adjusted by the external resistors connected from Vcc to pin 4. These external resistors &
capacitors at pin 10 will decide the frequency of the output wave forms.
Pin 6 + Vcc:
Positive supply voltage the value of which is between 10 & 30V is applied to this pin.
Pin 7 : FM Bias:
This pin along with pin no8 is used to TEST the IC 8038.
A square wave output is available at this pin. It is an open collector output so that this pin
can be connected through the load to different power supply voltages. This arrangement is very
useful in making the square wave output.
The external capacitor C connected to this pin will decide the output frequency along with the
resistors connected to pin 4 & 5.
If a single polarity supply is to be used then this pin is connected to supply ground & if (±)
supply voltages are to be used then (-) supply is connected to this pin.
5. Easy to use.
Parameters:
The output frequency dependent on the values of resistors R1 & R2 along with the external
capacitor C connected at pin 10.
If RA= RB = R & if RC is adjusted for 50% duty cycle then f0= 0.3/RC; RA = R1, RB =
Duty cycle as well as the frequency of the output wave form can be adjusted by external
resistors at pin 4 & 5.
The values of resistors RA & RB connected between Vcc pin 4 & 5 respectively along
with the capacitor connected at pin 10 decide the frequency of the wave form. The values of RA
& RB should be in the range of 1kΩ to 1MΩ.
(iii)FM Bias:
• The FM Bias input (pin7) corresponds to the junction of resistors R1 & R2.
• The voltage Vin is the voltage between Vcc & pin8 and it decides the output frequency.
With pin 7 & 8 connected to each other the output frequency is given by f0= 0.3/RC where
R = RA = RB for 50% duty cycle.
• But if the output frequency is supposed to vary, then a variable dc voltage should be applied
to this pin.
• The voltage between Vcc & pin 8 is called Vin and it decides the output frequency as,
f0=1.5 Vin/CRAVCC
A potentiometer can be connected to this pin to obtain the required variable voltage required to
change the output frequency.
The temperature compensated Zener diode, constant current source & voltage reference
amplifier together from the reference generating block. The Zener diode is used to generate a
fixed reference voltage internally. Constant current source will make the Zener diode to
operate at affixed point & it is applied to the Non – inverting terminal of error amplifier. The
Unregulated input voltage ±Vcc is applied to the voltage reference amplifier as well as error
amplifier.
2. Error Amplifier:
Error amplifier is a high gain differential amplifier with 2 input (inverting & Non-inverting). The
Non-inverting terminal is connected to the internally generated reference voltage. The
Inverting terminal is connected to the full regulated output voltage.
Q1 is the internal series pass transistor which is driven by the error amplifier. This transistor
actually acts as a variable resistor & regulates the output voltage. The collector of transistor
Q1 is connected to the Un-regulated power supply. The maximum collector voltage of Q1 is
limited to 36Volts. The maximum current which can be supplied by Q1 is 150mA.
The internal transistor Q2 is used for current sensing & limiting. Q2 is normally OFF transistor.
It turns ON when the IL exceeds a predetermined limit.
Low voltage, Low current is capable of supplying load voltage which is equal to or between 2
to 7Volts.
The Voltage across R2 is connected to the Non – inverting terminal of the regulator I C Vnon-
inv = R2/(R1+R2) Vref
Therefore the Vo is connected to the Inverting terminal through R 3 & RSC must also be
equal to Vnon-inv
R3 = R1ll R2 =R1R2/(R1+R2)
Rsc (current sensing resistor) is connected between Cs & CL. The voltage drop across Rsc is
proportional to the IL.
This resistor supplies the output voltage in the range of 2 to 7 volts, but the load current
can be higher than 150mA.
The Non – inverting terminal is now connected to Vref through resistance R3.
The value of R1 & R2 is adjusted in order to get a voltage of Vref at the inverting terminal at
the desired output.
Vo = [1+R1/R2] Vin
Rsc is connected between CL & Cs terminals as before & it provides the short Circuit
current limiting Rsc =0.6/Ilimit
For this circuit the output voltage varies between 7 & 37V.
Transistor Q increase the current sourcing capacity thus IL (MAX) is greater than 150mA.
Rsc =0.6/Ilimit