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SRAM & DRAM

The document explains the operations of 6T SRAM and DRAM memory types. SRAM uses 6 transistors for storing and accessing data, with operations including hold, write, and read, while DRAM uses 1 transistor and 1 capacitor per bit, requiring periodic refresh to maintain data. Each memory type has distinct operational steps and characteristics that define their functionality and data retention methods.

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7 views

SRAM & DRAM

The document explains the operations of 6T SRAM and DRAM memory types. SRAM uses 6 transistors for storing and accessing data, with operations including hold, write, and read, while DRAM uses 1 transistor and 1 capacitor per bit, requiring periodic refresh to maintain data. Each memory type has distinct operational steps and characteristics that define their functionality and data retention methods.

Uploaded by

coffeeglass14
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SUMMARIZING SRAM OPERATION

The 6T SRAM (Static Random-Access Memory) cell is a fundamental building block in


memory design, using 6 transistors: 4 for storing data (as a latch) and 2 for accessing the cell
(access transistors). Let’s break down its read, write, and hold operations clearly:

📌 6T SRAM Cell Overview


 Cross-coupled inverters (4 transistors - M1 to M4): Store 1-bit data using
feedback.
 Access transistors (2 transistors - M5 and M6): Connect internal nodes to bit lines
(BL, BLB) when the word line (WL) is high.

🔸 1. Hold Operation (Idle / Retention Mode)


What happens:
 Word line (WL) = Low
 Access transistors M5 and M6 = OFF
 Bit lines (BL, BLB) = Don’t care (disconnected from the cell)
Effect:
 The cross-coupled inverters keep the internal nodes (Q and Q̅ ) stable.
 Data is retained as long as power is supplied.
✅ No power is needed to refresh the data like in DRAM.

🔸 2. Write Operation
Goal: Overwrite the stored value with new data.
Steps:
1. Set bit lines:
o BL = Data to write (e.g., 1)
o BLB = Complement of data (e.g., 0)
2. WL = High → Access transistors M5 and M6 turn ON
3. The stronger bit line drivers overpower the weak latch and force Q and Q̅ to the new
state.
Note:
 Write margin is a key design metric: ability to successfully flip the latch.

🔸 3. Read Operation
Goal: Read the stored value without disturbing it.
Steps:
1. Precharge BL and BLB to VDD (both high)
2. WL = High → M5 and M6 ON
3. Depending on stored value:
o If Q = 1, it pulls BL slightly lower
o If Q = 0, it pulls BLB slightly lower
4. A sense amplifier detects the small voltage difference between BL and BLB and
amplifies it to logic level.
Key Point:
 Read operation must not disturb the stored data.
 Design ensures that the internal nodes are not flipped during read.

🔎 Summary Table
Access Cross-coupled
Operation WL BL / BLB Action
Transistors Inverters

Hold previous
Hold Low Don't care OFF No change
value

BL = data, BLB = New value


Write High ON Overwritten
complement stored

Read without Sense amplifier


Read High Precharged ON
disturb used
SUMMARIZING DRAM OPERATION

Dynamic RAM (DRAM) Operation Explained

Dynamic RAM (DRAM) is a type of memory that stores each bit of data using a capacitor and an
access transistor — typically 1 transistor and 1 capacitor per bit (1T1C structure).

Unlike SRAM, DRAM is "dynamic" because it must be periodically refreshed to retain data — the
capacitor charge leaks away over time.

🔧 DRAM Cell Structure

 1 Transistor (Access Transistor) — controls access to the storage capacitor.

 1 Capacitor — stores the actual data bit:

o Charged = ‘1’

o Discharged = ‘0’

Each cell is connected to:

 Word Line (WL) — controls the gate of the access transistor.

 Bit Line (BL) — carries data to/from the cell.

🔸 1. Write Operation

Goal: Store a bit ('0' or '1') into the capacitor.

Steps:

1. Bit Line (BL) is driven with the data:

o BL = VDD (logic 1) or 0V (logic 0)

2. WL = High → Access transistor turns ON

3. Charge is transferred to the capacitor:

o If BL = VDD → Capacitor is charged → Logic 1 stored

o If BL = 0V → Capacitor is discharged → Logic 0 stored

4. WL = Low → Access transistor OFF → Charge is isolated

🔸 2. Read Operation

Goal: Read the stored bit from the capacitor.

Steps:

1. Bit Line is precharged to a midpoint voltage (usually VDD/2)


2. WL = High → Access transistor turns ON

3. Small charge from the capacitor affects the bit line voltage:

o If cap is charged → BL voltage slightly rises

o If cap is discharged → BL voltage slightly drops

4. A sense amplifier detects and amplifies this small voltage change to logic ‘1’ or ‘0’.

5. Destructive Read: The read process disturbs the capacitor charge → data must be rewritten
immediately

🔸 3. Refresh Operation

Why?

 The stored charge leaks away over time (due to capacitor leakage).

 Must refresh every cell periodically (e.g., every 64 ms).

How?

 The memory controller reads and rewrites each cell to restore the correct charge.

🧾 Summary Table

Operation Word Line Bit Line Capacitor Notes

Write High VDD / 0 Charged/Discharged Bit stored

Read High Precharged Slight change in BL → sensed Destructive read

Refresh Periodic Automatic Charge is restored Prevent data loss

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