EEE211

PSpice Assignment – Part 2

Design of an Operational Amplifier

QUESTION FORM

NAME: STUDENT ID:

aotttdceee
2143765
Eeoa
Yiyan.Hu
…………………………………… ……………………………………

Questions

1. Briefly explain how an ‘active load’ doubles the gain of the differential input
stage (10%)
Solution:
The circuit diagram depicting the initial configuration of the differential input
stage is presented below:

Figure 1. The original differential input stage circuit

The associated small-signal equivalent circuit can be graphically represented:

rπ1 gmVπ1 rπ2

gmVπ2

Vout
Vin+ Vin-
ro1 RL
ro2

Figure 2. The equivalent circuit

1
Upon scrutinizing the voltage gain aforementioned, it can be deduced that:
 Vin βVin ( RL // ro 2 ) g mVi ( RL // ro 2 ) (1)
Vout  βib 2 ( RL // ro 2 )  β ( RL // ro 2 )  
rπ 2rπ 2

Vout g m ( RL // ro 2 )
Av   (2)
Vin 2

Subsequently, substitute the load resistor RL with a current mirror, linking the
reference transistor Q8 to the collector circuit of Q9. The voltage gain is
unaffected by the second current mirror composed of Q4 and Q5. The
schematic representation of the circuit is illustrated below:

Figure 3. The circuit with active load

The current exiting from the output terminal can be formulated as:

io  iC 7  iC 9 (3)

Upon the application of differential voltages Vin+ and Vin-, the current iC9
equates to iC8 as a consequence of the operational behavior of the current
mirror. Additionally, iC8 is equivalent to iC6, given that the collector terminals
of Q6 and Q8 are interconnected at the identical node. Consequently:

(4)
The resulting current, io', exhibits a twofold increase compared to the
antecedent state, while iC7 remains constant in Figure 2. To generate the
output voltage gain, a load resistor RL is connected at the output terminal,
mirroring the configuration in Figure 2. Consequently, the voltage gain can be
computed as follows:
2
 (5)
Concerning equations (2) and (6), it can be deduced that the utilization of an
active load results in a twofold amplification of voltage gain through the
doubling of the output current.

2. Give the circuit diagram of your differential amplifier input circuit and show
your calculation of the differential input resistance and voltage gain of the
input stage. (10%)
Solution:
The schematic representation of the small signal equivalent circuit for the
differential amplifier in the differential mode is illustrated in Figure 4 as
depicted.

Figure 4 The small signal equivalent circuit for the differential amplifier
The differential amplifier input circuit diagram is shown:

Figure 5 The differential amplifier input circuit

3
This circuit is founded upon the long-tail pair configuration illustrated in
Figure 1, where the tail resistor RE has been substituted with a stable current
source, represented by the current mirror Q1 and Q2. Additionally, the resistor
RL has been replaced by connecting the reference transistor Q8 to the collector
circuit of Q9. Consequently, the input resistance can be ascertained through the
utilization of the small signal equivalent circuit depicted in Figure 2, as
derived from the original circuit in Figure 1.

(6)

Examining Figure 5, it is evident that ICQ4 equals ICQ5, and ICQ4 equals ICQ3,
attributable to the current mirror effect. This implies that IEQ4 is approximately
equal to IEQ3, approximating ICQ4. Consequently, ICQ1 can be expressed as the
sum of IEQ4 and IEQ3, yielding 2ICQ4. Leveraging the current mirror effect, it
follows that ICQ1 equals ICQ2. The computation of ICQ2 involves the utilization
of VEB(on), which is 0.6V according to the specified parameters of the PNP
transistor 2N2907, as detailed in the parameter table presented in Figure 6.

(7)

Figure 6 2N2907 parameters.

Therefore, ICQ4 equals: ICQ2/2 = 1.16×10-4A accordingly.
Then we can calculate the input resistance:
× ×
𝑅 = 2𝑟 = = = = 1.08 × 10 𝛺 (8)
× × . ×

The output voltage can be expressed as:

Vout  iout (ro3 // ro5 )  (i7  i9 )(ro3 // ro5 )  g mVin (ro3 // ro5 ) (9)
The voltage gain can be expressed:
Vout
Av   g m (ro 3 //ro 5 )
Vin (10)
Referring to the previous lab1, the early voltage for pnp 2N2907 is 119.3V
and for npn 2N2222 is 99.3V. Thus the output resistances can be calculated:
4
 VAp 119.3
ro3    1.028 106Ω (11)
I CQ 3 1.16 10-4

VAn 99.3
ro5    0.856 106Ω
I CQ 5 1.16 10-4
(12)

Substitute the value of gm, ro3, and ro5 into (10)the voltage gain can be calculated:
Av(calculated) = 2.167k

3. Give your measurements used to obtain the input resistance and voltage gain
of the input stage by simulation of the circuit. (15%)
Solution:
Initially, the circuit is configured according to the depiction presented in
Figure 7 within the LTspice simulation environment.

Figure 7
( ) ( )
Then we measure the value of input resistance is 𝑅 through −
( ) ( )

and get:

5
 Figure 8
Then, the measured value of input resistance is 𝟏𝟏𝟖. 𝟒𝒌𝜴.

Subsequent to these procedures, we quantified the voltage gain denoted as AV,

( )
calculated as through = = and get:
( )

Figure 9
Then, the measured value of voltage gain is 2.17k.

4. Show the voltage transfer characteristic obtained by simulation. (15%)

Initially, the circuit is configured by the illustration presented in Figure 10,
followed by the establishment of the circuit for a DC sweep with incremental
steps of 0.01u, spanning the range from -0.05mV to 0.05mV.

6
 Figure 10

Subsequently, the circuit is executed to assess the output voltage under the
condition of a 0V input, employing LTspice simulation. The outcome is
depicted in Figure 11.

Figure 11
So, we can get the input offset voltage is 𝟑𝟑. 𝟏𝟖𝝁𝑽.

Following this, the calculation of the slope is conducted by designating two

specific points, as delineated in Figure 12.

7
 Figure 12
So, the voltage gain can be determined through calculating the slope of the
∆𝑽𝒐𝒖𝒕
curve in figure 12: = 2.79× 𝟏𝟎𝟔 .
∆𝑽𝒊𝒏

Subsequently, the circuit is reconfigured to facilitate a DC sweep with

incremental steps of 0.01, spanning the range from -9mV to 9mV, thereby
yielding the voltage transfer characteristic illustrated in Figure 13.

8
 Figure 13

5. Give your calculation of the differential voltage gain and the output resistance
of the whole amplifier. You should refer to the amplifier properties sheet
included in the laboratory script and make reasonable approximations. (25%)

To do the calculation of the whole circuit, the circuit is divided into 5 parts:

Figure 14 The original AC circuit

9
 Figure 15 The circuit is divided into 5 stages

DC analysis:

Stage 1:
I2 can be calculated by applying KVL:

Stage 2:
Therefore, I1 can be calculated:

Stage 3:
I4 can be calculated by:

10
Stage 4:
According to the current mirror: I5 = I2 = 8.7×10-4A
The calculation of I6 is contingent upon the prior determination of I7, as indicated in
stage 5. Additionally, referencing the findings from the preceding laboratory
experiment (Lab1), the βn value for the NPN transistor 2N2222 is approximated to be
around 213. This value serves as a critical parameter in the subsequent calculations
and analyses.

Stage 5:
Since Vout is 0V. Apply KVL, I7 can be calculated:

AC analysis:
Subsequently, for the assessment of the small signal voltage gain and output
resistance, an AC analysis is executed.

Stage 1:
Stage 1, functions as the bias current section and can be conceptualized as a current
source. Consequently, it makes no substantive contribution to the overarching voltage
gain.

Stage 2:
Subsequently, Stage 2 executes a differential amplifier featuring an active load.
Reference to equation (4) facilitates the calculation of the voltage gain.

11
Ri3 is the input resistance seen from the base of transistor Q7, which:

Ri4 is the input resistance seen from the base of transistor Q8, which:

Substitute the value of rπ7 and Ri4 into , it can be obtained: Ri3
= 1675.68kΩ.
Then, Av2 can be obtained: Av2 = 1692.5

Stage 3:
Stage 3 is characterized by an emitter follower (CC) configuration. By referencing the
amplifier properties sheet provided in the laboratory script, the calculation for the
voltage gain can be ascertained.

12
Therefore, Av3 can be obtained: Av3 = 0.723

Stage 4:
Stage 4 is a common-emitter amplifier, wherein the presence of a current mirror
introduces an impact on the voltage gain. The determination of the voltage gain can
be derived by consulting the amplifier properties sheet outlined in the laboratory
script.

Substitute the values into , the voltage gain can be calculated:

Av4 = -2020.9

Stage 5:
Stage 5 serves as a common-collector amplifier, constituting the output stage. The
assessment of the voltage gain in this stage can be established by consulting the
amplifier properties sheet as outlined in the laboratory script, where the relevant

expression is represented by equation . In the context of Stage 5:

So, the voltage gain can be obtained: Av5 = 0.997.

13
Finally, the whole voltage gain can be obtained:

Then we calculate the output resistance of the whole amplifier:

6. Complete the table below.

Specification Voltage Input Output Current Input

gain resistance resistance from offset
(MΩ) (kΩ) supply voltage
(mA) VOS
(mV)
Specified > 5 x105 > 0.1MΩ < 1kΩ < 5mA ---------
value
Measured 28.856x105 0.13466MΩ 0.3174KΩ 2.9246mA 0.03318mV
value

Calculated 24.656x105 0.10851MΩ 0.3301KΩ 2.8823mA ---------

value
Compare your measured and calculated values given in the table and account for any
significant discrepancies. (10%)

14
 Voltage gain
1. Measured value
The voltage gain can be obtained by:

Figure 16
According to the figure, the voltage gain is: Av(measured) = 2.88256M

2. Calculated value
Reiterating the findings from the previous section, the calculated value for the open-
loop gain was determined to be 2.4656x106. Subsequently, during the measurement
phase, the obtained value closely aligned with the calculated one. This close
agreement between the calculated and measured values suggests that the results for
this particular part of the analysis are reliable and can be considered reasonable.

Input resistance
1. Measured value
Initially, the circuit is assembled by the configuration depicted in Figure 17.
Subsequently, the DC voltage is calibrated, setting Vin+ to 33.18μV— a value
previously measured in Figure 11, Question 4, and Vin- to 0V. Following this, the AC
voltage of Vin+ is adjusted to 1μV with a phase of 0°, while Vin- is set to 1μV with a

15
phase of 180°. After these adjustments, an AC sweep simulation is executed, yielding
an input resistance value of Rin=134.66kΩ, as illustrated in Figure 18.

Figure 17

Figure 18

2. Calculated input resistance

The input resistance can be calculated by (6):

2 p
Rin ( calculated )  rπ 3  rπ 4   108.510kΩ
gm4

16
 Output resistance
1. Measured value
To obtain the output resistance, the complete circuit is modified:

Figure 19

Figure 20 The output resistance

The measured output resistance is: Rout(measured) = 317.37Ω

2. Calculated value
In the preceding section, the output impedance value was computed and found to
be 0.3301KΩ. Consequently, the measured value closely aligns with the calculated
one, indicating a high degree of agreement. It is reasonable to conclude that the
results for this particular aspect are deemed satisfactory.

17
 Current from supply
1. Measured value
Subsequently, the circuit remains unaltered as we proceed with the DC simulation. In
this context, the current originating from the source can be approximated as the
current flowing through the voltage supply V1. The obtained results are presented in
Figure 21.

Figure 21
The current from supply: Is(measured) = Ie1+Ie2+Ic7+Ie9+Ic10 = 2.9246mA

2. Calculated value
The calculation for the current from the supply involves summing up the emitter
currents (IE) flowing through transistors Q1, Q2, Q7, Q9, and Q10. Assuming that IE is
approximately equal to the collector current (Ic), the calculated value for the current
sourced from the supply can be obtained as follows: Is(calculated) = I1+I2+I4+I5+I7 =
2.8823mA

Input offset voltage

In question 4 it was already shown that input offset voltage is equal to

𝟑𝟑. 𝟏𝟖𝝁𝑽.
18
Compare measured values with calculated values, we can find:
The identified reasons provide a comprehensive explanation for the significant
discrepancies observed in both voltage gain and input resistance. Let's break down
each reason:
1. Output Resistance Calculation (Early Effect and VCE): The calculation of
output resistance (ro) is related to the Early effect, but it is noted that the DC voltage
across the collector and emitter terminals (VCE) is ignored in the lab's calculations.
This oversight affects the accuracy of the output resistance values, contributing to the
observed discrepancies.
2. Assumptions in Current Determination: The assumption that collector currents
are equal to emitter currents (Ic ≈ Ie), and the neglect of base currents during DC
calculations introduce small differences. While these assumptions are often made for
simplification, they contribute to the overall discrepancies in the results.
3. Reference Values for β and Early Voltages (VA): The reliance on current
amplification factors (β) and Early voltages (VA) for the pnp 2N2907 and npn 2N2222
transistors from a previous lab introduces potential errors. Inaccuracies in these
reference values contribute to discrepancies in the calculations.
4. Assumptions and Approximations in Open-Loop Voltage Gain and Input
Resistance: The significant discrepancies between open-loop voltage gain and input
resistance are attributed to various assumptions and approximations made during the
calculations. Assumptions such as IC=IE, considering a reference current equal to the
output current of the current mirror circuit, and ignoring the CC circuit's effect on
voltage gain contribute to differences between calculated and measured values.

To address these discrepancies, it is crucial to refine the calculations by considering

the impact of VCE on output resistances, accounting for base currents in current
determinations, verifying and improving reference values for β and VA, and
reassessing assumptions and approximations made in open-loop voltage gain and
input resistance calculations. This iterative process of refinement can enhance the
accuracy of the analysis and bring the calculated values closer to the measured values.
19
 7. Give your measured Bode plots
(a) log10 gain magnitude vs log10 frequency, and
(b) linear phase vs log10 frequency
for the op-amp. What can you deduce about the stability of your amplifier
from the Bode plots when it is used in a negative feedback circuit? (15%)
Initially, the circuit is assembled according to the schematic representation in Figure
17. Subsequently, a simulation is conducted, yielding the Bode plot illustrating the
relationship between gain and frequency, as depicted in Figure 22. Additionally, the
Bode plot illustrating the phase-frequency characteristics is obtained and presented in
Figure 23.

Figure 22

Figure 23

20
Subsequently, specific data points are meticulously measured to acquire detailed and
precise results:

Figure 24

Figure 25

Figure 26

21
In Figure 24, the data reveals a peak gain of 129.19 dB, occurring precisely at a
frequency of 14.79 kHz. Moving on to Figure 25, it becomes apparent that the 3-dB
frequency, often referred to as the cutoff frequency, is measured at 7.476 kHz.
Importantly, this frequency point is situated below the frequency corresponding to the
maximum gain. and the 3dB frequency also called cut-off frequency. Drawing
insights from Figure 26, it is discerned that the frequency at which the gain reaches 0
decibels is identified as 36.132 MHz, and concurrently, the phase is measured at 3.21
degrees. In the pursuit of evaluating the stability of this amplifier when incorporated
into a negative feedback circuit, a crucial preliminary step involves the computation
of the closed-loop gain. This pivotal parameter is calculated through the

expression:𝐴 = = where T is loop gain. Then we sense the return

voltage 𝑉 , break the feedback loop ,and add test voltage signal V . After that, we

have loop gain 𝑇 = − and the phase of loop gain is ∠T = ∠𝑉 − ∠V − 180°.

If we assume ∠V = 0°, then the formula of ∠T can be simplified to ∠T = ∠𝑉 −

180°.
If we assume ∠V = 0°, then the formula of ∠T can be simplified to ∠T = ∠𝑉 −
180°. By the depictions presented in Figures 24 and 25, the Bode plot illustrates the
relationship between phase and frequency. Specifically, when the phase angle
∠T =0, it implies that the phase angle of ∠𝑉 = 180. Consequently, ∠T is
positioned at lower frequencies. Subsequently, as the frequency is incremented until
the attainment of the 0 dB point, characterized by ∠Vr = 3.21°, the corresponding
∠T can be computed as 3.21° - 180° = -176.79°, situating it within the domain of
high frequencies. However, at the juncture of reaching the 0 dB point, where 𝛽 ≠ 1,
the phase exceeds -180 degrees. To rectify this incongruity, an adjustment to ∠Vr is
implemented, ensuring that |β| = 1. As ∠Vr ascends, ∠T concurrently increases by
the prescribed formula.
The culmination of these analytical deliberations affirms the stability of the amplifier
when employed within a negative feedback circuit.

22