LIMITATIONS OF REPEATED ADDITION The Booth Multiplication Algorithm

METHOD FOR MULTIPLICATION: 1. Multiplicand is placed in BR and Multiplier in

a. Least sophisticated method QR 2. Accumulator register AC, Qn+1 are
b. Just use adder over and over again initialized to 0 3. Sequence counter SC is
c. If the multiplier is n bits,can have as many as initialized to n (number of bits).
d. 2n iterations of addition -- O(2n) 4. Compare Qn and Qn+1 & perform following
e. Not used in an ALU 01 –> AC=AC+BR
Array Multiplier :Binary multiplication can be 10 –> AC=AC+BR’+1
implemented in a combinational two- 00 –> No arithmetic operation
dimensional logic array called array multipl 11-> No arithmetic operation
5. ASHR- Arithmetic Shift right AC,QR
6. Decrement SC by 1
The final product will be store in AC, QR
Features of Booth Algorithm:
> Booth algorithm works equally well for both
negative and positive multipliers.
> Booth algorithm deals with signed
multiplication of given number.
> Speed up the multiplication process.
restoring division algorithm with an example.
: Register A is initially loaded with 0 and it
•The main component in each in each cell is a consists of n+1 bits, where n is the number of
full adder, FA. •The AND gate in each cell bits in the dividend. Dividend is loaded in
determines whether a multiplicand bit mj, is register Q and Register M is loaded with the
added to the incoming partial product bit based divisor. After division is complete n bit
on the value of the multiplier bit, qi. •Each row quotient is in register Q and remainder is in
i, where 0<= i <=3, adds the multiplicand register A. extra bit on A and M accommodates
(appropriately shifted) to the incoming parcel the sign bit during subtractions.
product, PPi, to generate the outgoing partial Eg; M = 00011
product, PP(i+1), if qi.=1. • If qi.=0, PPi is passed M’+1 = 11100+1
vertically downward unchanged. = 11101
Sequential Circuit Multiplier :Multiplication is
performed as a series of (n) conditional addition
and shift operation such that if the given bit of
the multiplier is 0 then only a shift operation is
performed, while if the given bit of the
multiplier is 1 then addition of the partial
products and a shift operation are performed.
Algorithm:
(1) The multiplier and multiplicand are loaded
into two registers Q and M. Third register
A and C are cleared to 0.
(2) In each cycle it performs 2 steps:
(a) If LSB of the multiplier qi =1, control
sequencer generates Add signal which
adds the multiplicand M with the register A and
the result is stored in A.
(b) If qi =0, it generates Noadd signal to restore
the previous value in register A.
(3) Right shift the registers C, A and Q by 1 bit
Dividend=8 [1000], Divisor=3 [11]
Quotient=2 [0010], Remainder=2 [00010]
PIPELINING is a technique of decomposing a Four Segment Pipeline The general structure
sequential process into sub operations, with of four segment pipeline is shown in fig. the
each sub process being executed in a special operands are passed through all four segments
dedicated segment that operates concurrently in affixed sequence. Each segment consists of
with all other segments. A pipeline can be a combinational circuit Si that performs a sub
visualized as a collection of processing segments operation over the data stream flowing
through which binary information flows. Each through the pipe. The segments are separated
segment performs partial processing dictated by by registers Ri that hold the intermediate
the way the task is partitioned. The result results between stages. Information flows b/w
obtained from the computation in each segment adjacent stages under control of a common
is transferred to the next segment in the clock applied to all registers simultaneously
pipeline. The final result is obtained after the
data have passed through all segments.
A pipeline processor process instruction in
4 steps: F Fetch: Read the instruction from the
memory D Decode: Decode the instruction and
fetch source operands. E Execute: perform
operation specified by instruction W Write: PIPELINE CONFLICTS:
Store the result in the destination location. 1. Resource Conflicts: They are caused by
Advantages of pipeline. access to memory by two segments at the
• Multiple tasks operating simultaneously using same time. Most of these conflicts can be
different resources resolved by using separate instruction and
• Pipelining increases throughput data memories.
Pipeline Organization 2. Data Dependency: these conflicts arise
The simplest way of viewing the pipeline when an instruction depends on the result of a
structure is to imagine that each segment previous instruction, but this result is not yet
consists of an input register followed by a available.
combinational circuit. The register holds the 3. Branch Difference: they arise from branch
data and the combinational circuit performs the and other instructions that change value of PC.
sub operation in the particular segment. The PIPELINE HAZARDS DETECTION AND
output of the combinational circuit is applied to RESOLUTION Pipeline hazards are caused by
the input register of the next segment. A clock is resource usage conflicts among various
applied to all registers after enough time has instructions in the pipeline. Such hazards are
elapsed to perform all segment activity. In this triggered by inter instruction dependencies
way the information flows through the pipeline when successive instructions overlap their
one step at a time. fetch, decode and execution through a
Eg: Suppose we want to perform the combined pipeline processor, inter instruction
multiply and add operations with a stream of dependencies may arise to prevent the
numbers. sequential data flow in the pipeline. For
Ai*Bi + Ci for i=1, 2, 3 ….7 example an instruction may depend on the
Each sub operation is to implemented in a results of a previous instruction. Until the
segment within a pipeline. Each segment has completion of the previous instruction, the
one or two registers and a combinational circuit. present instruction cannot be initiated into the
R1 through r5 are registers that receive new pipeline. In other instances, two stages of a
data with every clock pulse. pipeline may need to update the same
The multiplier and adder are combinational memory location. Hazards of this sort, if not
circuits R1<- Ai R2<-Bi Input Ai and Bi properly detected and resolved could result in
R3<-R1*R2 R4<-Ci multiply and input Ci an inter lock situation pipeline or produce
R5<-R3+R4 add Ci to product unreliable results by overwriting.
CLASSIFICATION OF PIPELINE PROCESSORS pipelining speeding up the performance of a
1. Arithmetic Pipelining: The arithmetic logic computer Speedup (S) of the pipelined
units of a computer can be segmented for processor over non-pipelined processor, when
pipeline operations in various data formats. 'n' tasks are executed on the same processor
2. Instruction Pipelining: The execution of is: S-Performance of pipelined processor/
stream of instructions can be pipelined by Performance of non pipelined processor
overlapping the execution of current instruction Consider a 'k' segment pipeline with clock
with the fetch, decode and execution of cycle time as 'Tp'. Let there be 'n' tasks to be
subsequent instructions. This technique is completed in the pipelined processor. Now,
known as instruction lookahead. the first instruction is going to take 'k' cycles to
3. Processor Pipelining: Pipeline processing of come out of the pipeline but the other 'n - I'
the same data stream by a cascade of instructions will take only '1' cycle each,
processors, each of which processes a specific i.e, a total of 'n 1' cycles. So, time taken to
task. The data stream passes the first processor execute 'n' instructions in a pipelined
with the results stored in memory block which is processor.
also accessible by the second processor. The ET pipeline k+n-1 cycles= (k+n-1)Tp not
second processor then passes the refined results In the same case, for a non-pipelined
to the third and so on. processor, execution time of 'n' instructions
INSTRUCTION PIPELINE An instruction pipeline will be: ET non pipdine n*k*Tp
operates on a stream of instructions by As the performance of a processor is inversely
overlapping the fetch, decode, and execute proportional to the execution time, we have,
phases of instruction cycle. An instruction S=ETnonpipeline/ET pipeline=
pipeline reads consecutive instructions from n *k*Tp/ (k+n-1)Tp = (n*k)/(k+n-1)
memory while previous instructions are being ARITHMETIC PIPELINE An arithmetic pipeline
executed in other segments. This causes the divides an arithmetic problem into various sub
instruction fetch and executes phases to overlap problems for execution in various pipeline
and perform simultaneous operations segments. It is used for floating point
operations, multiplication and various other
computations. Eg: Floating point addition using
arithmetic pipeline
The following sub operations are performed:
•Compare the exponents. •Align mantissas.
•Add/subtract mantissas. •Normalize result

Four stages Instruction Pipeline

DATA DEPENDENT HAZARD TYPES CONTROL / BRANCH HAZARD
1. Read after Write (RAW): Instruct J tries to A control/branch hazard is when we need to
read operand before Instruction I writes it find the destination of a branch, and can’t
2. Write after Read (WAR):Instruction J tries to Fetch any new instructions until we know that
write operand before Instruction I reads -Gets destination.
wrong operand Method for dealing with branch hazard
3. Write after Write (WAW): Instruction J , tries •Stall: Stop loading instruction until result is
to write operand before Instruction I writes it available. Stalling for each branch is not
Leaves wrong result (Instr I not Instr J Practical
Read after Read (RAR).: It occurs when the •Predict: Assume an outcome and continue
instruction both read from the same register. No fetching (undo if prediction is wrong)
hazard occurs. -Loses cycles only on misprediction
•Delayed Branch: Specify in architecture that
the instruction immediately following branch is
always executed.
PIPELINE HAZARDS
Pipeline hazards are situations that prevent
the next instruction in the instruction stream
from executing during its designated clock
cycles. Any condition that causes a stall in the
pipeline operations can be called a hazard.
Structural hazard
a. two different instructions use same h/w in
same cycle- They arise from resource conflict
b. HW cannot support all combination of
instructions in overlapped fashion (single
person to fold and put clothes away)
Data hazard
c. They arise when the instruction depends on
the result of previous instruction.
Methods for dealing with data hazard d. must appear as if the instructions execute in
Forwarding: It adds special circuitry to the correct order
pipeline. This method works because it takes Control hazard
less time for the required values to travel e. one instruction affects which instruction is
through a wire than it does for a pipeline next
segment to compute its result. f. They arise when the pipelining of branches &
Code reordeing: We need a special type of other instructions that change the PC
software to reorder code. We call this type of TECHNIQUES USED to OVERCOME HAZARD
software a hardware-dependent compiler. •Structural hazard: Stall, Use of additional
Stall insertion: it inserts one or more installs hardware
(no-op instructions) into the pipeline, which •Data Hazard: Stall, Data Forwarding, Code
delays the execution of the current instruction reordering
until the required operand is written to the •Control hazard: stall , branch predict ,
register file, but this method decreases pipeline delayed branch
efficiency and throughput.