Micro-program Control HARDWIRED CONTROL Horizontal Micro-Instructions

The purpose of control unit is to initiate a The control hardware can be viewed as a The scheme of micro-instruction by
series of sequential steps of micro- state machine that changes from one state assigning one bit position to each control
operations. At any given time certain to another in every clock cycle, depending signal is called horizontal micro-
operations are to be initiated while all on the contents of the instruction register, instructions. Example:
others remain idle. The control variable at the condition codes and the external 011101001101001110 In a horizontal
any given time can be represented by a inputs. The outputs of the state machine microinstruction every bit in the control
string of 1's and 0's called control word. are the control signals. field attaches to a controller.Horizontal
The control words can be programmed to Control logic derived in this section is a microinstructions represent several micro-
initiate the various components in the hardwired control of the one flip-flop per operations that are executed at the same
system in an organized manner. A control state method. The design of hardwired time.
unit whose control variables are stored in control is carried out in 5 consecutive Vertical Micro-Instructions
a memory called a micro-programmed steps We can reduce the length of the
control unit. Each control word of memory 1. The problem is stated horizontal micro-instruction so easily by
is called Microinstruction and Sequence of 2. An initial equipment configuration is implementing another method known as
microinstructions is called Micro-program. assumed vertical micro-instructions. In this case,
Control memory is usually ROM since an 3. An algorithm is formulated Most signals are not needed
alteration of micro-program is seldom 4. The data processor part is specified simultaneously and many others are
needed. The use of micro-program 5. The control logic is designed mutually exclusive Example: In a vertical
involves placing all control variables in Micro-program Sequencer microinstruction, a code is used for each
words of the ROM for use by the control Micro program sequencer is a control unit action to be performed andthe decoder
unit through successive read which does the tasks of Micro-program translates this code into individual control
operations.The content of the word in the sequencing.There are two important signals. The vertical microinstruction
ROM at a given address specifies the factors must be considered while resembles the conventional machine
micro-operations for the system. designing the micro programsequencer. language format comprising one operation
PLA control o The size of the microinstruction and a few operands
The external sequence register establishes o The address generation time
the present state of the control circuit. Micro-program sequencer is attached to
The PLA outputs determine which micro- the control memory.It inspects certain bits
operations should be initiated depending in the microinstruction to determine the
on the external input conditions and the next address for controlmemory.A typical
present state of the sequence register. At sequencer has the following address
the same time other PLA outputs sequencing capabilities.
determine the next state of the sequence 1. Increments the present address of
register control memory
2. Branches to an address which will be
specified in the bits of microinstruction
3. Branches to a given address if a
specified status bit is equal to 1.
4. Transfers control to a new address as
specified by an external source
5. Has a facility for subroutines calls and
returns.

The output from CAR provides the address

for control memory.The contents of CAR
are incremented and applied to the
multiplexer and to the stack registerfile.
The register selected in the stack is
determined by stack pointer. Inputs (I0-I2)
specify theoperation for the sequencer
and input T is the test point for a status
bit.
Array Multiplier CLASSIFICATION OF PIPELINE
Binary multiplication can be implemented PROCESSORS PIPELINE HAZARDS DETECTION AND
in a combinational two-dimensional logic 1. Arithmetic Pipelining: The arithmetic RESOLUTION
array called array multiplier. logic units of a computer can be Pipeline hazards are caused by resource
 The main component in each in each segmented for pipeline operations in usage conflicts among various instructions
cell is a full adder, FA. various data formats. in the pipeline. Such hazards are triggered
 The AND gate in each cell determines 2. Instruction Pipelining: The execution of by inter instruction dependencies when
whether a multiplicand bit mj , is added to stream of instructions can be pipelined by successive instructions overlap their fetch,
the incoming partial product bit based on overlapping the execution of current decode and execution through a pipeline
the value of the multiplier bit, qi . instruction with the fetch, decode and processor, inter instruction dependencies
 Each row i, where 0<= i <=3, adds the execution of subsequent instructions. This may arise to prevent the sequential data
multiplicand (appropriately shifted) to the technique is known as instruction flow in the pipeline
incoming parcel product, PPi , to generate lookahead There are three classes of data dependent
the outgoing partial product, PP(i+1), if qi 3. Processor Pipelining: Pipeline hazards, according to various data update
.=1. processing of the same data stream by a patterns:
 If qi .=0, PPi is passed vertically cascade of processors, each of which 1. Write After Read hazards (WAR)
downward unchanged. PP0 is all 0’s and processes a specific task. The data stream 2. Read After Write hazards (RAW)
PP4 is the desired product. The passes the first processor with the results 3. Write After Write hazards (WAW)
multiplication is shifted left one position stored in memory block which is also We use resource object to refer to
per row by the diagonal signal path. accessible by the second processor. The working registers, memory locations and
Sequential Circuit Multiplier second processor then passes the refined special flags. The contents of these
Multiplication is performed as a series of results to the third and so on. resource objects are called data objects.
(n) conditional addition and shift Each instruction can be considered a
operation such that if the given bit of the PIPELINING mapping from a set of data objects to a set
multiplier is 0 then only a shift operation is Pipelining is a technique of decomposing of data objects. The domain D(I) of an
performed, while if the given bit of the a sequential process into sub operations, instruction I is a set of resource objects
multiplier is 1 then addition of the partial with each sub process being executed in a whose data objects may affect the
products and a shift operation are special dedicated segment that operates execution of instruction I. The range of an
performed. The combinational array concurrently with all other segments. A instruction R(I) is the set of resource
multiplier uses a large number of logic pipeline can be visualized as a collection of objects whose data objects may be
gates for multiplying numbers. processing segments through which binary modified by the execution of instruction I.
Multiplication of two n-bit numbers can information flows. Each segment performs Obviously, the operands to be used in an
also be performed in a sequential circuit partial processing dictated by the way the instruction execution are retrieved (read)
that uses a single n bit adder task is partitioned from its domain and the results will be
Algorithm: A pipeline processor may process each stored (written) in its range.
(1) The multiplier and multiplicand are instruction in 4 steps: F Fetch: Read the Restoring Division
loaded into two registers Q and M. Third instruction from the memory D Decode:
register A and C are cleared to 0. Decode the instruction and fetch the
(2) In each cycle it performs 2 steps: (a) If source operands E Execute: Perform the
LSB of the multiplier qi =1, control operation specified by the instruction W
sequencer generates Add signal which Write: Store the result in the destination
adds the multiplicand M with the register location
A and the result is stored in A. (b) If qi =0, ARITHMETIC PIPELINES
it generates Noadd signal to restore the An arithmetic pipeline divides an
previous value in register A. arithmetic operation into sub operations
(3) Right shift the registers C, A and Q by 1 for execution in the pipeline segments.
Figure shows a logic circuit arrangement
bit Pipeline arithmetic units are usually found
that implements the restoring division
The Booth Algorithm Algorithm in very high speed computers. They are
algorithm just discussed. An n-bit positive
1. Multiplicand is placed in BR and used to implementfloating point
divisor is loaded into register M and an n-
Multiplier in QR operations, multiplication of fixed point
bit positive dividend is loaded into register
2. Accumulator register AC, Qn+1 are numbers, and similar computations
Q at the start of the operation. Register A
initialized to 0 encountered in scientific problems
is set to 0. After the division is complete,
3. Sequence counter SC is initialized to n INSTRUCTION PIPELINE
the n-bit quotient is in register Q and the
(number of bits). An instruction pipeline operates on a
remainder is in register A. The required
4. Compare Qn and Qn+1 and perform the stream of instructions by overlapping the
subtractions are facilitated by using 2’s-
following fetch, decode, and execute phases of
complement arithmetic. The extra bit
01 –> AC=AC+BR instruction cycle. An instruction pipeline
position at the left end of both A and M
10 –> AC=AC+BR’+1 reads consecutive instructions from
accommodates the sign bit during
00 –> No arithmetic operation memory while previous instructions are
subtractions. The following algorithm
11-> No arithmetic operation being executed in other segments. This
performs restoring division. Do the
5. ASHR- Arithmetic Shift right AC,QR causes the instruction fetch and executes
following three steps n times:
6. Decrement SC by 1 The final product phases to overlap and perform
1. Shift A and Q left one bit position.
will be store in AC, QR simultaneous operations.
2. Subtract M from A, ie; (A-M) and place
the answer back in A.
3. If the sign of A is 1, set q0 to 0 and add
M back to A (that is, restore A); otherwise,
set q0 to 1.
Components of Register Status Registers The relative magnitude of
Transfer Logic 1. The set of registers in the two numbers may be determined by
system and their functions:A register also subtracting one number from the other
encompasses all type of registers including andthen checking certain bit conditions in
shift registers, counters and memory the resultant difference. This status bit
units. conditions (often calledcondition-code bits
2. The binary-coded information stored in or flag bits) are stored in a status register.
the registers: The binary information Status register is a 4 bit register. The four
stored in registers may be binary numbers, bits are C (carry), Z (zero),S (sign) and V
binary coded decimal numbers, (overflow).These bits are set or cleared as
alphanumeric characters, control a result of an operation performed in the
information or any other binary coded ALU.  Bit C is set if the output carry of an
information. ALU is 1.  Bit S is set to 1 if the highest
3. The operations performed on the order bit of the result in the output of the
information stored in the registers: The ALU is 1.  Bit Z is set to 1 if the output of
operations performed on data stored in the ALU contains all O's.  Bit V is set if the
registers are called micro operations. exclusive —OR of carries C8 and C9 is 1,
Examples are shift, count, add, clear and and cleared otherwise. This is the
load condition for overflow when the numbers
4. The control functions that initiate the are in signed 2's complement
sequence of operations: The control representation. For an 8 bit ALU, V is set if
functions that initiate the sequence of the result is greater than 127 or less than -
operations consists of timing signals that 128.
sequence the operations one at a time. Accumulator Register
An accumulator is a register for short-
Micro-Operation: Operations performed term, intermediate storage of arithmetic
in data stored in registers. Elementary and logic data in a computer's CPU
operation that can be performed parallel (central processing unit).The most
during one clock pulse period. The result elementary use for an accumulator is
of operation may replace the previous adding a sequence of numbers. The
binary information of a register or may be numerical value in the accumulator
transfered to another register. Example: increases as each number is added, exactly
Shift, count, clear, add & load as it happens in a simple desktop
Types of Micro-Operations in digital calculator (but much faster, of course).
system Once the sum has been determined, it is
 Interregister transfer micro-operation: written to the main memory or to another
Do not change the information content register
when the binary information moves from
one register to another
 Arithmetic operation: Perform
arithmetic on numbers stored in registers.
 Logic microoperation: Perform
operations such as AND and OR on
individual pairs of bits stored in registers.
 Shift microoperation: Specify operations
for shift registers.
Design of Arithmetic Circuit The basic
component of the arithmetic section of an
ALU is a parallel adder. A parallel adder is
constructed with a number of full-adder
circuits connected in cascade. By
controlling the data inputs to the parallel
adder, it is possible to obtain different
types of arithmetic operations. The above
figure demonstrates the arithmetic
operations obtained when one set of
inputs to a parallel adder is controlled
externally. The number of bits in the
parallel adder may be of any value. The
input carry Cin goes to the full-adder
circuit in the least significant bit position.
The output carry Cout comes from the full-
adder circuit in the most significant bit
position.
Design of Arithmetic Logic Unit The logic
circuit can be combined with the
arithmetic circuit to produce one
arithmetic logic unit. Selection variables S1
and S0 can be made common to both
sections provided, we are using a third
selection variable S2, to differentiate
between the two. Design steps
1. Design the arithmetic section
independent of the logic section. 2.
Determine the logic operations obtained
from the arithmetic circuit in step 1,
assuming that the input carries to all
stages are 0. 3. Modify the arithmetic
circuit to obtain the required logic
operations.
Functional units of a computer memory is organized so that a group of n Single Bus organization of Processor The register file is said to have three ports.
Input unit accepts information: •Human bits can be stored or retrieved in a single, Figure shows the organization in which the There are two outputs, allowing the
operators, •Electromechanical devices basic operation. Each group of n bits is arithmetic and logic unit (ALU) and all the contents of two different registers to be
(keyboard) •Other computers referred to as a word of information, and registers are interconnected via a single accessed simultaneously and have their
Arithmetic and logic unit(ALU): •Performs n is called the word length common bus. contents placed on buses A and B. The
the desired operations on the input Byte Addressability third port allows the data on bus C to be
information as determined by instructions We now have three basic information loaded into a third register during the
in the memory quantities to deal with: bit, byte, and same clock cycle.
Output unit sends results of processing: word. A byte is always 8 bits, but the word
•To a monitor display, •To a printerStores length typically ranges from 16 to 64 bits.
information: •Instructions, •DataControl It is impractical to assign distinct addresses
unit coordinates various actions •Input, to individual bit locations in the memory.
•Output •Processing The most practical assignment is to have
BASIC OPERATIONAL CONCEPTS successive addresses refer to successive
To perform a given task, an appropriate byte locations in the memory.
program consisting of a list of instructions Big-Endian and Little-Endian Assignments
is stored in the memory. Individual There are two ways that byte addresses
instructions are brought from the memory can be assigned across words. The name
into the processor, which executes the big-endian is used when lower byte
specified operations addresses are used for the more
significant bytes (the leftmost bytes) of
the word. The name little-endian is used
for the opposite ordering, where the lower
byte addresses are used for the less The data and address lines of the external
significant bytes (the rightmost bytes) of memory bus are connected to the internal
the word processor bus via the memory data
MEMORY OPERATIONS Both program register, MDR, and the memory address
instructions and data operands are stored register, MAR, respectively. Register MDR
in the memory. Two basic operations has two inputs and two outputs. Data may
involvingthe memory are needed, namely, be loaded into MDR either from the
Read and Write.The Read operation memory bus or from the internal
transfers a copy of the contents of a processor bus.
The instruction register (IR) holds the specific memory location tothe processor. The data stored in MDR may be placed on
instruction that is currently being The memory contents remain unchanged. either bus. The input of MAR is connected
executed. The program counter (PC) ADDRESSING MODES to the internal bus, and its output is
contains the memory address of the next The different ways for specifying the connected to the external bus. The control
Buses A and B are used to transfer the
instruction to be fetched and executed. In locations of instruction operands are lines of the memory bus are connected to
source operands to the A and B inputs of
addition to the IR and PC, general-purpose known as addressing modes the instruction decoder and control logic
the ALU, where an arithmetic or logic
registers R0 through Rn−1, often called Register mode: The operand is the block. Three registers Y, Z, and TEMP
operation may be performed. The result is
processor registers. They serve a variety of contents of a processor register; the name registers are used by the processor for
transferred to the destination over bus C.
functions, including holding operands of the register is given in the instruction. temporary storage during execution of
If needed, the ALU may simply pass one of
Operating Steps Absolute mode: The operand is in a some instructions. The multiplexer MUX
its two input operands unmodified to bus
• Programs reside in the memory through memory location; the address of this selects either the output of register Y or a
C. We will call the ALU control signals for
input devices. location is given explicitly in the constant value 4 to be provided as input A
such an operation R=A or R=B. The three-
• PC is set to point to the first instruction. instruction. of the ALU
bus arrangement obviates the need for
• The contents of PC are transferred to Immediate mode: The operand is given specified sequence:
registers Y and Z. A second feature is the
MAR. A read signal is sent to the memory. explicitly in the instruction • Transfer a word of data from one
introduction of the Incrementer unit,
• The first instruction is read out and Indirect mode: The effective address of processor register to another or to the
which is used to increment the PC by 4.
loaded into MDR. the operand is the contents of a register ALU
Using the Incrementer eliminates the need
• The contents of MDR are transferred to that is specified in the instruction.We • Perform an arithmetic or a logic
to add 4 to the PC using the main ALU
IR. denote indirection by placing the name of operation and store the result in a
The control sequence for executing this
• Decode and execute the instruction. Get the register given in the instruction in processor register
instruction is given as below
operands for ALU (Address to MAR – Read parentheses • Fetch the contents of a given memory
Step 1: the contents of the PC are passed
– MDR to ALU). Indexing and Arrays The next addressing location and load them into a processor
through the ALU, using the R=B control
• Perform operation in ALU and Store the mode we discuss provides a different kind register
signal, and loaded into the MAR to start a
result back to general-purpose register. of flexibility for accessing operands. It is • Store a word of data from a processor
memory read operation. At the same time
• Transfer the result to memory (address useful in dealing with lists and arrays register into a given memory location
the PC is incremented by 4
to MAR, result to MDR – Write). Index mode: The effective address of the Step 2: the processor waits for MFC and
• During the execution, PC is incremented operand is generated by adding a constant loads the data received into MDR.
to the next instruction value to the contents of a register. The Step 3: Transfersthe data received in MDR
BUS STRUCTURES register used in this mode is refereed as to IR.
The bus consists of three sets of lines used the index register Step 4: The execution phase of the
to carry address, data, and control signals. Relative mode: The effective address is instruction requires only one control step
I/O device interfaces are connected to determined by the Index mode using the to complete.
these lines program counter in place of the general-
Each I/O device is assigned a unique set of purpose register Ri.
addresses for the registers in its interface. Auto-increment mode:The effective
When the processor places a particular address of the operand is the contents of a
address on the address lines, it is register specified in the instruction.
examined by the address decoders of all Auto-decrement mode:The contents of a
devices on the bus. The device that register specified in the instruction are
recognizes this address responds to the first automatically decremented and are
commands issued on the control lines then used as the effective address of the
The processor uses the control lines to operand.
request either a Read or a Write
operation, and the requested data are
transferred over the data lines. When I/O
devices and the memory share the same
address space, the arrangement is called
memory-mapped I/O

MEMORY LOCATIONS AND ADDRESSES

The memory consists of many millions of
storage cells, each of which can store a bit
MULTIPLE BUS ORGANIZATION
of information having the value 0 or 1. The
DIRECT MEMORY ACCESS SEMICONDUCTOR RAM MEMORIES MAPPING FUNCTIONS CONTENT ADDRESSABLE MEMORY
 It is a technique used for high speed I/O Semiconductor memories are available in The mapping functions are used to map a (CAM)/ ASSOCIATIVE MEMORY
device. a wide range of speeds. Their cycle times particular block of main memory to a The established way to search a table is to
 Here, the device interface transfer data range from 100ns to less than 10 ns particular block of cache store all items where they can be
directly to or from the memory without Static Memories (SRAM) Three mapping functions: addressed in sequence. The search
continuous involvement by the processor Static memories are the memories that  Direct mapping. procedure is a strategy for choosing a
 A special control unit may be provided to consist of circuits capable of retaining  Associative mapping. sequence of addresses, reading the
allow the transfer of large block of data at their state as long as power is applied.  Set-associative mapping. Direct content of memory at each address, and
high speed directly between the external Two transistor inverters are cross Mapping comparing the information read with the
device and main memory, without connected to implement a basic flip-flop. A particular block of main memory can be item being searched until a match occurs.
continuous intervention by the processor. The cell is connected to one word line and brought to a particular block of cache The number of accesses to memory
This approach is called DMA. two bits lines by transistors T1 and T2. memory. So, it is not flexible. The simplest depends on the location of theitem and
 DMA transfers are performed by a When word line is at ground level, the way of associating main memory blocks the efficiency of the search algorithm. The
control circuit called the DMA Controller. transistors are turned off and the latch with cache block is the direct mapping time required to find an item stored in
To initiate the transfer of a block of words retains its state. technique. In this technique, block k of memory can be reduced considerably if
, the processor sends, Read operation: In order to read state of main memory maps into block k modulo m stored data can be identified for access by
 Starting address SRAM cell, the word line is activated to of the cache, where m is the total number the content of the data itself rather than
 Number of words in the block close switches T1 and T2. Sense/Write of blocks in cache. by an address. A memory unit accessed by
 Direction of transfer. When a block of circuits at the bottom monitor the state of content is called an associative memory or
data is transferred , the DMA controller b and b‟. Write operation: During the Content Addressable Memory (CAM)
increment the memory address for write operation, the state of the cell is set This type of memory is accessed
successive words and keep track of by placing the appropriate value on bit line simultaneously and in parallel on the basis
number of words and it also informs the b and its complement on b‟ and then of data content rather than by specific
processor by raising an interrupt signal. activating the word line address or location
While DMA control is taking place, the Dynamic Memories (DRAM)
program requested the transfer cannot Static RAMs are fast, but the cost is too
continue and the processor can be used to high because their cells require several
execute another program. After DMA transistors.Less expensive RAMs can be
transfer is completed, the processor implemented if simpler cells are used.
returns to the program that requested the Such cells don't retain their state
transfer. indefinitely; hence they are called dynamic
R/W - Determines the direction of RAMs
transfer. Read Operation: Transistor turned on,
R/W =1, DMA controller read data from Sensor check voltage of capacitor. If
memory to I/O device. R/W =0, DMA voltage is less than Threshold value,
Associative mapping
controller perform write operation. Done Capacitor discharged and it represents
In the associative mapping technique, a
Flag=1, the controller has completed logical „0‟ else if voltage is above
main memory block can potentially reside
transferring a block of data and is ready to Threshold value, Capacitor charged to full
in any cache block position. In this case,
receive another command. IE=1, it causes voltage and it represents Logical „1‟ Write
the main memory address is divided into
the controller to raise an interrupt Operation - Transistor is turned on and a
two groups, a low-order bit identifies the
(interrupt Enabled) after it has completed voltage is applied/removed to the bit line.
location of a word within a block and a
transferring the block of data. IRQ=1, it CACHE MEMORIES
high-order bit identifies the block
indicates that the controller has requested Cache Memory is a special very high-speed
an interrupt. memory. It is used to speed up and
Use of DMA controllers in a computer synchronizing with high-speed CPU. Cache
system memory is costlier than main memory or
Burst Mode: The DMA controller may be disk memory but economical than CPU
given exclusive access to the main registers. Cache memory is an extremely
memory to transfer a block of data fast memory type that acts as a buffer
without interruption. This is known as between RAM and the CPU. It holds
Burst/Block Mode frequently requested data and instructions
Bus Master: The device that is allowed to so that they are immediately available to
initiate data transfers on the bus at any the CPU when needed
given time is called the bus master. Set-Associative mapping
Bus Arbitration: It is the process by which This mapping technique is intermediate to
the next device to become the bus master the previous two techniques. Blocks of the
is selected and the bus mastership is Existence of a cache is transparent to the cache are grouped into sets, and the
transferred to it processor. The processor issues Read and mapping allows a block of main memory
Cycle Stealing: Write requests in the same manner. If the to reside in any block of a specific set.
Requests by DMA devices for using the bus data is in the cache, it is called a Read or Therefore, the flexibility of associative
are having higher priority than processor Write hit. Read hit: The data is obtained mapping is reduced from full freedom to a
requests. Top priority is given to high from the cache. Write hit: Cache has a set of specific blocks. This also reduces the
speed peripherals such as ,  Disk  High replicaof the contents of the main searching overhead, because the search is
speed Network Interface and Graphics memory. Contents of the cache and the restricted to number of sets, instead of
display device. Since the processor main memory may be updated number of blocks. Also the contention
originates most memory access cycles, the simultaneously.This is the write-through problem of the direct mapping is eased by
DMA controller can be said to steal the protocol. Update the contents of the having a few choices for block
memory cycles from the processor. This cache, and mark it as updated by setting a replacement.
interviewing technique is called Cycle bit knownas the dirty bit or modified bit
stealing Read miss: Block of words containing this
requested word is transferred from the
memory
Write-miss: Write-through protocol is
used, and then the contents of the main
memory areupdated directly.