DIGITAL ELECTRONICS

Contents:
S.No Topic Page no.
1. Analog and digital signals, logic gates, Boolean Algebra, 2 – 20
Demorgan’s theorem, Number system, 1’s complement, 2’s
complement arithmetic operations, number system conversion.
2. Codes: BCD, Excess code, Gray code, Octal code, Hexadecimal 21 – 25
code, Alphanumeric codes, Error codes.
3. Digital logic families. 26 – 33
4. Combinational logic design: K – Map. 34 – 43
5. Arithmetic circuits, BCD to Seven segment decoder, Binary to 44 – 53
gray code converter, gray to binary converter, multiplexers, DE
multiplexers.
6. Adders, subtraction, BCD arithmetic, digital comparators, Parity 54 – 65
generators/Checkers, BCD to binary converter, Binary to BCD,
Priority encoders: Decimal to BCD encoder, octal to binary, BCD
to decimal decoder BCD to seven segment decoder I/C.
7. Flip flops. 66 – 71
8. Counters. 72 – 76
9. A/D and D/A converters. 77 – 87
10. Semiconductor memories. 88 – 94
11. Programmable logic devices. 95 – 96
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 CHAPTER – 1
Analog and Digital Signals:
There are basically two types of signals, analog and digital.
a) Analog signals: Analog signal is defined as voltage or current whose size is proportional to the quantity
it represents. Analog signal is continuous and has infinite set of possible values.
In the real work most of the quantities such as sound, velocity, weight, pressure and temperature etc
are analog in nature. For this reason, analog signals that often represent these values are the most
common type monitored, processed and controlled by electronic circuitry.
b) Digital Signals: A digital signal is one which changes between two discrete levels of voltage. These
changes are very sudden. Figure illustrate that the most positive fixed voltage represents 1 state.
Similarly most negative voltage represents 0 state.
Digital signals represent the real quantities by means of group of 0 and1. Group of 0 and 1s in some
orderly format can represent unlimited information.

Analog and Digital Systems:

The different electronic systems can be classified as:
a) Analog systems: Analog system is one which contains devices that manipulate physical quantities
which are represented in analog form. In an analog system, the quantities can vary over a continuous
range of values. For example, the amplitude of the output signal to the speaker in radio receiver can
have any value between zero and its maximum limit. Commonly used analog systems are T.V receiver,
telephone systems and Magnetic tape recording and playback equipment.
b) Digital Systems: Digital system consists of devices designed to handle physical quantities that are
represented in digital form i.e. they can take only discrete values. Some of the digital systems are
digital computers, calculators, digital watches and traffic signal controller.
Advantages of Digital Systems: Most of the applications in electronics use digital methods to perform
operations that were once performed using analog methods. The main advantages are:
i) Digital systems are easier to design.
ii) Information can be stored very easily.
iii) Accuracy and precision are greater in digital systems.
iv) Operation of the digital systems can be programmed by a set of stored instructions.
v) Digital circuits are less affected by the noise.
vi) More digital circuitry can be fabricated on IC chips as compared to analog circuitry.
vii) Digital systems and equipment are easier to use, primarily because direct display of data is convenient
to read.

Logic Gates and Boolean Expressions:

AND Operation:
Y = A AND B AND C …… AND N
= A.B.C……N
= ABC……N

Truth table of a 2 – input AND Gate:

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 Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR Operation:
Y = A OR B OR C ……. OR N
= A + B + C + ……. + N
Truth table of 2 – input OR Gate:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

NOT Operation:
Y = NOT A
=A̅
Truth table of NOT Gate:
Inputs Output
A B Y
0 1 1
1 0 0

NAND Operations:
Y = (̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
AB … … . . N)
Truth table of NOT Gate:
Inputs Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NAND Gate as a universal Gate

NOR Operation:
Y’ = A + B + ……. + N
Y = Y̅′ = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
A + B + ⋯+ N
3

Truth table of 2 – input NOR Gate:

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 Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOR Gate as a universal Gate.

Exclusive OR Gate:
Y=AB
= A̅ B + AB
̅
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Exclusive NOR Gate:

Y=A B
̅̅̅̅̅̅̅̅
̅B
= AB + A ̅
Inputs Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Question:
The output of an exclusive – NOR gate is 1. Which input combination is correct? (DMRC 2016)
a) A = 1, B = 0 c) A = 0, B = 0
b) A = 0, B = 1 d) None of the above
Ans. c
Question:
The output of an AND gate with three inputs A, B and C, is HIGH when _________ (DMRC 2016)
a) A = 1, B = 1, C = 0 c) A = 1, B = 1, C = 1
b) A = 0, B = 0, C = 0 d) A = 1, B = 0, C = 1
Ans. c
Question:
What is the output state of an AND gate if the inputs are 0 and 1? (DMRC JE)
4

a) 0 c) 3
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b) 1 d) 2
 Ans a
Question:
A NOT gate has (DMRC JE)
a) Two inputs and one output c) One input and two outputs
b) One input and one output d) None of the above
Ans. b
Question:
An OR gate has (DMRC JE)
a) Two inputs and one output c) One input and two outputs
b) One input and one output d) None of the above
Ans. a
Question:
The output of a logic gate can be one of two ______? (DMRC JE)
a) Inputs c) States
b) Gates d) None
Ans. a
Question:
Logic states can only be _____ or 0. (DMRC JE)
a) 3 c) 1
b) 2 d) 0
Ans. c
Question:
The output of a _______ gate is only 1 when all of its inputs are 1 (DMRC JE)
a) NOR c) AND
b) XOR d) NOT
Ans. c
Question:
A NAND gate is equivalent to an AND gate pulse a _______ gate put together (DMRC JE)
a) NOR c) XOR
b) NOT d) None
Ans. b
Question:
Universal gates are: (JE Signal Telecom)
a) AND, OR c) OR, NOT
b) AND, NOT d) NAND, NOR
Ans. d
Question:
AND Act as a (JE Signal Telecom)
a) Parallel circuit c) Series parallel circuit
b) Series circuit d) None of the above
Ans. b
Question:
The output of a two input NAND gate is low: (JE Signal Telecom)
a) Only if both the inputs are high c) Only if one input is high and the other is low
b) Only if both the inputs are low d) Only if at least one of the input is low
Ans. a

Boolean Algebra:
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Theorem 1.1: A + 0 = A
 If A = 0 then 0 + 0 = 0 = A
And if A = 1 then 1 + 0 = 1 = A
And hence the theorem is proved
Table: Boolean algebraic theorems
Theorem No. Theorem
1.1. A+0=A
1.2. A.1 = A
1.3. A+1=1
1.4. A.0 = 0
1.5. A+A=A
1.6. A.A = A
1.7. A+A ̅=1
1.8. ̅
A. A = 0
1.9. A. (B + C) = AB + AC
1.10. A + BC = (A + B)(A + C)
1.11. A + AB = A
1.12. A (A + B) = A
1.13. A+A ̅B = (A + B)
1.14. A (A̅ + B) = AB
1.15. AB + AB ̅=A
1.16. (A + B).(A + B ̅) = A
1.17. AB + A ̅C = (A + C) (A̅ + B)
1.18. (A + B)( A̅ + C) = AC + A ̅B
1.19. ̅
AB + AC + BC = AB + AC ̅
1.20. (A + B) (A̅ + C)(B + C) = (A + B)( A
̅ + C)
1.21. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
A. B. C … … . . = A̅+B ̅ + C̅ + ……….
1.22. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
A+B+C+⋯=A ̅. B
̅. C̅ …….

Truth Table to prove Theorem 1.10:

A B C BC A+BC A+B A+C (A + B) (A + C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
De Morgan’s theorems:
̅̅̅̅̅
A. B = A ̅+ B ̅
̅̅̅̅̅̅̅̅
And, A + B = A ̅. B
̅
Truth table to prove De Morgan’s theorems:
A B 𝐀 ̅ ̅ ̅̅̅̅
𝐁 ̅+ 𝐁
𝐀𝐁 𝐀 ̅ ̅̅̅̅̅̅̅̅
𝐀+𝐁 𝐀 ̅. 𝐁
̅
0 0 1 1 1 1 1 1
0 1 1 0 1 1 0 0
1 0 0 1 1 1 0 0
1 1 0 0 0 0 0 0
Now, consider the NAND operation of three variables,
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ABC = ̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅ (AB). C
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̅̅̅̅̅̅̅̅
= (A. B) + C̅
 =A̅+ B ̅ + C̅
In a similar way, the NOR operation of three variable gives
A + B + C = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅ (A + B) + C
̅̅̅̅̅̅̅̅̅̅
= (A + B). C̅ = A
̅. B
̅. C̅

Boolean Laws:
a) Commutative laws:
A+B=B+A

The commutative law of multiplication of two variables is

AB = BA
b) Associative law:
A + (B + C) = (A + B) + C
The associative law of multiplication can be state for three variables as:
A (BC) = (AB) C

c) Distributive law:
A (B + C) = AB + AC

Question:
If two inputs A and B of Figure are applied to input OR gate, find the output waveform

Solution:
When either or both inputs are high, the output Y will be high
Question:
If two inputs A and B of Figure are applied to two input NAND gate find the output waveform.

Solution:
The output is low only when both inputs are high as shown in figure.

Question:
If two waveforms A and B of Figure are applied to two input NOR gate, draw the resulting waveform
produced at the output.
Solution:
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Whenever any input is high, the output is low as shown in Figure.

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 Question:
Inputs A and B of Figure are applied to the X – NOR gate. Draw the resulting waveform produced at the
output.

Solution:
The output goes high only when both inputs are at the same state as shown in figure.
Question:
Apply De Morgan’s theorem to following expressions:
a) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
(A + B) + C̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
b) ̅̅̅̅̅̅̅̅̅̅
̅ + B) + ̅̅̅̅
(A CD
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
c) (A + B)CD̅̅̅̅ + E + F̅
Answer:
a) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
(A + B) + C̅ = ̅̅̅̅̅̅̅̅̅̅
(A + B). C̿ = (A + B)C
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
b) ̅̅̅̅̅̅̅̅̅̅
̅ + B) + CD
(A ̅̅̅̅ = ̅̅̅̅̅̅̅̅̅̅
̅ + B). CD
(A ̅̅̅̅ = (A
̅ + B)CD
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
c) (A + B)CD ̅̅̅̅ + E + F̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (A + B)CD ̅̅̅̅ ̅̅̅̅̅̅̅̅ ̅B
E + F̅ = (A ̅ + C + D)E ̅F

Question:
A NOR gate is equivalent to a bubbled AND gate. This statement is an outcome of: (DMRC 2016)
a) De Morgan’s law c) Law of absorption
b) Involution law d) Idempotent law
Ans. a

Question:
Which of the following relation is true for two digital signals A and B? (DMRC 2016)
a) ̅̅̅̅̅̅̅
A+B = A ̅. B
̅ c) ̅̅̅̅̅̅̅
A+B = A ̅. B
̅ + A.B
̅̅̅̅̅̅̅
b) A + B = A.B ̅̅̅̅̅̅̅ ̅
d) A + B = A. B
Ans. a

Question:
The number of bits in a nibble is (DMRC JE)
a) 16 c) 4
b) 5 d) 8
Ans. c

Number System:
Binary – to – Decimal Conversion:
Any binary number can be converted into its equivalent decimal number using the weights assigned to
each bit position.

Question:
Find the decimal equivalent of the binary number (1 1 1 1 1)2
Answer:
The equivalent decimal number is
8

= 1 X 24 + 1 X 23 + 1 X 22 + 1 X 21 + 1 X 20
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= 16+ 8 + 4 + 2 + 1 = (31)10
 Question:
Determine the decimal numbers represented by the following binary numbers:
a) 110101 c) 111111111
b) 101101 d) 00000000
Answer:
a) (110101)2 = 1 X 25+ 1 X 24 + 0 X 23 + 1 X 22 + 0 X 21+ 1 X 20
= 32 + 16 + 0 + 4 + 0 + 1 = (53)10
b) (101101)2 = 32 + 0 + 8 + 4 + 0 + 1 = (45)10
c) (11111111)2 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1 = (255)10
d) (00000000)2 = (0)10

Question:
Convert (13)10 to an equivalent base 2 number
Answer:

Thus, (13)10 = (1101)2

Question:
Convert (0.65625)10 to an equivalent base – 2 number
Answer:

Thus, (0.65625)10 = (0.10101)2

Question:
Express the following decimal numbers in the binary form
a) 25.5 b) 10.625 c) 0.6875
Answer:
a) Integer part

Therefore, (25)10 = (11001)2

Fractional part

i.e. (0.5)10 = (0.1)2

Therefore, (25.5)10 = (1100.1)2
b) Integer part (10)10 = (1010)2
Fractional part
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i.e, (0.625)10 = (0.101)2

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Therefore, (10.625)10 = (1010.101)2

 c)

Therefore,
(0.6875)10 = (0.1011)2

Signed Binary Numbers:

Sign – Magnitude Representation:
In the decimal number system a plus (+) sign is used to denote a positive number and a minus () sign for
denoting a negative number. The plus sign is usually dropped and the absence of any sign means that the
number has positive value. This representation of numbers is known as signed number. As is well known,
digital circuits can understand only two symbols, 0 and 1; therefore, we must use the same symbols to
indicate the sign of the number also. Normally, an additional bit is used as the sign bit and it is placed as
the most significant bit. A 0 is used to represent a positive number and a 1 to represent a negative number.
For example, an 8 – bit signed number 01000100 represents a positive number and its value (magnitude) is
1000100)2 = (68)10. The left most 0 (MSB) indicates that the number is positive. On the other hand, in the
signed binary form, 11000100 represents a negative number with magnitude (10001002 = (68)10. The 1 in
the left most position (MSB) indicates, that the number is negative and the other seven bits give its
magnitude. This kind of representation for signed numbers is known as sign magnitude representation. The
user must take care to see the representation used while dealing with the binary numbers.
Question:
Find the decimal equivalent of the following binary numbers assuming sign magnitude representation of
the binary numbers.
a) 101100 c) 0111
b) 001000 d) 1111
Solution:
a) Sign bit is 1, which means the number is negative.
Magnitude = 01100 = (12)10
 (101100)2 = (12)10
b) Sign bit is 0, which means the number is positive
Magnitude = 01000 = 8
 (001000)2 = (+8)10
c) (0111)2 = (+7)2
d) (1111)2 = (7)2
Question:
Find the one’s complement of the following binary number
a) 0100111001 b) 11011010
Answer:
a) 1011000110 b) 00100101
Question:
Represent the following numbers in one’s complement form
a) +7 and 7 b) +8 and 8 c) +15 and 15
Answer:
In one’s complement representation
a) (+7)10 = (0111)2
And, ( 7)10 = (1000)2
b) (+8)10 = (01000)2
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And (8)10 = (10111)2

c) (+15)10 = (01111)2
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And (15)10 = (10000)2

 From the above examples, it can be observed that for an n – bit number, the maximum positive
number which can be represented in 1’s complement representation is (2n – 1 – 1) and the maximum
negative number is – (2n – 1 – 1)
Two’s Complement Representation:
If 1 is added to 1’s complement of a binary number, the resulting number is known as the two’s
complement of the binary number. For example, 2’s complement of 0101 is 1011. Since 0101 represents
(+5)10 therefore, 1011 represents (– 5)10, therefore, 1011 represents (– 5)10, in 2’s complement
representation. In this representation also, if the MSB is 0 the number is positive, whereas if the MSB is 1
the number is negative. For an n – bit number, the maximum positive number which can be represented in
2’s complement form is (2n – 1 – 1) and the maximum negative number is  2n – 1. Table gives sign –
magnitude, 1’s and 2’s complement number represented by 4 – bit binary numbers. From the table, it is
observed that the maximum positive number is 0111 = +7, whereas the maximum negative number is 1000
=  8 using four bits in 2’s complement format.
It is also observed that the 2’s complement of the 2’s complement of a number is the number itself.
Table:
Sign – magnitude, 1’s and 2’s complement representation using four bits
Decimal number Binary number
Sign magnitude One’s complement Two’s complement
0 0000 0000 0000
1 0001 0001 0001
2 0010 0010 0010
3 0011 0011 0011
4 0100 0100 0100
5 0101 0101 0101
6 0110 0110 0110
7 0111 0111 0111
8   1000
7 1111 1000 1001
6 1110 1001 1010
5 1101 1010 1011
4 1100 1011 1100
3 1011 1100 1101
2 1010 1101 1110
1 1001 1110 1111
0 1000 1111 

Question:
Find the 2’s complement of the numbers:
a) 01001110 b) 00110101
Solution:

From the above example, we observe the following:

1. If the LSB of the number is 1, its 2’s complement is obtained by changing each 0 to 1 and 1 to 0 except
the least significant bit.
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 2. If the LSB of the number is 0, its 2’s complements is obtained by scanning the number from the LSB to
MSB bit by bit and retaining the bits as they are up to and including the occurrence of the first 1 and
complement all other bits.
Question:
Find two’s complement of the numbers:
i) 01100100 iii) 11011000
ii) 10010010 iv) 01100111
Solution:
Using the rules of conversion given above, we obtain

i) Number 2’s complement 01100100

10011100

ii) Number 2’s complement 10010010

01101110

iii) Number 2’s complement 11011000

00101000

iv) Number 2’s complement 01100111

10011001
Question:
Represent (17)10 in
i) Sign – magnitude iii) Two’s complement representation
ii) One’s complement
Answer:
The minimum number of bits required to represent (+17)10 in signed number format is six
 (+17)10 = (010001)2
Therefore (17)10 = (010001)2
Therefore (17)10 is represented by
i) 110001 in sign – magnitude representation
ii) 101110 in 1’s complement representation
iii) 101111 in 2’s complement representation

Binary addition:
The rules of binary addition are given in table
Table:
Rules of binary addition
Augend Addend Sum Carry Result
0 0 0 0 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 10
In the first three rows above, there is no carry, that is, carry = 0, whereas in the fourth row a carry is
produced (since the largest digit possible is 1), that is, carry = 1 and similar to decimal addition it is added
to the next higher binary position.

Question:
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Add the binary numbers

i) 1011 and 1100 ii) 0101 and 1111
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Solution:
 Question:
Add the binary numbers:
01101010
00001000
10000001
11111111
Answer:

 The sum = 1 1 1 1 1 0 0 1 0
From the above example, we observe the following:
i) If the number of 1’s to be added in a column is even then the sum bit is 0 and if the number of 1’s to be
added in a column is odd then the sum bit is 1.
ii) Every pair of 1’s in a column produces a carry (1) to be added to the next higher bit column.

Binary Subtraction:
The rules of binary subtraction are given in table
Table:
Rules of binary subtraction
Minuend Subtrahend Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Except in the second row above, the borrow = 0. When the borrow = 1, as in the second row, this is to be
subtracted from the next higher binary bit as it is done in decimal subtraction.

Question:
Perform the following subtraction:

Here, in columns 1 and 2, borrow = 0 and in column 3 it is 1. Therefore, in column 4 first subtract 0 from 1
and from this result obtained subtract the borrow bit.

Binary Multiplication:
13

Binary multiplication is similar to decimal multiplication. In binary, each partial product is either zero
(multiplication by 0) or exactly same as the multiplicand (multiplication by 1). An example of binary
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multiplication is given below.

 Question:
Multiply 1001 by 1101
Solution:

In a digital circuit, the multiplication operation is performed by repeated addition of all partial products to
obtain the full product.

Binary Division:
Binary division is obtained using the same procedure as decimal division. An example of binary division is
given below

Question:
Divide 1 1 1 0 1 0 1 by 1 0 0 1
Solution:

Addition/Subtraction in 2’s complements Representation:

The addition/subtraction of signed binary numbers can most conveniently be performed using 2’s
complement representation of both the operands. This is the method most commonly used when these
operations are performed using digital circuits and microprocessors.

Question:
Perform the following operations using 2’s complement method:
i) 48 – 23 iv)  48 – 23
ii) 23 – 48
iii) 48 – ( 23)
Use 8 – bit representation of numbers
Solution:
i) 2’s complement representation of +48 = 00110000
2’s complement representation of 23 = 11101001
48 + ( 23)

ii) 2’s complement representation of +23 = 0 0 0 1 0 1 1 1

2’s complement representation of 48 = 1 1 0 1 0 0 0 0
23 – 48 = 23 + ( 48)
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iii) 48 – ( 23) = 48 + 23
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 iv)  48 – 23 = ( 48) + ( 23)

From the above example, we observe the following:

a) If the two operands are of the opposite sign, the result is to be obtained by the rule of subtraction
using 2’s complement.
b) If the two operands are of the same sign, the sign bit of the results (msb) is to be compared with the sig
bit of the operands. In case the sign bits are same. The result is correct and is in 2’s complement form.
If the sign bits are not same there is a problem of overflow i.e. the result cannot be accommodated
using the eight bits and the result is to be interpreted suitably. The result in this case will consist of nin
bits i.e. carry and eight bits and the carry bit will give the sign of ht enumber.

Octal Number System:

Question:
a) Convert (247)10 into octal
b) Convert (0.6875)10 into octal
c) Convert (3287.55100098)10 into octal
Solution:
a)

Thus (247)10 = (367)8

b)

Thus (0.6875)10 = (0.54)8

c) Integer part

Thus (3287)10 = (6327)8

Fractional part:

Thus, (0.5100098)10 = (0.4051)8

Therefore, (3287.5100098)10 = (6327.4051)8
From the above examples we observe that the conversion for fractional numbers may not be exact. In
general, an approximate equivalent can be determine by terminated the process of multiplication by
eight at the desired point.
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Octal to Binary conversion:

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 Octal numbers can be converted into equivalent binary numbers by replacing each octal digit by its 3 – bit
equivalent binary. Table gives octal numbers and their binary equivalents for decimal numbers 0 to 15.

Question:
Convert (736)8 into an equivalent binary number
Solution:
From table, we observer the binary equivalents of 7, 3 and 6 as 111, 011 and 110, respectively. Therefore,
(736)8 = (111 011 110)2
Binary – to – Octal conversion:
Binary numbers can be converted into equivalent octal numbers by making groups of three bits starting
from LSB and moving towards MSB for integer part of the number and then replacing each group of three
bits by its octal representation. For fractional part, the groupings of three bits are made starting from the
binary point.
Question:
Convert (10011110)2 to its octal equivalent
Answer:
(1001110)2 = (001 001 110)2
= (1 1 6)8 = (116)8

Question:
Convert (0.10100110)2 to its equivalent octal number
Answer:
(0.10100110)2 = (0.101 001 100)2
= (0.5 14)2 = (0.514)2

Question:
Convert the following binary numbers to octal numbers
a) 11001110001.000101111001
b) 1011011110.11001010011
c) 111110001.10011001101
Solution:
a) 011 001 110 001.000 111 001= (3161.0571)8
b) 001 011 011 110.110 010 100 110 = (1336.6246)8
c) 111 110 001.100 110 011 010 = (761.4632)8
From the above examples we observe that in forming the 3 – bit groupings, 0’s may be required to
complete the first (most significant digit) group in the integer part and the last (least significant digit)
group in the fractional part.

Octal Arithmetic:
Octal arithmetic rules are similar to the decimal or binary arithmetic. Normally, we are not interested in
performing octal arithmetic operations using octal representation of numbers. This number system is
normally used to enter long strings of binary data into a digital system like a microcomputer. This makes
the task of entering binary data in a microcomputer easier. Arithmetic operations can be performed by
converting the octal numbers to binary numbers and then using the rules of binary arithmetic.

Question:
Add (23)8 and (97)8
Solution:
16
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 Question:
Subtract
a) (37)8 from (67)8
b) (75)8 from (26)8
Solution:
Using 8 – bit representation

Two’s complement of 11011001 = 00 100 111 = (47)8

Multiplication and division can also be performed using the binary representation of octal numbers and
then making use of multiplication and division rules of binary numbers.

Table:
Binary and decimal equivalents of octal numbers
Octal Decimal Binary
0 0 000
1 1 001
2 2 010
3 3 011
4 4 100
5 5 101
6 6 110
7 7 111
10 8 001000
11 9 001001
12 10 001010
13 11 001010
14 12 001011
15 13 001100
16 14 001110
17 15 001111

Hexadecimal number system:

Table:
Binary and decimal equivalents of hexadecimal number
Hexadecimal Decimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
17

8 8 1000
9 9 1001
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A 10 1010
 B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111

Hexadecimal – to – Decimal conversion:

Using equation, hexadecimal numbers can be converted to their equivalent decimal numbers.
Question:
Obtain decimal equivalent of hexadecimal number (3A.2F)16
Answer:
Using equation
(3A.2F)16 = 3 X 16’ + 10 X 160 + 2 X 161+ 15 X 162
2 5
= 48 + 10 + + = (58.1836)10
16 162
The fractional part may not be an exact equivalent and therefore, may give a small error.
Decimal – to – Hexadecimal Conversion:
For conversion from decimal to hexadecimal, the procedure used in binary as well as octal systems is
applicable, using 16 as the dividing (for integer part) and multiplying (for fractional part) factor.

Question:
Convert the following decimal numbers into hexadecimal numbers.
a) 95.5 b) 675.625
Solution:
a) Integer part

Therefore, (95.5)10 = (5F.8)16

b) Integer part

Therefore, (675.625)10 = (2A3.A)16

Hexadecimal – to binary Conversion:

Hexadecimal numbers can be converted into equivalent binary numbers by replacing each hex digit by its
equivalent 4 – bit binary number.

Question:
18

Convert (2F9A)16 to equivalent binary number.

Answer:
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Using table, find the binary equivalent of each hex digit

 (2F9A)16 = (0010 1111 1001 1010)2
= (0010111110011010)2

Binary – to – Hexadecimal conversion:

Binary numbers can be converted into the equivalent hexadecimal numbers by making groups of four bits
starting from LSB and moving towards MSB for integer part and then replacing each group of four bits by
its hexadecimal representation.
For the fractional part, the above procedure is repeated starting from the bit next to the binary point and
moving towards the right.

Question:
Convert the following binary numbers to their equivalent hex numbers.
a) 10100110101111 b) 0.00011110101101
Solution:

 (0.00011110101101)2 = (0.1EB4)16

Conversion from Hex – to – Octal and Vice – Versa:

Hexadecimal numbers can be converted to equivalent octal number and octal numbers can be converted
to equivalent hex numbers by converting the hex/octal number to equivalent binary and then to octal/hex,
respectively.

Question:
Convert the following hex numbers to octal numbers.
a) A72E b) 0.BF85
Solution:

Question:
Convert (247.36)8 to equivalent hex number.
Solution:
(247.36)8 = (010 100111.011 110)2
= (0 1010 0111.0111 1000)2 = (A 7.78)16

Hexadecimal Arithmetic:
The rules for arithmetic operations with hexadecimal numbers are similar to the rules for decimal, octal
and binary systems. The information can be handled only in binary form in a digital circuit and it is easier to
enter the information using hexa – decimal number system. Since arithmetic operations are performed by
the digital circuits on binary numbers, therefore hexadecimal numbers are to be first converted into binary
numbers. Arithmetic operations will become clear from the following examples.
Question:
Add (7F)16 and (BA)16
19

Answer:
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 Question:
Subtract
a) (5C)16 from (3F)16
b) (7A)16 from (C0)16
Solution:

Two’s complement of 11100011 = 0001 1101 = (1D)16

Multiplication and division can also be performed using the binary representation of hexadecimal numbers
and then making use of multiplication and division rules of binary numbers.
20
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 CHAPTER – 2
Codes:
Computers and other digital circuits process data in the binary format. Various binary codes are used to
represent data which may be numeric, alphabets or special characters. Although, in every code used the
information is represented in binary form, the interpretation of this binary information is possible only if
the code in which this information is available is known. For example, the binary number 1000001
represents 65 (decimal) in straight binary, 41 (decimal) in BCD and alphabet A in ASCII code. A user must be
very careful about the code being used while interpreting information available in the binary format. Codes
are also used for error detection in digital systems.
Some of the commonly used codes are given below.
Straight binary code:
This is used to represent numbers using natural (or straight) binary form. Various arithmetic operations can
be performed in this form. Binary codes for decimal numbers 0 to 15 are given in table.
Natural BCD Code:
In this code, decimal digits 0 through 9 are represented (coded) by their natural binary equivalents using
four bits and each decimal digit of a decimal number is represented by this four bit code individually. For
example, (23)10 is represented by 0010 0011 using BCD code, rather than (10111) 2. From this it is observed
that is requires more number of bits to code a decimal number using BCD code than using the straight
binary code. However, inspite of this disadvantage it is very convenient and useful code for input and
output operations in digital systems.
This code is also known as 8 – 4 – 2 – 1 code or simply BCD code 8,4,2 and 1 are the weights of the four bits
of the binary code of each decimal digit similar to straight binary number system. Therefore, this is a
weighted code and arithmetic operations can be performed using this code, which will be discussed BCD
codes for decimal digits 0 through 9 are given in table.

Table:
Various binary codes
Decimal number Binary BCD Excess – 3 Gray
B3 B2 B1 B0 D C B A E 3 E2 E1 E0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1
2 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 1
3 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 0
4 0 1 0 0 0 1 0 0 0 1 1 1 0 1 1 0
5 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1
6 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1
7 0 1 1 1 0 1 1 1 1 0 1 0 0 1 0 0
8 1 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0
9 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

Excess code:
21

This is another form of BCD code, in which each decimal digit is coded into a 4 – bit binary code. The code
for each decimal digit is obtained by adding decimal 3 to the natural BCD code of the digit. For example,
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decimal 2 is coded as 0010 + 0011 = 0101 in Excess 3 code. It is not a weighted code. This code is a self
 complementing code, which means 1’s complement of the coded number yields 9’s complement of the
number itself. For example, Excess – 3 code of decimal 2 is 0101, its 1’s complement is 1010 which is
excess – 3 code for decimal 7, which is 9’s complementing of 2. The self complementing property of this
code helps considerably in performing subtraction operation in digital systems. Excess – 3 codes for
decimal digits 0 through 9 are given in table.

Gray code:
It is very useful code in which a decimal number is represented in binary form in such a way so that each
Gray code number differs from the preceding and the succeeding number by a single bit. For example, the
Gray code for decimal number 5 is 0111 and for 6 is 0101. These two codes differ by only one bit position
(third from the left). This code is used extensively for shaft encoders because of this property. It is not a
weighted code. The Gray code is a reflected code and can be constructed using this property as given
below.
i) A 1 – bit Gray code has two code words 0 and 1 representing decimal numbers 0 and 1 respectively.
ii) An n – bit (n  2) Gray code will have first 2n – 1 Gray code of (n – 1) bits written in order with a leading 0
appended.
iii) The last 2n – 1 Gray code will be equal to the Gray code words of an (n – 1) – bit Gray code, written in
reverse order (assuming a mirror placed between first 2n – 1 and last 2n – 1 Gray codes) with a leading 1
appended.

Question:
Determine (a) 1 – bit (b) 2 – bit (c) 3 – bit Gray codes and tabulate along with their equivalent decimal
number.
Answer:
a) 1 – bit gray code is constructed using (i) above
Decimal number Gray code
0 0
1 1
b) 2 – bit gray code is constructed using (ii) and (iii) above and gray code of 1 – bit
Decimal number Gray code
0 00
1 01
2 11
3 10
c) 3 – bit gray code is constructed using 2 – bit gray code
Decimal number Gray code
0 000
1 001
2 011
3 010
4 110
5 111
6 101
7 100

Octal code:
It is a 3 – bit binary code, in which each of the octal digits 0 through 7 is coded into 3 – bit straight binary
number. For example, code for octal digit 4 is 100. Using this code, octal numbers can be coded into
straight binary form or the binary numbers can be represented by octal numbers as discussed.
22

This code is used for binary inputs in digital computers, microprocessor etc.
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 Hexadecimal code:
It is a 4 – bit binary code used for input/output in digital computer microprocessors etc.

Question:
Represent the decimal number 27 in binary form using
i) Binary code iii) Excess – 3 code v) Octal code
ii) BCD code iv) Gray code vi) Hexadecimal code
Solution:
i) The decimal number is converted into straight binary form. Its value is 11011
ii) Each digit of the decimal number is code using 4 – bit BCD code as given below.
0010 0111
iii) Each digit of the decimal number is coded using 4 – bit excess – 3 code as given below
0101 1010
iv) 5 bit are required to represent 27, therefore, 5 – bit Gray code is constructed and 27 is represented as
10110
v) (27)10 = (33)8 = 011 011
vi) (27)10 = (1B)16 = 0001 1011
Question:
Represent the decimal number (a) 396 and (b) 4096 in binary form in
i) Binary code (straight ii) BCD code iv) Octal code
binary) iii) Excess – 3 code v) Hex code
Answer:
a)
i) 396 = 110001100
ii) 396 = 001110010110
iii) 396 = 011011001001
iv) 396 = (614)8 = 110001100
v) 396 = (18C)16 = 000110001100
b)
i) 4096 = 1000000000000
ii) 4096 = 0100000010010110
iii) 4096 = (10000)8 = 001 000 000 000 000
iv) 4096 = (1000)16 = 0001 0000 0000 0000
Alphanumeric code:
Table:
Some alphanumeric codes:
Character 6 – bit Internal code 8 – bit EBCDIC code 12 – bit Hollerith code
A 010001 11000001 12, 1
B 010010 11000010 12, 2
C 010011 11000011 12, 3
D 010100 11000100 12, 4
E 010101 11000101 12, 5
F 010110 11000110 12, 6
G 010111 11000111 12, 7
H 011000 11001000 12, 8
I 011001 11001001 12, 9
J 100001 11010001 11, 1
K 100010 11010010 11, 2
23

L 100011 11010011 11, 3

M 100100 11010100 11, 4
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 N 100101 11010101 11, 5
O 100110 11010110 11, 6
P 100111 11010111 11, 7
Q 101000 11011000 11, 8
R 101001 11011001 11, 9
S 110010 11100010 0, 2
T 110011 11100011 0, 3
U 110100 11100100 0, 4
V 110101 11100101 0, 5
W 110110 11100110 0, 6
X 110111 11100111 0, 7
Y 111000 11101000 0, 8
Z 111001 11101001 0, 9
0 000000 11110000 0
1 000001 121110001 1
2 000010 11110010 2
3 000011 11110011 3
4 000100 11110100 4
5 000101 11110101 5
6 000110 11110110 6
7 000111 11110111 7
8 001000 11111000 8
9 001001 11111001 9
Blank 110000 01000000 No punch
. 011011 01001011 12, 3, 8
( 111100 01001101 12, 5, 8
+ 010000 01001110 12, 6, 8
Error codes:
When the digital information in the binary form is transmitted from one circuit or system to another circuit
or system an error may occur. This means a signal corresponding to 0 may change to 1 or vice versa. In
complex digital systems, millions of bits per second are manipulated and it is desired to have high data
integrity, or at least a violation of data integrity must be detectable.
A simple process of improving data integrity in digital system is by adding one additional bit in the data
known as parity bit. This extra bit allows the detection of a single error in transmission. By parity we mean
the number of 1’s in a digital data which may be even (even parity) or odd (odd parity) In ASCII (ask – key)
code, C is coded as 1000011. There are three 1’s in this and we say that its parity is OIDD. If we add an
extra bit b1, the total number of ones in the 8 – bit code corresponding to C will be ODD if b7= 0 and EVEN
if b7 = 1. This extra bit is transmitted from the transmitting end along with the code and the parity of the 8
– bit code is checked at the receiving end if there is an error in one bit or in an odd number of bits, it can
be detected. However, if even numbers of bits are transmitted incorrectly, the error can not be detected.
In fact, there is considerable improvement in data integrity with the addition of the parity bit.

Question:
(3527)8 is equivalent to (DRDO 2008)
a) (757)16 c) (131113)4
b) (1879)10 d) All of these
Question:
The number of digits in octal system is (DMRC JE)
24

a) 8 c) 10
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b) 7 d) None
 Question:
The number of digits in Hexadecimal system is (DMRC JE)
a) 15 c) 16
b) 17 d) 8
Ans. c
Question:
Which of the following binary numbers is equivalent to decimal 10 (DMRC JE)
a) 1000 c) 1010
b) 1100 d) 1001
Ans. c
Question:
The number FF in Hexadecimal system is equivalent to _____ in decimal system (DMRC JE)
a) 256 c) 240
b) 255 d) 239
Ans. b
Question:
The total number of Boolean functions that can be constructed for n Boolean variables is (DRDO 2008)
a) n c) (2n)n
n
b) 2n d) 2(2 )
Ans. b
25
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 CHAPTER – 3
Digital Logic Families:
Bipolar Logic Families:
The main elements of a bipolar IC are resistors, diodes (which are also capacitors) and transistors. Basically,
there are two types of operations in bipolar ICs:
1. Saturated, and
2. Non – Saturated
In saturated logic, the transistors in the IC are driven to saturation, whereas in the case of non –
saturated logic, the transistors are not driven into saturation.
The saturated bipolar logic families are:
1. Resistor – transistor logic (RTL)
2. Direct – coupled transistor logic (DCTL)
3. Integrated – injection logic (I2L)
4. Diode – transistor logic (DTL)
5. High – threshold logic (HTL), and
6. Transistor – transistor logic (TTL)
The non – saturated bipolar logic families are:
1. Schottky TTL, and
2. Emitter – coupled logic (ECL)

Unipolar Logic Families:

MOS devices are unipolar devices and only MOSFET’s are employed in MOS logic circuits. The MOS logic
families are:
1. PMOS 2. NMOS 3. CMOS
While in PMOS and p – channel MOSFETs are used in NMOS only n – channel MOSFETs are used, in
complementary MOS (CMOS), both p – and n – channel MOSFETs are employed and are fabricated on
the same silicon chip.
Characteristic of Digital ICs:
With the widespread use of ICs in digital systems and with the development of various technologies for the
fabrication of ICs, it has become necessary to be familiar with the characteristic of IC logic families and
their relative advantages and disadvantages. Digital ICs are classified either according to the complexity of
the circuit, as the relative number of individual basic gates (2 – input NAND gates) it would require to build
the circuit to accomplish the same logic function or the number of components fabricated on the chip. The
classification of digital ICs is given in table.

Classification of digital ICs:

IC Classification Equivalent individual basic gates Number of components
Small – scale integration (SSI) Less than 12 Up to 99
Medium scale integration (MSI) 12 – 99 100 – 999
Large scale integration (LSI) 100 – 999 1000 – 9999
Very large scale integration (VL SI) 1000 – 9999 10000 – 99999
Ultra large scale integration (ULSI) 10,000 or more 100000 and above
The various characteristic of digital ICs used to compare their performance are:
1. Speed of operation 5. Current and voltage parameter
2. Power dissipation 6. Noise immunity
3. Figure of merit 7. Operating temperature range
4. Fan out 8. Power supply requirements
26

Speed of operation:
Page
 The speed of a digital circuit is specified in terms of the propagation delay time. The input and output
waveforms of a logic gate are shown in Figure. The delay times are measured between the 50 percent
voltage levels of input and output waveforms. There are two delay times: t pHL, when the output goes from
the HIGH state to LOW state and tpLH, corresponding to the output making a transition from the LOW state
to HIGH state. The propagation delay time of the logic gate is taken as the average of these two delay
times.

Power Dissipation:
This is the amount of power dissipated in an IC. It is determine by the current, I CC that it draws from the VCC
supply, and is given by VCC X ICC. ICC is the average value of ICC (0) and ICC (I). This power is specified in
milliwatts.

Figure of Merit:
The figure of merit of a digital IC is defined as the product of speed and power. The speed is specified in
terms of propagation delay time expressed in nanoseconds.
Figure of merit = propagation delay time (ns) X power (mW)
It is specified in pico joules (ns X mW = pJ)
A low value of speed power product is desirable. In a digital circuit, if it is desired to have high speed i.e.
low propagation delay, then there is a corresponding increases in the power dissipation and vice – versa.

Fan out:
This the number of similar gates which can be driven by a gate. High fan out is advantageous because it
reduces the need for additional drivers to drive more gates.

Current and voltage parameters:

The following currents and voltages are specified which are very useful in the design of digital systems.
High level input voltage, VIH: This the minimum input voltage which is recognized by the gate as logic 1.
Low level input voltage, vIL: This is the maximum input voltage which is recognized by the gate as logic 0.
Low – level output voltage, VOH: This is the minimum voltage available at the output corresponding to logic
1.
Low – level output voltage, VOL: This is the maximum voltage available at the output corresponding to logic
0.
High level input current, IIH: This is the minimum current which must be supplied by a driving source
corresponding to 1 level voltage.
Low level input current, IIL: This the minimum current which must be supplied by a driving source
corresponding to 0 level voltage.
High level output current, IOH: This is the maximum current which the gate can sink in 1 level.
Low level output current, IOL: This is the maximum current which the gate can sink in 0 level.
High level supply current, ICC (1): This the supply current when the output of the gate is at logic 1.
Low – level supply current, ICC (0): This is the supply current when the output of the gate is at logic (0).
The current direction are illustrated in Figure.
27

Noise Immunity:
The input and output voltage levels defined above are shown in figure. Stray electric and magnetic fields
Page

may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may
 cause the voltage at the input to a logic circuit to drop below V IH or rise above VIL and may produce
undesired operation. The circuit’s ability to tolerate noise signals is referred to as noise immunity a
quantitative measure of which is called noise margin.

Operating temperature:
The temperature range in which an IC functions properly must be known. The accepted temperature
ranges are: 0 to + 700C for consumer and industrial applications and – 550C to + 1250C for military purpose.

Power Supply Requirements:

The supply voltage (s) and the amount of power required by an IC are important characteristics required to
choose the proper power supply.

Switching Devices as Logic Gates:

AND
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

Resistor transistor logic (RTL):

NOT
A B Y
0 Y 1
1 N 0
Shortcut:
Column = AND separation
Row = OR separation
28

(Same for N – MOS)

Page

NAND
 AB Q1 Q2 Y
00 N N 1
01 N Y 1
10 Y N 1
11 Y Y 0

NOR
AB Q1 Q2 Y
00 N N 1
01 N Y 0
10 Y N 0
11 Y Y 0

Direct coupled transistor logic (DCTL):

It is the same as that of RTL except that input resistor are removed.
They suffer with current hogging problem.

Current Hagging:
Because of different saturation levels of loading gates, current will be blocked or hogged in certain loads
only and certain loads are in the saturation of current known as current hogging problem.

N – MOS
N – MOS  Gate  (+)ve  ON ( ve)
Gate  ()ve  OFF

NOT
A n1 n2 Y
0 Y N 1
1 Y Y 0

NAND
A B n1 n2 n3 Y
00 Y N N 1
01 Y N Y 1
10 Y Y N 1
11 Y Y Y 0
29

NOR
Page
 AB n1 n2 n3 Y
00 Y N N 1
01 Y N Y 0
10 Y Y N 0
11 Y Y Y 0

P – MOS
P – MOS  Gate  (+)ve  OFF
Gate  ()ve  ON

NOT
A P1 P2 Y
0 Y Y (GND) 1
0 Y N ( VDD) 0

NOR
Shortcut is opposite to N – MOS
A B P1 P2 P3 Y
00 Y Y Y 1 GND
01 Y Y N 0  VDD
10 Y N Y 0  VDD
11 Y N N 0  VDD

NAND
A B P1 P2 P3 Y
00 Y Y Y 1
01 Y Y N 1
10 Y N Y 1
11 Y N N 0

C – MOS
NOT
A P n Y
0 Y N 1  VDD
1 N Y 0 GND

NAND
Use shortcut seeing N – MOS column multiplication AND operation
A B P1 P2 n1 n2 Y
00 Y Y N N 1 VDD
01 Y Y N Y 1 VDD
10 N Y Y N 1 VDD
11 N N Y Y 0 GND

NOR
30

A B P1 P2 n1 n2 Y
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00 Y Y N N 1 VDD
 01 Y Y N Y 0 GND
10 N Y Y N 0 GND
11 N N Y Y 0 GND

DTL
NAND
= D1 + D2 + VBE (SAT)
= 0.7 + 0.7 + 0.7 = 2.1
= 0.7 + 0.7 + 0.8 (sat) = 2.2V
Given:
VY = 0.7V
VBE (ON) = 0.7V
VBE (Sat) = 0.8V,  = 25
VCE (Sat) = 0.1V
Case (i):
Vx = 0.1V, Vy = 0.1V
VCC − V1 5−0.8
4= = = 1.05mA
R1 4K
i2 = i B = i R = 0
 Q is cutoff
 Y = High (5V)
Case (ii):
Vx = 0.1V, Vy = 5V
Same as that of (i)
 Y = high (5V)
Case (iii):
Vx = 5V, Vy = 0.1V
Same as that of case (i) and Case (ii)
 Y = High (5V)

Saturation condition:
i′c

iB
1.22+(1.05)
 25
0.62
N = 13.7
N  13
Case (ii): Output of the driving gate is high
In this case, input diode of the loading gate is reverse biased and there exist a reverse saturation current
which passes through RC of driving gate from + VCC. By N number of loads, we get much voltage drop across
RC and output alters from high value which lead to improper operation so even in this case also there is a
limit on fan out.
Note:
Among the above two cases the least value should be taken for the overall fan out. So, the output low case
is preferable.

Procedure to find Noise Margin:

Case (i): Output of the driving gate is low
In this case, the other section of the loading gate requires D1 + D2 + VBE (ON) = 0.7 + 0.7 + 0.7 = 2.1N
31

So the difference of voltage 2.1 – 00.8 = 1.3V

Is the acceptable fluctuating voltage so the noise margin is 1.3V
Page

Case (ii): Output of the driving gate is high

 In this case also, the noise margin will be calculated and among the above two cases the least value is
preferable for overall value of noise margin.
Power dissipation P.D = Vcc Icc
P.D (0) + P.D (1)
P.D =
2

TTL:
NAND NOT

The purpose of D1: It avoids the ringing problem. The negative voltage fluctuations can be grounded by D 1
and the input transistor will be safe.
The purpose of D2: It is used for the proper switching voltages at the output.
TTL Technologies are three types.
1) Totem pole TTL: In this case, output transistors are not ON simultaneously. The above discussed
example is totem pole TTL only.
2) Open collector TTL: In this case, the collector section of output transistor and a pull up resistor is used
for proper switching output.
Note:
Pull up resistor also avoids voltage fluctuations of power supply.
Open collector TTL allows wired logic.

Wired Logic:
Wired AND Logic Wired OR Logic

3) Tristate logic:
In the case of tristated logic, there will be 3 states, logic 0, logic 1 and high impedance state.

Voltage and current Parameters:

High Low

NMH = VOH – V1H

Noise Margin
32

IOH
Fan out =
IIH
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Take whichever value is less of NM Take whichever value is less of

 IOL
Fan out = fan out.
IIL
NML = VIL – VOL

Question:
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Design f = AB + C (D + E)
Using NMOS Using PMOS

Using CMOS
Consider both NMOS & PMOS circuit

Shortcut: To Know which gate it is

Applicable to Column – multiplication AND operation
all except PMOS Row – OR operation
PMOS Column – OR operation
Row – AND operation
Question:
The fastest logic family used in high speed as application is (JE Signal Telecom)
a) DTL c) ECL
b) TTL d) RTL
Ans. c
33
Page
 CHAPTER – 4
Combinational logic design:
Karnaugh Map Representation of Logical Functions:
We have discussed the two standard forms of logical functions and their realization using gates. We have
also established the need for the simplification of the Boolean expressions and introduced the algebraic
method of simplification using Boolean algebraic theorems. Sometimes it is difficult to be sure that a
logical expression can be simplified. There is another technique, which is graphical known as the Karnaugh
map technique which provides a systematic method for simplifying and manipulating Boolean expressions.
In this technique, the information contained in a truth table or available in POS or SOP form is represented
on Karnaugh map (K – map). This is perhaps the most extensively used tool for simplification of Boolean
functions. Although the technique may be used for any number of variables, it is generally used up to six
variables beyond which it becomes very cumbersome.

Above figure shows the K – maps for two, three and four variables. In an n – variable K – map there are 2n
cells. Each cell corresponds to one of the combination of n variables, since there are 2 n combinations of n
variables. Therefore, we see that for each row of truth table, for each minterm and for each Maxterm
there is one specific cell in the K – map. The variables have been designated as A, B, C and D and the binary
numbers formed by them are taken as AB, ABC, and ABCD for two, three, and four variables respectively.
In each map the variables and all possible values of the variables are indicated (the first bit corresponds to
the first variable and the second bit corresponds to the second variable) to identify the cells. Gray code has
been used for the identification of cells. The reason for using Gray code will become clear when we discuss
the application of K – map. You can verify the decimal number corresponds to each cell which is written in
the top left corner of the cell as shown in Figure.
Figure shown the minterm/Maxterm corresponding to each cell and the term is written inside the cell for
clear understanding.

Representation of truth table on K – map:

Consider the truth table of the 3 – variable logic function given in table 3. The output Y is logical 1
corresponding to the rows 1, 2, 4 and 7. Corresponding to this we can write the equation in terms of
standard SOP as given below:
Y=A ̅B ̅BC̅ + AB
̅C + A ̅C̅ + ABC  14
Equation (14) represents the complete truth table in standard SOP form. Similarly, we note that the output
Y is logical 0 corresponding to the rows 0, 3, 5 and 6 and the output Y can be represented in terms of
standard POS form as given below.
Y = (A + B + C)(A + B̅ + C̅)( A
̅ + B + C̅)( A
̅+ B
̅ + C)  15
34
Page
 Equation (15) also represents the complete truth table, and equation (14) and (15) are equivalent. We shall
make use of the 3 – variable K – map of figure (b) and enter the value of the output variable Y (0 or 1) in
each cell corresponding to its decimal or minterm or Maxterm identification. Figure gives the complete K –
map of the truth table given in table 3
The procedure used above is general and is used to represent a truth table on the K – amp. On the other
hand, if a K – map is given we can make the truth table corresponding to this by following the reverse
process. That is, the output Y is logical 1 corresponding to the decimal numbers/minterms represented by
cells with entries 1. In all other rows, the output Y is logical 0.

Table (3):
Truth table of a 3 – variable function
Row number Inputs Output
A B C Y
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1

Question:
Prepare the truth table for K – map of figure

Solution:
The truth table is given in table
Note that the 0’s are not written in the K – map of Figure. Actually, we need enter either 0’s and 1’s only in
the K – map. If only 1’s are entered the empty cells are 0’s and if only 0’s are entered then the empty cells
are 1’s.

Question:
35

Simplify Boolean function represented in sum of product of min – terms, (ISRO)

F(x, y, z) = (0, 2, 4, 5, 6)
Page

a) z' + xy’ b) x’y’z’ + xyz + xy’z’

 c) xyz + x’ + y’ + z’ d) xy + yz + zx
Ans. a

Table 4:
Truth table for K – map of figure
Row number Inputs Output
A B C D Y
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 1
13 1 1 0 1 0
14 1 1 1 0 1
15 1 1 1 1 1

Representation of Standard SOP Form on K – Map:

A logical equation in standard SOP form can be represented on a K – map by simply entering 1’s in the cells
of the K – map corresponding to each minterm present in the equation.

Question:
Represent equation (14) on K – map
Solution:
Corresponding to each minterm in the equation, there is a cell in the K – map and a 1 is entered in each
one of these cells. The K – map will be as shown in figure.
Similarly, from the K – map, we can write the corresponding logical equation in standard SOP from by
ORing ht minterms corresponding to each 1 entry in the K – map.

Question:
Write the logical equation in the standard SOP form for the K – map of figure above.
Solution:
Y=A ̅B
̅C̅D
̅ + ABC̅D̅+ A ̅BC̅D̅ + AB̅C̅D + A̅BCD + ABCD + ABCD ̅
= m(0, 5, 7, 9, 12, 14, 15)  16
If the equation is in SOP form, it can be converted to standard SOP form by using the method discussed
earlier and then it can be represented on K – map. Another method of representing SOP form on K – map
without converting it to standard SOP form will become clear from the discussion of following sections.

Representation of Standard POS Form on K – map:

Logical equation in standard POS form can be represented on K – map by entering 0’s in the cells of K –
map corresponding to each Maxterm present in the equation.
36

Question:
Page

Represent equation (15) on K – map

 Solution:
Corresponding to each max term in the equation, there is a cell in the K – map and a 0 is etered in each one
of these cells. The K – map will be as shown in figure.
From a given K – map, we can write the logical equation in the standard POS form by ANDing the maxterms
corresponding to each 0 entry in the K – map.

Question:
Write the logical equation in the standard POS from for the K – map of figure.
Solution:
̅ ) (A + B + C̅ + D) (A + B + C̅ + D
Y = (A + B + C + D ̅)
̅ + C + D) (A + B
(A + B ̅ + C̅ + D) (A ̅ + B + C + D)
̅ + B + C̅ + D) (A
(A ̅ + B + C̅ + D ̅+B
̅ ) (A ̅+C+D ̅)
= M (1, 2, 3, 4, 6, 8, 10, 11, 13)  17
If the equation is in POS form, it can be converted into standard POS form by the method discussed earlier
and then it can be represented on K – map. Another method of representing POS form on K – map without
converting it to standard POS form will become clear from the discussion of next sections.
Equation (16) represents the K – map of figure in standard SOP form and equation (17) represents the
same K – map in standard POs form. Therefore, these two equations are equivalent. Alternatively stated,
an equation in SOP form can be converted into an equivalent POS form and vice – versa.

Simplification of Logical functions Using K – Map:

Simplification of logical functions with K – map is based on the principal of combining terms in adjacent
cells. Two cells are said to be adjacent if they differ in only one variable. For example, in the two – variable
K – maps of figure (a) and (b), the top two cells are adjacent and the bottom two cells are adjacent. Also
the left two cells and the right two cells are adjacent. It can be verified that in adjacent cells one of the
literals is same, whereas the other literal appears in uncomplemented form in one and in the
complemented form in the other cell.
Similarly, we observe adjacent cells in the 3 – variable and 4 – variable K – maps. Table 5 gives the adjacent
cells in 2 –, 3 –, and 4 – variable K – maps. From this it becomes clear that if the Gray code is used for the
identification of cells in K – map, physically adjacent (horizontal and vertical but not diagonal) cells differ in
only one variable. Also, the left most cells are adjacent to their corresponding right most cells and similarly
the top cells are adjacent to their corresponding bottom cells. The simplification of logical function is
achieved by grouping adjacent 1’s or 0’s in groups of 2’. Where i = 1, 2, ………. N and n is the number of
variables.

Grouping two adjacent ones:

If there are two adjacent ones on the map, these can be grouped together and the resulting term will have
one less literal than the original two terms. It can be verified for each of the groupings of two ones as given
in table 5.
Table 5:
Adjacent cells in K – maps
Cell with decimal Decimal numbers of adjacent cells
number 2 – variable 3 – variable 4 – variable
0 1,2 1, 2,4 1, 2, 4, 8
1 0, 3 0, 3, 4 0, 3, 5, 9
2 0, 3 0, 3, 6 0, 3, 6, 10
3 1, 2 1, 2, 7 1, 2, 7, 11
4 0, 5, 6 0, 5, 6, 12
37

5 1, 4, 7 1, 4, 7, 13
6 2, 4, 7 2, 4, 7, 14
Page

7 3, 5, 6 3, 5, 6, 15
 8 0, 9, 10, 12
9 1, 8, 11, 13
10 2, 8, 11, 14
11 3, 9, 10, 15
12 4, 8, 13, 14
13 5, 9, 12, 15
14 6, 10, 12, 15
15 7, 11, 13, 14

Question:
Simplify the K – map of figure

Solution:
The standard SOP form of equation can be written by inspection as
Y=A ̅B̅C̅ + A
̅BC + ABC + AB ̅C̅  18
If we combine the ones in adjacent cells (0, 4) and (3, 7) equation (18) can be written as
Y = (A̅ + A) B
̅C̅ + (A
̅ + A)BC  19
̅ ̅
= BC + BC  20
Equation (20) can be directly obtained from the K – map by using the following procedure:
1. Identify adjacent ones, then see the values of the variables associated with these cells. Only one
variable will be different and gets eliminated. Other variables will appear in ANDed form in the term, it
will be in the uncomplemented for if it is 1 and in the complemented form if it is 0.
2. Determine the term corresponding to each group of adjacent ones. These terms are ORed to get the
simplified equation in SOP form.

Grouping Four adjacent ones:

Four cells form a group of four adjacent ones if two of the literal associated with the minterms/maxterms
are not same and the other literals are same. Table 6 gives all possible groups of four adjacent ones for
each cell in a 3 – variable map. In case of 2 – variable map, there is only one possibility corresponding to
entry 1 in all the four cells, and the simplified will be Y = 1. That is, Y always equals 1 (independent of the
variables).
On the basis of grouping of 4 adjacent ones given in table 6 we can find the groupings in K – maps of four
or more variables. In the case of a four variable K – map, there are six possible of 4 – variables involving
any cell. It is left to the reader to verify this fact.

Table 6:
Groups of four adjacent ones in a 3 – variable K – map
Cell with decimal number Decimal numbers of cells forming groups of adjacent fours
0 (0, 2, 6, 4), (0, 1, 2, 3), (0, 1, 4, 5)
1 (1, 0, 2, 3), (1, 3, 7, 5), (1, 0, 4, 5)
2 (2, 0, 6, 4), (2, 3, 1, 0), (2, 3, 6, 7)
3 (3, 1, 7, 5), (3, 2, 1, 0), (3, 2, 6, 7)
4 (4, 6, 2, 0), (4, 5, 6, 7), (4, 5, 0, 1)
5 (5, 1, 3, 7), (5, 4, 6, 7), (5, 4, 0, 1)
6 (6, 0, 2, 4), (6, 7, 4, 5), (6, 7, 2, 3)
38

7 (7, 1, 3, 5), (7, 6, 4, 5), (7, 6, 2, 3)

Page

Question:
 Simplify the K – map of figure
Solution:
The standard SOP form of equation can be written by inspection as
Y = m0 + m1 + m3 + m7 + m8 + m9 + m11 + m15
= (m0 + m1 + m8 + m9) + (m3 + m7 + m15 + m11)  21
In the K – map of figure, there are two groups of four adjacent ones. One corresponding to cells 0, 1, 8 and
9 and the other one corresponding to 3, 7, 15 and 11

In equation 21, the minterms corresponding to each group are combined. The first term can be written as
m0 + m1 +m8 + m9 = A ̅B
̅ C̅D
̅+ A ̅B
̅ C̅D + AB
̅ C̅D + AB̅ C̅D ̅ C̅D
̅ + AB
̅ ̅ ̅ ̅ ̅
= BC (AD + AD + AD + AD)̅
= B̅C̅ [A
̅ (D̅ + D) + A(D ̅ + D)]
= B̅C̅ [A
̅ . 1 + A. 1]
= B̅C̅ [A
̅ + A] = B ̅C̅. 1 = B ̅C̅
In the first term of equation (21) we observe the following
1. In this group of four minterms, two of the variables appear as B ̅ and C̅ in all the four terms.
2. The variable A appears as A in two and as A ̅ in the other two minterms.
3. The variable D appears as D in two and as D ̅ in the other two minterms.
4. The combination of these four minterms results in one term with two literals which are present in all
the four terms. Similarly, the second term of equation (21) is simplified to CD. Therefore, the K – map is
simplified to
Y=B ̅C̅ + CD

Grouping eight adjacent ones:

Eight cells form a group of eight adjacent ones if three of the literals associated with the minterms/max
terms are not same and the other literals are same. In case of 3 – variable K – map, there is only one
possibility of eight ones appearing in the K – map and this corresponds to output equal to 1, irrespective of
the values of the input variables. Table 7 gives all possible groups of eight adjacent ones in a 4 – variable K
– map. From an understanding of this, we can easily find out such combinations for 5 – and 6 – variables K
– maps. When eight adjacent ones are combined, the resulting equation will have only one term with the
number of literals, three less than the number of literals in the original minterms. Similar to the groupings
of adjacent two and four ones, the literals which are common in all the eight minterms will be present and
the literals which are not same get eliminated in the resulting term.

Table 7:
Groups of eight adjacent ones in 4 – variable K – map
Decimal numbers of cells forming groups of
adjacent eights in a 4 – variable K – map
0, 4, 12, 8, 1, 5, 13, 9
0, 4, 12, 8, 2, 6, 14, 10
0, 1, 3, 2, 4, 5, 7, 6
0, 1, 3, 2, 8, 9, 11, 10
1, 5, 13, 9, 3, 7, 15, 11
39

4, 5, 7, 6, 12, 13, 15, 14

12, 13, 15, 14, 8, 9, 11, 10
Page

3, 7, 15, 11, 2, 6, 14,10

 The reader is advised to verify the simplification of eight adjacent ones into a single term with three
variables eliminated. For example, let us take the first group of eight adjacent ones in table 7. For all these
eight cells, the variable C appears as C̅ in the minterms and the other three variables are not same.
Therefore, the grouping of these eight cells results in a terms C̅. Figure shows the simplified expression for
each of the groupings of eight ones for a 4 – variable K – map.

Grouping 2, 4 and 8 Adjacent zeros:

In the above discussion, we have considered groups of 2, 4 and 8 adjacent ones. Instead of making the
groups of ones, we can also make groups of zeros. The procedure is similar to the one used above and it as
follows:
1. Group of two adjacent zeros result in a term with one literal less than the number of variables. The
literal which is not same in the max terms gets eliminated.
2. Groups of four adjacent zeros result in a term with two literals less than the number of variables. The
two literals which are not same in all the four max terms get eliminated.
3. Group of eight adjacent zeros result in a term with three literals less than the number of variables. The
three literals which are not same in all eight max terms get eliminated.
We have considered groups of 2, 4 and 8 adjacent ones and zeros. The same logic can be extended to
16, 32 and 64 adjacent ones and zeros which occur in K – maps with more than 4 – variables.

Minimization of logical functions

Specified in minters/maxterms
OR
Truth table
Minimization of SOP form:
We have seen the advantages of simplifying a logical expression. If the expression is simplified to a stage
beyond which it cannot be further simplified, it will require minimum number of gates with minimum
number of inputs to the gates. Such an expression is referred to as the minimized expression.
For minimizing a given expression in SOP form or for a given truth table, we have to prepare the K – map
first and then look for combinations of ones on the K – map. We have to combine the ones in such a way
that the resulting expression is minimum. To achieve this, the following algorithm can be used which will
definitely lead to minimized expression.
1. Identify the ones which cannot be combined with any other ones and encircle them. These are
essential prime implicants.
2. Identify the ones that can be combined in groups of two in only one way. Encircle such groups of ones.
3. Identify the ones that can be combined with three other ones, to make a group of four adjacent ones,
in only one way. Encircle such groups of ones.
4. Identify the ones that can be combined with seven other ones, to make a group of eight adjacent ones,
in only one way. Encircle such groups of ones.
5. After identifying the essential groups of 2, 4 and 8 ones, if there still remains some ones which have not
been encircled ones. Of course, however, we should combine the left over ones in largest possible
groups and in as few groupings as possible. In this, the groupings may not be unique and we should
make the groupings in an optimum manner. You can verify that anyone can be included any number of
times without affecting the expression.
40

The above algorithm will be used to minimize the logical functions in the examples given.
Page
 Question:
Minimize the four variable logic function using K – map
f(A, B, C, D) = m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)  23
Solution:
The K – map of equation (23) id shown in figure. The equation is minimized in the following steps:
1. Encircle 1 in cell 14 which cannot be combined with any other 1. The term corresponding to this is
ABCD ̅.
2. There are at least two possible ways for every 1 forming groups of two adjacent ones. Therefore, we
ignore it for the time being and go to the next step.
3. There is only one possible group of four adjacent one involving each of the cells 8, 11, 5 or 7 and 2, and
these are (8, 9, 0, 1), (11, 9, 1, 3), (5, 7, 3, 1) and (2, 3, 1, 0) respectively. Encircle these groups. The
terms corresponding to these groups are B ̅C̅, B ̅D and A
̅D, A ̅B̅, respectively.
Since all the ones have been encircled, therefore the minimized equation is
̅+B
f (A, B, C, D) = ABCD ̅C̅ + B
̅D + A ̅D + A ̅B̅  24

Question:
Determine the minimized expression in SOP form for the truth table given in table 8
Solution:
The K – map for the truth table of table 8 is shown in figure. Using the minimization steps, we obtain the
minimized expression
Y=B̅ + AC̅ + A
̅ CD  25

Table 8
Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
41
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 Minimization of POS form:
For minimizing a given expression in POS form or for a given truth table we write zeros in the cells
corresponding to max terms for 0 outputs. The K – map is simplified by following the same procedure as
used for SOP form with ones replaced by zeros. In this groups of zeros are formed rather than groups of
ones. We shall minimize the above two examples in POS form.

Question:
Minimize the logic function of equation (23) in POS form.
Solution:
Equation (23) can be expressed in standard POS from as
f(A, B, C, D) = M (4, 6, 10, 12, 13, 15)  26
The K – map corresponding to equation (26) is shown in figure. Note that the K – map can also be obtained
directly from equation (23).

Using steps similar to those outlined for SOP form, we obtain the minimized expression.
̅ + B + C̅ + D).( A
f = (A ̅+B
̅+D ̅ ).(A + B
̅ + D)  27
If we compare equation (24) and (27), we observe that the number of terms are not same in the two
minimizations. In fact, in general the two minimizations will not have the same number of terms and will
require different quantities of hardware. Therefore, one can obtain both minimizations and select the one
which requires minimum hardware. Inn some situations there not be any choice to be designer because of
non – availability of certain ICs.

Question:
Minimize the truth table give in table 8 using maxterms.
Solution:
The K – map is given in figure

The simplified expression is

̅+B
̅ + C) (A
Y = (A + B ̅ + C̅) (B
̅ + C̅ + D)  28
Comparison of equation (25) and (28) confirms our generalizations made in above question regarding the
hardware requirements in the two methods.

Don’t care Conditions:

1. In terms of minterms and don’t care conditions. For example,
f (A, B, C, D) = m (1, 3, 7, 11, 15) + d(0, 2, 5)
Its K – map and the minimized expressions ar given in figure (a)
42

2. In terms of maxterms and don’t care conditions. For example,

f(A, B, C, D) = M (4, 5, 6, 7, 8, 12). d(1, 2, 3, 9, 11, 14)
Page

Its K – map and minimized expression are given in figure.

 3. In terms of truth table, for example, consider the truth table of table.

Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

CHAPTER – 5
Design Examples:
Arithmetic Circuits:
1. Half adder:
Truth table of an half adder
Inputs Output
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table, we obtain the logical expressions for S and C outputs as
S=A ̅=AB
̅B + AB
C = AB
The realization of an half adder using gates is shown in figure.
43
Page
 2. Full adder:
Truth table for a full adder
Inputs Outputs
An Bn Cn – 1 Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The K – maps for the outputs Sn and Cn are given in figure and the minimized expressions are given by
Sn = ̅̅̅̅ ̅̅̅̅̅̅
An Bn C ̅̅̅̅ ̅̅̅̅̅̅
n−1 + An Bn Cn−1 + An Bn Cn−1
Cn = An Bn + Bn Cn−1 + An Cn−1

Sn = ̅̅̅̅ ̅̅̅̅̅̅
An Bn C ̅̅̅̅ ̅̅̅̅ ̅̅̅̅ ̅̅̅̅̅̅
n−1 + An Bn Cn−1 + An Bn Cn−1 + An Bn Cn−1
Cn = AnBn + BnCn – 1 + AnCn – 1
The NAND – NAND realization are given in figure

3. Half subtractor
Table:
Inputs Outputs
A B D C
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
From the truth table, the logical expression for D and C are obtained as
D=A ̅B + AB ̅=AB
C=A ̅B
44

The realization of half subtractor using gates is shown in figure.

Page
 4. Full subtractor:
Truth table of a full subtractor
Inputs Outputs
An Bn Cn – 1 Dn Cn
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
The K – map for Cn is given n figure and its realization is given in figure (b)
The simplified expression for Cn is
Cn = ̅̅̅̅
An Bn + ̅̅̅̅
An Cn−1 + Bn Cn−1

BCD to 7 segment Decoder:

a=B ̅D ̅ + BD + CD + A
b = B + C̅ D
̅ ̅ + CD
c = B + C̅ + D = ̅̅̅̅̅̅
̅CD
B ̅
d = B D + C D + B C + BC̅D
̅ ̅ ̅ ̅
e=B ̅D ̅+CD ̅
f = A + C̅ D
̅ + BC̅ + BD ̅
g = A + BC̅ + B̅C + CD ̅

Truth table:
Truth table of BCD to 7 segment decoder
Decimal digit displayed Inputs Outputs
A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
45

6 0 1 1 0 0 0 1 1 1 1 1
Page

7 0 1 1 1 1 1 1 0 0 0 0
 8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1

The NAND gate realization are shown in figure.

We see from the realization of figure that a term with single literal must be inverted and then applied to
the second level NAND gate.

Question:
Design a binary to Gray code converter.
Answer:
The truth table of binary to gray code converter is given in table. Or each of four outputs, K – maps are
prepared and simplified. The K –maps are prepared and simplified. The K – maps are given in figure and the
simplified expressions are given by equation. The circuit is given,
46

G3 = B3
G2 = B2  B3
Page

G1 = B1  B2
 G0= B0  B1

Question:
Design a gray to binary code converter
Solution:
The truth table for this is given in table. The K – maps are given in figure and the simplest expressions are
given by equation

The converter circuit is given in figure

B3 = G3
B2 = G2  G3
B1 = G1  G2  G3
B0 = G0  G1  G2  G3

Five and Six Variable K – Maps:

Question:
Simplify the logic expression
F (A, B, C, D, E,) = m (0, 5, 6, 8, 9, 10, 11, 16, 20, 24, 25, 26, 27, 29, 31)
Answer:
The K – map is shown in figure and the simplified expression is,
F=A ̅B̅CD ̅E+ A ̅B̅ CD E
̅ + AB ̅D ̅E ̅ + C̅ D
̅E̅ + ABE + BC̅
Above equation can be realized using NAND – NAND configuration.

Question:
Simplify the six variable logic expression.
f (A, B, C, D, E, F) = m (0, 5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44, 46, 55, 56, 57, 60, 61)
Answer:
The K – map of above equation shown in figure and the simplified expression is
F=A ̅B ̅D̅E ̅ F̅ + A̅B̅ C̅ DF + BC̅DE ̅F + BC̅DEF + AB ̅ CF̅ + A̅CE ̅ + BCE ̅
Above equation can be realized using NAND – NAND configuration.
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 Multiplexers and their use in combinational logic design:
Multiplexer:
The multiplexer is a special combinational circuit that is one of the most widely used standard circuits in
digital design. The multiplexer (or data selector) is a logic circuit that gates one out of several to a single
output. The input selected is controlled by a set of select inputs. Figure shows the block diagram of a
multiplexer with n input lines and one output line. For selecting one out of n inputs for connection to the
output, a set of m select inputs is required where 2m = n. Depending upon the digital code applied at the
select inputs one out of n data sources is selected and transmitted to a single output channel. Normally, a
strobe (or enable) input (G) is incorporated which helps in cascading and it is generally active low, which
means it performs its intended operation when it is LOW.

Table:
Truth table of a 4:1multiplexer
Select inputs Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Above table gives the truth table of a 4:1 multiplexer. With LOW input at G, the output Y can be expressed
as
Y = S̅1 ̅̅̅
S0 I0 + S̅1 S0 I1 + S1 ̅̅̅
S0 I2 + S1 S0 I3 1
Equation (1) can be realized using NAND gates and the realization is given in figure.
Combinational logic design using multiplexers:
The multiplexing function discussed above can conventionally be used as a logic element in the design of
combinational circuits. Standard ICs are available for 2:1, 4:1, 8:1, 16:1 multiplexers.

Table:
Available multiplexer ICs
IC Number Description Output
74157 Quad 2:1 Multiplexer Same as output
74158 Quad 2:1 Multiplexer Inverted input
74153 Dual 4:1 Multiplexer Same as input
74152 Dual 4:1 Multiplexer Inverted input
48

74151A 8:1 Multiplexer Complementary outputs

74152 8:1 Multiplexer Inverted input
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74150 16:1 Multiplexer Inverted input

 Use of multiplexers offers the following advantages:
1. Simplification of logic expression is not required.
2. It minimizes the IC package count, and
3. Logic design is simplified
For using the multiplexer as a logic element, either the truth table or one of the standard forms of logic
expression must be available. The design procedure is given below:
1. Identify the decimal number corresponding to each minterm in the expression. The input lies
corresponding to these numbers are to be connected to logic 1 level.
2. All other input lines are to be connected to logic 0 level.
3. The inputs are to be applied to select inputs.
The following examples illustrate the above procedure.
Question:
Implement the expression using a multiplexer
f(A, B, C, D) = m(0, 2, 3, 6, 8, 9, 12, 14)
Solution:
Since there are four variables, therefore a multiplexer with four select inputs is required. The circuit of 16:1
multiplexer connected to implement the above expression is shown in figure. This implementation requires
only one IC package. In case the output of the multiplexer is active low, the logic 0 and logic 1 inputs of
figure are to interchanged. The reader should verify the validity of the statement.

Question:
Realize the logic function of the truth table given in table
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
49

1 1 1 1 1
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 Table:
Inputs Output
A B C Y
0 0 0 0
0 0 1 ̅
D
0 1 0 ̅
D
0 1 1 1
1 0 0 D
1 0 1 1
1 1 0 ̅
D
1 1 1 ̅
D
The second method can also be used if the logic expression is specified.

Multiplexer tree:
Since 16 – to – 1 multiplexers are largest available ICs. Therefore, to meet the larger input needs there
should be a provision for expansion. This is achieved with the help of enable/strobe inputs and multiplexes
stacks or trees are designed. Two commonly used methods for this purpose are illustrated in figures.

These two general techniques can be used to expand to an n input multiplexer without any difficulty.

Demultilexer/Decoders and their use in combination logic design:

Demultilexer:
The Demultilexer performs the reverse operation of a multiplexer. It accepts a single input and distributes
it over several outputs. Figure gives the block diagram of a Demultilexer. The select input code determines
to which the data input will be transmitted.
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 The number of output lines in n and the number of select lines is m, where n = 2 m. This circuit can also be
used as binary to decimal decoder with binary inputs applied at the select input lines and the output will be
obtained on the corresponding line. The data input line is to be connected to logic 1 level. This circuit can
be designed using gates and it is left as an exercise for the reader. However, this device is available as an
MSI IC and can conveniently be used for the design of combinational circuits. The device is very useful if
multiple output combinational circuit is to be designed, because this needs minimum package count. Thse
devices are available as 2 – line to 4 – line, 3 – line to 8 – line, and 4 – line to 16 – line decoders. The
outputs of most of these devices are active low, also there is an active low enable/data input terminal
voltage.
Unlike the multiplexer, the decoder does requires some gates in order to realize Boolean expressions in the
standard SOP form. The following example illustrate its use in combinational logic design.

Table:
Available Demultilexer ICs
IC Number Description Output
74139 Dual 1:4 Demultiplexer Inverted input
(2 – line to 4 – line decoder)
74155 Dual 1:4 Demultiplexer 1Y – Inverted input
(2 – line to 4 – line decoder) 2Y – Same as input
74156 Do Open collector
1Y – Inverted input
2Y – Same as input
74138 1:8 Demultilexer Inverted input
(3 – line to 8 – line decoder)
74154 1:16 Demultilexer Same as input
(4 – line to 16 – line decoder)
74159 Do Same as input
Open collector

Question:
Implement the following multi – output combinational logic circuit using a 4 – to – 16 line decoder.
F1 = m (1, 2, 4, 7, 8, 11, 12, 13)
F2 = m (2, 3, 9, 11)
F3 = m (10, 12, 13, 14)
F4 = m (2, 4, 8)
Answer:
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 The four bit input ABCD is applied at the select input terminals S 3, S2, S1 and S0. The output F1 is required to
be 1 for require to be 1 for minterms 1, 2, 4, 7, 8, 11, 12 and 13. Therefore, a NAND gate is connected as
shown. Similarly NAND gates are used for the outputs F2, F3 and F4. Here, the decoder’s outputs are active
low. Therefore, a NAND gate is required for every output of the combination circuit.
In the combinational logic design using multiplexer, additional gates are not required, whereas design
using Demultilexer requires additional gates. However even with this disadvantage, the decoder is more
economical in cases where non trivial, multiple – output expressions of the same input variables are
required. In such cases, one multiplexer is required for each output whereas it is likely that only one
decoder will be required, supported with a few gates. Therefore, using a decoder could have advantages
over using a multiplexer.

Demultilexer tree:
Since 4 – line – to – 16 – line decoders are the largest available circuits in ICs, to meet the larger inputs
need there should be provision for expansion. This is made possible by using enable input terminal. Figure
shows a 5 – line – 32 – line decoder and figure shows a 8 – line – to – 256 – line decoder using 4 – line – to
– 16 – line decoders. In a similar way, any m line to n line decoder using 4 – line – to 16 – line decoders. In
a similar way, any m – line – to – n – line decoder can be implemented. However if only a few codes of a
large number need be recognized the alternative approach, such as the one shown in figure can be used.
This is connected to detect the digital number 00011111. The most significant 4 – bits are applied at A B C
D inputs and the least significant bits are 0 0 0 1 and the least – significant bits are 1 1 1 1. The circuit can
be expanded to detect other 8 – bit codes.
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 CHAPTER – 6
Adders and their use as subtractor:
Half and full adders and subtractor for two one – bit binary number have been discussed. Using these
circuits, we can design adders and subtractor for n – bit numbers. However, we can perform both addition
and subtraction using only adders because the problem of subtraction becomes that of an addition when
we use 1’s and 2’s complement representation of negative numbers. Therefore, adders have become
widely used standard circuit available in MSI.
An adder circuit for addition of two n – binary numbers consists of n full adder circuits. It accepts two n –
bit binary numbers as inputs and produces an (n + 1) – bit binary number as the sum. Figure (a) below
shows an adder using full adders and figure (b) below shows its block diagram.

Here, A and B are two n – bit inputs to be added and Cn – 1 Sn – 1 Sn – 2 ……S2 S1 S0 is their sum. In this, a half
adder may be used to add the least significant bits A0 and B0. However, for cascading these adders to
increase the number of bits to be added the CARRY input terminal is required for the adder to add the least
– significant bits. Therefore, all the adders used are full adders, 2 – bit and 4 – bit adder circuits are
available in ICs.
If the n – bit adder is implemented using the scheme of figure (a) above, the carry has to ripple down the
line of cascaded adders from the LSB to MSB position. This decreases the operating speed of the adder and
is limited by the amount of time required to complete the ripple carry operation. Adder ICs are designed to
include a special technique for speeding up the carry generation process known as look – ahead carry. This
technique anticipates the carry bits for each stage before the actual summing operation takes place.

Cascading of adders:
The bit lengths of the number to be added can be increased by cascading the adders. Figure shown an 8 –
bit adder using two 4 – bit adders. In a similar way, we can from an adder tree for making an n – bit adder.

Subtraction using adder:

As discussed, the problem of subtraction gets converted into that of addition if 1’s and 2’s complement
representation are used of representing negative numbers. The algorithm for a subtractor using adder is
given in figure below.
The two numbers A and B can be of the same sign or of opposite sign. If the two numbers are of unlike
sign, we may come across the problem of overflow or underflow. Overflow occurs when the subtraction
53

operation produces a number larger than the largest possible number which can be represented by n –
bits. On the other hand, underflow occurs when the result produced is smaller than the smallest number
Page

which can be represented by n – bits. The overflow and underflow logic shown algorithmic. If overflow or
 underflow occurs then the result is wrong. This circuit can be converted into an ADDER/SUBTRACTOR
circuit with ADD/SUB control.

BCD Arithmetic:
Quite often, BCD code is used to represent decimal numbers. For example, in the calculator. Therefore
addition and subtraction are required to be performed in BCD code.

BCD Adder:
The 4 – bit binary adder IC (7483) can be used to perform addition of BCD numbers. In this, if the four bit
sum output is not a valid BCD digit, or if a carry C3 is generated, then decimal 6 (0 1 1 0 binary) is to be
added to the sum to get the correct result. Figure shows a 1 – digit BCD adder. BCD adders can be cascaded
to add numbers several digits long by connecting the carry out of a stage to the carry in of the next stage.

BCD Subtractor:
For BCD subtraction, nine’s complement of the subtrahend is added to the minuend. The nine’s
complement of a BCD number is given by nine minus that number. For example, nine’s complement of 7 =
54

9 – 7 = 2. In BCD code we say that the nine complement of 0 1 1 1 is 0 0 1 0. Examples of BCD subtraction
Page

using nine’s complement to represent negative numbers are given below.

 Question:
a) Subtract 5 from 9 b) Subtract 1 from 8 c) Subtract 8 from 4
Solution:
a) 9 = 1001
 5 = (+) 0100 (nine’s complement of 5)
1101 (Invalid)
Add 0110
10011

1 Add end around carry (EAC)

0100 = +4
b) 8 = 1000
 1 = (+)1000 (nine’s complement of 1)
10000 (Invalid)
Add 0110
10110

1 Add (EAC)
0111 = +7
c) 4 = 0100
 8 = (+) 0001 (nine’s complement of 8)
0101
Nine complement of 0101 = 4
Therefore, the answer is  4

Digital comparators:
Comparators can be designed for comparing multibit numbers. Figure below shows a block diagram of an n
– bit comparator. It receives two n – bit numbers A and B as inputs and outputs are A > B, A = B, and A < B.
Depending upon the relative magnitude of the two numbers, one of the outputs will be HIGH.
Truth table of a 2 – bit comparator
Inputs Outputs
A1 A0 B1 B0 A > B A = B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
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0 1 0 1 0 1 0
0 1 1 0 0 0 1
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0 1 1 1 0 0 1
 1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

Table above gives the truth table of a 2 – bit comparator. Simplify the expressions for A > B, A = B and A <
B outputs using K – map and design the circuit using gates. However, 4 – bit comparators are available in
MSI (7485) which can compare straight binary and natural BCD codes. These ICs can be cascaded to
compare words of greater lengths without external gates. The A > B, A = B, and A < B outputs of a stage
handling less significant bits are connected to the corresponding A > B, A = B, and A < B cascading inputs of
the next stage handling more significant bits. The stage handling the least significant bits musts have A = B
input connected to logic 1 level and A > B and A < B inputs connected to logic 0 or 1 level.

Parity generators/Checkers:
The concept of parity, wherein an additional bit known as the parity – bit is added to a binary word to
make the number of 1’s, in the new work formed, even (even parity) or (odd parity). The circuits of the
generation of parity bits and checking the parity of a given word can be designed using gates. Because of
its wide use, an 8 – bit parity generator/checker circuit has been designed and is available as a MSI chip
(74180).
Figure below gives the block diagram of 74180 in which there are eight parity inputs A through H and two
cascading inputs. There are two outputs EVEN and ODD. Its function table is given in table
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 Table:
Function table of 74180
Parity of inputs A through Cascading inputs Outputs
H EVEN ODD EVEN ODD
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1
The 74180 can be used as a parity generator as well as parity checker. Its function as a parity checker can
be understood from the function table. Its function as a parity generator is given in table below.
Table:
Function table of 74180 as a 9 – bit parity generator
Parity of inputs A though H Cascading inputs Parity of A through Parity of A through
EVEN ODD H and EVEN H and ODD
ODD 1 0 ODD EVEN
EVEN 1 0 ODD EVEN
ODD 0 1 EVEN ODD
EVEN 0 1 EVEN ODD
57

The cascading inputs must not be equal and the unused parity inputs must be tied to logic 0 level.
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Code Converters:
 There is a wide variety of binary codes and used in digital systems. Some of these codes are binary coded
decimal (BCD). Excess – 3, Gray, octal, hexadecimal, etc. Often, it is required to convert from one code to
another. For example the input to a digital system may be in natural BCD and the output may be 7 –
segment LEDs. The digital system used may be capable of processing th data in straight binary format.
Therefore, the data has to be converted from BCD to binary at the output.
The BCD output has to be converted to 7 – segment code before it can be used to drive the LEDs. Similarly,
octal and hexadecimal codes are widely used in microprocessor and digital computers as inputs and
outputs. The various code converters can be designed using gates, multiplexers or Demultilexer. However,
there are some MSI ICs available for performing these conversions and are extremely useful in the design
of digital systems. These devices have been discussed below.

BCD – to – Binary Converter:

The block diagram of BCD – to – binary converter IC 74184 is given in figure (a) below and table below gives
its truth table. This device can be used as a 1½ decade BCD – to – binary converter as shown in figure (b)
below.

The BCD inputs are applied at the input terminals A through E and the LSB of the least significant BCD digit
bypasses the converter and appears as the LSB of the binary output. It accepts two BCD digits – a full digit
D1 C1 B1 A1 and the two least significant bits of a second digit B2 A2. This means that the BCD inputs 00
through 39 can be converted to corresponding binary output by the circuit. Terminals Y 6, Y7 and Y8 are not
used for BCD – to – binary conversion.

Table:
Truth table of 74184 BCD – to – binary converter
BCD Words Inputs Outputs
E D C B A G Y5 Y4 Y3 Y2 Y1
0–1 0 0 0 0 0 0 0 0 0 0 0
2–3 0 0 0 0 1 0 0 0 0 0 1
4–5 0 0 0 1 0 0 0 0 0 1 0
6–7 0 0 0 1 1 0 0 0 0 1 1
8–9 0 0 1 0 0 0 0 0 1 0 0
10 – 11 0 1 0 0 0 0 0 0 1 0 1
12 – 13 0 1 0 0 1 0 0 0 1 1 0
14 – 15 0 1 0 1 0 0 0 0 1 1 1
16 – 17 0 1 0 1 1 0 1 1 0 0 0
18 – 19 0 1 1 0 0 0 1 1 0 0 1
20 – 21 1 0 0 0 0 0 1 1 0 1 0
22 – 23 1 0 0 0 1 0 1 1 0 1 1
24 – 25 1 0 0 1 0 0 1 1 1 0 0
26 – 27 1 0 0 1 1 0 1 1 1 0 1
28 – 29 1 0 1 0 0 0 1 1 1 1 0
58

30 – 31 1 1 0 0 0 0 1 1 1 1 1
32 – 33 1 1 0 0 1 0 0 0 0 0 0
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34 – 35 1 1 0 1 0 0 0 0 0 0 1
 36 – 37 1 1 0 1 1 0 0 0 0 1 0
38 – 39 1 1 1 0 0 0 0 0 0 1 1
Any X X X X X 1 1 1 1 1 1
These terminals are used to obtain the 9’s complement and the 10’s complement of BCD numbers useful
for BCD arithmetic operations. Figure below gives the block diagram of BCD 9’s complement converter and
table below gives truth table.

Table:
Truth table of 74184 as BCD 9’s complement converter
BCD Word Inputs Outputs BCD 9’s complement
E D C B A G Y8 Y7 Y6 ND NC NB NA
0 0 0 0 0 0 0 1 0 1 1 0 0 1
1 0 0 0 0 1 0 1 0 0 1 0 0 0
2 0 0 0 1 0 0 0 1 1 0 1 1 1
3 0 0 0 1 1 0 0 1 0 0 1 1 0
4 0 0 1 0 0 0 0 1 1 0 1 0 1
5 0 0 1 0 1 0 0 1 0 0 1 0 0
6 0 0 1 1 0 0 0 0 1 0 0 1 1
7 0 0 1 1 1 0 0 0 0 0 0 1 0
8 0 1 0 0 0 0 0 0 1 0 0 0 1
9 0 1 0 0 1 0 0 0 0 0 0 0 0
Any X X X X X 1 1 1 1

BCD input is applied at DCBA input terminal and its 9’s complement appears at N D NC NB NA terminal.
Figure below gives the block diagram of BCD 10’s complement converter and table gives its truth table.

Table:
Truth table of 74184 as BCD 10’s complement converter
BCD Word Inputs Outputs BCD 10’s complement
E D C B A G Y8 Y7 Y6 TD TC TB TA
0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 1 0 0 1 0 0 1
2 1 0 0 1 0 0 1 0 0 1 0 0 0
3 1 0 0 1 1 0 0 1 1 0 1 1 1
4 1 0 1 0 0 0 0 1 1 0 1 1 0
5 1 0 1 0 1 0 0 1 0 0 1 0 1
6 1 0 1 1 0 0 0 1 0 0 1 0 0
7 1 0 1 1 1 0 0 0 1 0 0 1 1
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8 1 1 0 0 0 0 0 0 1 0 0 1 0
9 1 1 0 0 1 0 0 0 0 0 0 0 1
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Any X X X X X 1 1 1 1
 The design of circuits for the conversion of 2 or more decades of BCD is quite involved. The circuit for 2
decades of BCD is quite involved. The circuit for 2 – decades BCD – to – binary converter is given in figure
below. The number of 74184 ICs required increases tremendously as the number of input BCD decades
increases. Table gives the number of ICs required for a given number of input BCD decades. From the table
we observe that the circuits become unmanageable for longer BCD words and it may be worthwhile to
examine an alternative approach.

Table:
Number of 74184 ICs required.
Number of
BCD decades 74184 ICs required
2 2
3 6
4 11
5 19
6 28
A read only memory (ROM) may be convenient alternative.

Binary – to – BCD Converter:

The block diagram of binary – to – BCD converter IC 74185A is given in figure and table gives its truth table.
It has the same pin out as the 74184. The binary inputs are applied at terminals A through E and the BCD
outputs are available at terminal Y1 through Y6 (Y7 and Y8 are not used and these are always at logic 1).
Similar to the BCD to binary converter, the least significant bit bypass the circuit as shown in figure below.

Table:
Truth table of 74185A binary – to – BCD converter
Binary words Inputs Outputs
E D C B A G Y6 Y5 Y4 Y3 Y2 Y1
0–1 0 0 0 0 0 0 0 0 0 0 0 0
2–3 0 0 0 0 1 0 0 0 0 0 0 1
4–5 0 0 0 1 0 0 0 0 0 0 1 0
6–7 0 0 0 1 1 0 0 0 0 0 1 1
8–9 0 0 1 0 0 0 0 0 0 1 0 0
10 – 11 0 0 1 0 1 0 0 0 1 0 0 1
12 – 13 0 0 1 1 0 0 0 0 1 0 0 0
14 – 15 0 0 1 1 1 0 0 0 1 0 1 1
60

16 – 17 0 1 0 0 0 0 0 0 1 0 1 0
18 – 19 0 1 0 0 1 0 0 0 1 1 0 1
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20 – 21 0 1 0 1 0 0 0 1 0 0 0 0
 22 – 23 0 1 0 1 1 0 0 1 0 0 0 1
24 – 25 0 1 1 0 0 0 0 1 0 0 1 0
26 – 27 0 1 1 0 1 0 0 1 0 0 1 1
28 – 29 0 1 1 1 0 0 0 1 0 1 0 0
30 – 31 0 1 1 1 1 0 0 1 1 0 0 1
32 – 33 1 0 0 0 0 0 0 1 1 0 0 0
34 – 35 1 0 0 0 1 0 0 1 1 0 1 1
36 – 37 1 0 0 1 0 0 0 1 1 0 1 0
38 – 39 1 0 0 1 1 0 0 1 1 1 0 1
40 – 41 1 0 1 0 0 0 1 0 0 0 0 0
42 – 43 1 0 1 0 1 0 1 0 0 0 0 1
44 – 45 1 0 1 1 0 0 1 0 0 0 1 0
46 – 47 1 0 1 1 1 0 1 0 0 0 1 1
48 – 49 1 1 0 0 0 0 1 0 0 1 0 0
50 – 51 1 1 0 0 1 0 1 0 1 0 0 1
52 – 53 1 1 0 1 0 0 1 0 1 0 0 0
54 – 55 1 1 0 1 1 0 1 0 1 0 1 1
56 – 57 1 1 1 0 0 0 1 0 1 0 1 0
58 – 59 1 1 1 0 1 0 1 0 1 1 0 1
60 – 61 1 1 1 1 0 0 1 1 0 0 0 0
62 – 63 1 1 1 1 1 0 1 1 0 0 0 1
All X X X X X 1 1 1 1 1 1 1
The method of expansion to accommodate larger number of binary inputs is quite complicated. The circuit
for conversion of 8 – bit binary number to BCD is given in figure. This requires three ICs. Table gives the
number of ICs required for a given number of input binary bits. Similar to the BCD to binary converters we
may have to resort to ROM for conversion of longer binary words.

Table:
Number of 74185A ICs required
Number of
Binary bits 74185 ICs required
4–6 1
7, 8 3
9 4
10 6
11 7
12 8
13 10
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14 12
15 14
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16 16
 Priority Encoders:
Decimal – to – BCD Encoder:
One of the most commonly used input device for a digital system is a set of ten switches, one for each
numeral between 0 and 9. These switches generate 1 or 0 logic levels in response to turning then OFF or
ON. When a particular number is to be fed to the digital circuit in BCD code, the switch corresponding to
that number is pressed. There is an IC available for performing this function (74147) which is a priority
encoder. The block diagram of 74147 IC is given in figure and table gives its truth table. It has active low
inputs and outputs. The meaning of the work priority can be seen from the truth table, for example, if
inputs 2 and 5 are LOW, the output will be corresponding to 5 which has a higher priority than 2, i.e. the
highest numbered input has priority over lower numbered inputs.

Table:
Truth table of 74174
Active low decimal points Active low BCD outputs
1 2 3 4 5 6 7 8 9 D C B A

1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 0
X 0 1 1 1 1 1 1 1 1 1 0 1
X X 0 1 1 1 1 1 1 1 1 0 0
X X X 0 1 1 1 1 1 1 0 1 1
X X X X 0 1 1 1 1 1 0 1 0
X X X X X 0 1 1 1 1 0 0 1
X X X X X X 0 1 1 1 0 0 0
X X X X X X X 0 1 0 1 1 1
X X X X X X X X 0 0 1 1 0

Octal – to – Binary Encoder:

The octal code is often used at the inputs of digital circuits that require manual entering of long binary
words. Priority encoder 74148IC has been designed to achieve this operation.
Table:
EI Inputs Outputs
0 1 2 3 4 5 6 7 C B A GS EO
1 X X X X X X X X 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
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0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X X X 0 0 0 0 0 1
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0 1 1 1 1 1 1 1 1 1 1 1 1 0
 Its block diagram is given in figure and table gives its truth table. This circuit also have active low inputs and
active low outputs. The enable input and carry outputs, which are also active low, are used to cascade
circuits to handle more inputs. A hexadecimal – to – binary encoder, which is also a microprocessors, etc
can be designed using this facility.
The priority encoders can conveniently be used for handling priority interrupts in computers,
microprocessors etc.

Decoder/Drivers For Display Devices:

BCD – to – decimal Decoder/Driver:
In many digital systems, we prefer to see the output in a decimal format. The outputs can either be
displayed using display devices like LEDs. Nixie tubes etc or can be used to actuate some indicators or
relays. Table gives the available BCD to decimal decoder/driver ICs. All these ICs have active high inputs
and active low outputs.

Table:
Available BCD – to decimal decoder/driver ICs
IC No. Output circuit Application
7441 Open collector Nixie tube driver
7442 Totem- pole LED driver
7445 Open collector Indicator/relay driver
74141 Open collector Nixie tube driver
74145 Open collector Indicator/relay driver
74445 Open collector Indicator/relay driver

BCD to 7 segment Decoder/Driver:

Seven segment display is the most popular display device used in digital systems. For displaying data using
this device, the data have to converted from BCD to 7 – segment code. A number of MSI ICs are available
for performing this function. The decoder/driver circuit has 4 input lines for BCD data and 7 output lines to
drive a 7 – segment display. Output terminals a through g of the decoder are to be connected to a through
g terminals of the display respectively. If the outputs are active low, then the 7 – segment LED must be of
the common cathode type.

Question:
Design 16 line multiplexer using two 74151 ICs
Answer:
As there are 16 data lines, 4 selections are required. A is the LSB data select line and D is MSB data select
line. When data select is in the range 0000 to 0111, the D line is 0 which enables the low order MUX
selecting D0 to D7, when the select input lies between 1000 to 1111, the high order multiplexer is selected
allowing D8 to D15 to be selected. The output of the two multiplexers is ORed to get combined output.
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 Question:
Use Multiplexer to implement the functions
Y=A ̅B ̅ C̅ + AB
̅ C̅ + AB
̅C + A̅ BC
Answer:
This is the three variable expression and therefore we need a multiplexer with three selection lines and
eight inputs. We will use 74151 MUX, A 1 must be placed at each data, input that satisfies any turn in
Boolean equation.

Question:
How many inputs and outputs does a full adder have?
a) 3, 2 c) 3, 3
b) 2, 3 d) 2, 2
Ans. d
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 CHAPTER – 7
Flip – Flops:
Block diagram of a sequential circuit:

A block diagram of a sequential circuit is shown in figure above. It consists of combinational circuits which
accept digital signals from external inputs and from outputs of memory elements and generates signals for
external outputs and for inputs to memory elements referred to as excitation.
A memory element is some medium in which one bit of information (1 or 0) can be stored or retained until
necessary, and thereafter its contents can be replaced by a new value. The contents of memory elements
in figure above can be changed by the output of combination circuit which are connected to its input.
The combinational circuit performs certain operations, some of which are used to determine the digital
signals to be stored in memory elements. The other operations are performed on external inputs and
memory outputs to generate the external outputs.
The above process demonstrates the dependence of the external outputs of a sequential circuit on the
external input and the present contents of the memory elements (referred to as the present state of
memory elements). The new contents of the memory elements referred to as the next state; depend on
the external inputs and the present state. Hence the output of a sequential circuit is a function of the time
sequence of inputs and the internal states.
Sequential circuits are classified in two main categories, known as asynchronous and synchronous
sequential circuits depending on timing of their signals.
A sequential circuit whose behaviour depends upon the sequence in which input signals change is referred
to as an asynchronous sequential circuit. The outputs will be affected whenever the input changes. The
commonly used memory elements in these circuits are time delay devices. These can be regarded as
combinational circuits with feedback.
A sequential circuit whose behaviour can be defined from the knowledge of its signal at discrete instant of
time is referred to as a synchronous sequential circuit. In these systems, the memory elements are
affected only at discrete instant of time. the synchronization is achieved by a timing device known as a
systems clock which generates a periodic train of clock pulses as shown in figure. The outputs are affected
only which the application of a clock pulse.

Since the design of asynchronous circuits is more – tedious and difficult, therefore their uses are rather
limited.
Synchronous circuits have gained considerable domination and wide popularity and are also known as
clocked sequential circuits. The memory elements used for FLIP – FLOPs which are capable of storing
binary information.

A 1 – Bit memory cell:

The basic digital memory circuit is known as FLIP – FLOP. It has two stable states which are known as the 1
65

states and the 0 state. It can be obtained by using NAND or NOR gate. We shall be systematically
developing a FLIP – FLOP circuit starting from the fundamental circuit shown in figure below. It consists of
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 two inverters G1 and G2 (NAND gates used as inverters). The output of G1 is connected to the input of G2
(A2) and the output of G2 is connected to the input of G1 (A1).

Let us assume the output of G1 to be Q = 1, which is also the input of G2 (A2 = 1). Therefore, the output of
G2 will be Q ̅ = 0 which makes A1 = 0 and consequently Q = 1 which confirms our assumption.
In a similar manner, it can be demonstrated that if Q = 0, then Q ̅ =1 and this is also consistent with the
circuit connections.
From the above discussion we note the following:
1. The output Q and Q ̅ are always complementary.
2. The circuit has two stable states: in one of the stable state Q = 1 which is referred to as the 1 state (or
set state) whereas in the other stable state Q = 0 which is referred to as the 0 state (or reset state).
3. If the circuit is in 1 state, it continues to remain in this state and similarly if it is in 0 state, it continuous
to remain in this state. This property of the circuit is referred to as memory i.e. it can be store 1 – bit of
digital information.
Since this information is locked or latched in this circuit, therefore, this circuit is also referred to as a
latch.
In the latch of figure above, there is no way of entering the desired digital information to be stored in
it. In fact, when the power is switched on, the circuit switches to one of the stable states (Q = 1 or 0)
and it is not possible to predict the state. If we replace the inverters G1 ad G2 with 2 – input NANG
gates, the input terminals of the NAND gates can be used to enter the desired digital information. The
modified circuit is shown in figure below. Two additional inverters G3 and G4 have been added for
reasons which will become clear from the following discussion.
If S = R = 0, the circuit is exactly the same as that of figure. If S = 1 and R = 0, the output of G3 will be 0
and the output of G4 will be 1. Since one of the inputs of G1 is 0, its output will certainly be 1.
Consequently, both the inputs of G2will be 1 giving an output Q ̅ = 0. Hence for this input condition, Q =
1 and Q ̅ = 0. Similarly, if S = 0 and R = 1 then the outputs will be Q = 0 and Q ̅ = 1. The first of these two
input conditions (S = 1, R = 0) makes Q = 1 which is referred to as the set state, whereas the second
input condition (S = 0, R = 1) makes Q = 0 which is referred to as the rest or clear state. This gives us the
means for entering the desired bit in the latch.

Now we see what happen if the input conditions are changed from S = 1, R = 0 to S = R = 0 or from S =
0, R = 1 to S = R = 0. The output remains unaltered. This shows the basic difference between a
combinational circuit and a sequential circuit, even through the sequential circuit is make up of
combination circuits.
The two input terminal are designated as set (S) and reset (R because S =1 brings the circuit in set state
and R =1 brings it to reset or clear state.
If S = R = 1, both the outputs Q and Q̅ will try to become 1 which is not allowed and therefore, this input
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condition is prohibited.
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 Clocked S – R Flip – Flop:
It is often required to set or reset the memory cell in synchronism with a train of pulse known as clock
(abbreviated as CK). Such a circuit shown is shown in figure below, and is referred to as clocked set – reset
(S – R) FLIP – FLOP.

Table:
Truth table of S – R Flip – Flop
Inputs Output
Sn Rn Qn + 1
0 0 Qn
1 0 1
0 1 0
1 1 ?

Preset and clear:

Table:
Summary of operations of S – R FLIP – FLOP
Inputs Output Operation
CK Cr Pr Q performed
1 1 1 Qn + 1 Normal Flip – Flop
0 0 1 0 Clear
0 1 0 1 Preset

J – K Flip – Flop:
The uncertainty in the state of an S – R FLIP – FLOP when Sn = Rn = 1 (fourth row of the truth table) can be
eliminated by converting it into a J – K Flip – Flop. The data inputs are J and K which are ANDed with Q ̅ and
Q, respectively, to obtain S and R inputs i.e.
̅
S = J. Q 1
R = K.Q 2
A J – K Flip – Flop thus obtained is shown in figure below. Its truth table is given in table below which is
reduced to table for convenience. Table has been prepared for all the possible combinations of J and K
inputs, and for each combination both the states of the output have been considered.
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 It is not necessary to use the AND gates of figure above, since the same function can be performed by
adding an extra input terminal to each NAND gate G3 and G4 of figure (Clocked SR flip flop). With the
modification incorporated in figure (SR flip flop with preset and clear), we obtain the J – K Flip – Flop using
NAND gates as shown in figure below. The logic symbol of J – K Flip – Flop is given in figure below.

Table (a):
Truth table for above figure
Data inputs Outputs Inputs to S – R FF Output
Jn Kn Q n Qn Sn Rn Qn + 1
0 0 0 1 0 0 0
0 0 1 0 0 0 1 = Qn
1 0 0 1 1 0 1
1 0 1 0 0 0 1 =1
0 1 0 1 0 0 0
0 1 1 0 0 1 0 =0
1 1 0 1 1 0 1
1 1 1 0 0 1 0 = ̅̅̅̅
Q𝑛

Table (b):
Truth table of J – K FLIP – FLOP
Inputs Output
Jn Kn Q n + 1
0 0 Qn
1 0 1
0 1 0
1 1 ̅̅̅̅
Q𝑛

The race – around condition:

The difficulty of both inputs 1 (S = R = 1) being not allowed in an S – R Flip Flop eliminated in a J – K Flip –
Flop by using the feedback connection from outputs to inputs of the gates G 3 and G4 above figure. Table (a)
above assumes that the inputs do not change during the clock pulse (CK = 1), which is not true because of
the feedback connections. Consider, for example that the inputs are J = k = 1 and Q = 0, and a pulse shown
in figure below is applied at the clock input. After a time interval t equals to the propagation delay
through two NAND gates in series, the output will change to Q = 1 (as in above table b). Now we have J = K
= 1 and Q = 1 and after another time interval of t the output will change back to Q = 0. Hence, we
conclude that for the duration tP of the clock pulse, the output will oscillate back and forth between 0 and
1. At the end the clock pulse, the value of Q is uncertain. This situation is referred to as the race around
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condition.
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 The race around condition can be avoided if tp < t < T. However, it may be difficult to satisfy this
inequality because of very small propagation delays in ICs. A more practical method for overcoming this
difficulty is the use of the master – slave (M – S) configuration shown below.

The Master – Slave J – K Flip – Flop:

D – Type Flip – Flop:

Table:
Truth table of a D – type Flip – Flop
Input Output
Dn Qn + 1
0 0
1 1

T – Type Flip – Flop:

Table:
Truth table of T – type Flip – Flop
Input Output
Tn Qn + 1
0 Qn
1 ̅̅̅̅
Qn
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 Conversion from one type of flip flop to another type:
Question:
Convert an S – R FLIP – FLOP to a J – K FLIP – FLOP
Answer:
The excitation tables of S – R and J – K FLIP FLOPs are given in table from which we make the truth table
given in table below.
Present state Next state S – R FF J – K FF T – FF D – FF
Sn Rn Jn Kn T n Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
The K – maps are given in figure below, which give
̅
S = J. Q
And,
R = K.Q
Thus, we see that the circuit resulting from the design is the same as that shown in figure.
Row FF data inputs Output S – R FF inputs
J K Q S R
1 0 0 0 0 X
2 0 1 0 0 X
3 1 0 0 1 0
4 1 1 0 1 0
5 0 1 1 0 1
6 1 1 1 0 1
7 0 0 1 X 0
8 1 0 1 X 0

Question:
A 1 MHz clock signal is applied to a J – K Flip Flop with J = K = 1, What is the frequency of the Flip – Flop O/P
signal? (ISRO)
a) 2MHz c) 250kHz
b) 50kHz d) 500 MHz
Ans. b
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 CHAPTER – 8
Counter:
Digital counters are often needed to count events. For example, counting the number of tablets filled in a
vial. Electrical pulses corresponding to the event are produced using a transducer and these pulses are
counted using a counter.
The counters are composed of flip flops. A 3 – counter consisting of three Flip – Flop is shown in figure. A
circuit with n Flip – Flops has 2n possible states. Therefore, the 3 – bit counter can count from decimal 0 to
7.
The Flip – Flops used are 74107J – K master – slave Flip – Flops, used as T – type. The pulses to be counted
are connected at the clock input of FFO. The Q0 output of FFO is connected to the clock input of FF1 and
similarly Q1 is connected to the clock input of FF2.
The FLIP – FLOPs are cleared by applying logic 0 at the clear input terminal momentarily. For normal
counting operation, it is to be maintained at logic 1. The pulses and the output waveforms are illustrated in
figure below.
The output Q0 of the least significant stage changes at the negative edge of each pulse (since T 0 = 1). The
output Q1 changes at the negative edge of each Q0 pulse (since Q0 act as CK for FF1 and T1 = 1) and the
output Q2 changes at the negative edge of each Q1 pulse (since Q1 acts as CK for FF2 and T2 = 1)
At any time, the decimal equivalent of the binary number Q2Q1Q0 is the number of pulses counted till that
time. For example, at X the count is 100 (decimal 4). The circuit resets after counting eight pulses.

Ripple or Asynchronous counters:

Table:
Counting sequence of a 3 – bit binary counter
Counter state Count
Q2 Q1 Q()
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
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 Up/Down Counter:
The counter of counts in the UP direction, i.e. the decimal equivalent of the counter output increase with
successive clock pulses. It is also possible to make a counter in which the decimal equivalent of the counter
output decreases with the application of successive clock pulse, i.e. the counting proceeds in the DOWN
direction. The former is referred to as an UP counter and the latter as a DOWN counter.
An UP/DOWN counter can also be designed which can count in any direction depending upon the direction
control input.

Modulus of the Counter:

The counter discussed above is referred to as a ripple counter, since the pulses applied ripple from stage to
stage. It is a modulo n counter where n = 2N
If it is desired t have a modulo m counter, the number of FLIP – FLOP required is determined using given
equation as the minimum value of N which satisfies the equation.
m  2N
For example the value of N is 4 for any of m from 9 to 16. If m = 16, then the circuit can be designed as
discussed above but if it is less than 16, say 10, then out of 16 states are used and the remaining six states
are unused. The counter is required to be reset (i.e. the normal counting is to be terminated) at the end of
the tenth clock pulse. This can be achieved by generating a logic 0 signal immediately after the tenth pulse
and applying it to be the clear input of all the FLIP – FLOPs.
For a modulo 10 counter (also referred to as a decade counter) the circuit for resetting the counter after
the tenth pulse is shown in figure below.

At the end of the tenth pulse, Q3 = Q1 = 1, therefore, the output of the NAND gate G will be 0, making the
output of the latch 0. This will reset the counter. The latch is used in order to keep the clear line at 0 till
both the FLIP – FLOPs are cleared.
A counter in which the starting state is not 0 can be designed by making use of the preset inputs of the FLIP
– FLOPs. This is referred to as loading the counter asynchronously (not synchronous with the clock pulse).
This is referred to as a presettable counter.

Synchronous counters:
Question:
Design a 3 – bit synchronous counter using J – K FLIP FLOPs.
72

Answer:
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 The number of FLIP – FLOPs required is 3. Let the FLIP – FLOPs be FF0, FF1 and FF2 and their inputs and
outputs are given below:
FLIP – FLOP Inputs Output
FF0 J 0, K 0 Q0
FF1 J 1, K 1 Q1
FF2 J 2, K 2 Q2

Counter state Flip flop inputs

Q2 Q1 Q0 FFO FF1 FF2
J0 K0 J1 K1 J2 K2
0 0 0 1 X 0 X 0 X
0 0 1 X 1 1 X 0 X
0 1 0 1 X X 0 0 X
0 1 1 X 1 X 1 1 X
1 0 0 1 X 0 X X 0
1 0 1 X 1 1 X X 0
1 1 0 1 X X 0 X 0
1 1 1 X 1 X 1 X 1
0 0 0

Transition table:
0  0 0 to 1 1  0 1  1
J0 0 1 X X
K0 X X 1 0
The count sequence and the required inputs of FLIP – FLOPs are given in table. The inputs to the FLIP –
FLOPs are determined in the following manner.

Consider one column of the counter state at a time and start from the first row, for example, consider Q 0.
Before the first pulse is applied, Q0 = 0 and it is required to be 1 at the end of the first clock pulse.
Therefore, to achieve this condition, the values of J0 and K0 are 1 and X respectively (from the excitation
table). These are entered in the table in the row corresponding to 0 pulse. When the second clock pulse is
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applied Q0 is to change from 1 to 0, therefore the required inputs are

J0 = X, K0 = 1
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In a similar manner inputs of each FLIP – FLOP are determined.

 Now, we prepare the K – maps as shown in above figure and the resulting minimized expressions are:
J0 = 1, K0 = 1
J1 = Q0, K1 = Q0
J2 = Q0Q1, K2 = Q0Q1

Question:
The SR waveforms shown in figure (b) are applied to SR latch shown in figure (a). Write mode of operation
for each duration and draw the output waveform.
Answer:
i) For time period a S = 1, R = 0, hence mode of operation is set hence Q = 1.
ii) For time period b S = 0, R = 0, Mode of operation is hold. Hence Q = 1
iii) For time duration C S = 0, R = 1. Mode of operation is reset hence output Q = 0
iv) S = 0, R = 0. Mode of operation = hold, therefore Q = 0 for time duration d

Similarly, modes of operation for time periods e, f, g are set, reset and prohibit respectively.

Question:
The S̅ and R
̅ waveforms in figure (a) are applied to the inputs of NAND SR latch as shown in figure (b).
Write mode of operations at different intervals of time.
Answer:
The modes of operations along with the output at different intervals of time are shown in figure.

Question:
The S, R, EN waveforms shown in figure (a) are applied to the inputs of the gated SR latch shown in figure
(b). Write the mode of operation for each time period and draw the output waveform.
Answer:
A high applied on the latch input EN causes enables the circuit and allows it to respond to S, R, inputs.
74

A low on En input disables the circuit which causes the latch to frozen. For the solution see lower part of
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figure.
 Question:
The D and EN waveforms in figure (b) are applied to the inputs of the data latch or shown in figure (a)
Answer:
The EN data are transferred from the D input to the Q output when the enables pulse is in the high state.

Question:
Determine the output frequency for a frequency division circuit that contains 12 flip – flops with an input
clock frequency ,of 20.48MHz. (DMRC 2016)
a) 10.24kHz c) 30.24kHz
b) 5kHz d) 15kHz
Ans. b

Question:
Which shift register counter requires the most decoding circuitry? (ISRO)
a) Johnson counter c) Ripple counter
b) Ring counter d) MOD counter
Ans. d

Question:
The ripple counters suffers from (JE Signal Telecom)
a) Propagation delays c) Both the above
b) Voltage spikes d) None of the above
Ans. c
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 CHAPTER – 9
A/D and D/A converters:
Digital to Analog Converters:
The analog output voltage V0 of an bit straight binary D/A converter is related to the digital input by the
equation
V0 = K(2nN– 1 bN – 1 + 2N – 2 bN – 2 + . . . . . . . . + 22b2 + 2b1 + b0) 1
Where K is a proportionality factor
bn = 1, if the nth bit of the digital input is 1
= 0, if the nth bit of the digital input is 0

Question:
Find the analog output voltage of a 4 – bit D/A converter for all possible inputs. Assume K = 1
Answer:
From above equation we obtain the output voltage of 4 – bit D/A converter for all are given in table.
There are two types of commonly used D/A converters. These are
1. Weighted resistor D/A converter, and
2. R – 2R ladder D/A converter
Weighted – Resistor D/A converter:
Let us assume an N – bit straight binary input to a resistor network (through digitally controlled electronic
switches) which produces a current I corresponding to logic 1 at the most significant bit, I/2 corresponding
to logic 1 at the least significant bit position. The total current thus produced will be proportional to the
digital input. This input can be converter into a corresponding voltage, by using an OP AMP, which will be
proportional to the digital input.
Digital input Analog circuit
b3 b2 b1 b0 V
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
The circuit of figure below can be used for converting the digital input to analog output which operates
according to the above principle. This circuit is referred to as a weighted resistor D/A converter since the
resistance values are weighted in accordance with the binary weights.
In the circuit figure, the digital inputs (1 or 0) operate the switches. A switch is thrown to position 1 or 0 for
a digital input corresponding to that bit being 1 or 0, respectively. The voltage applied to a resistor is V(1) if
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the switch connected to it is in position 1 and V(0) if it is position 0. The current I i is given by
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 Ii = IN – 1 + IN – 2 + IN – 3 + . . . . . . . . . + I2 + I1+ I0
Where,
IN – 1 = VN – 1 /R
IN – 2 = VN – 2 /2 R Where Vn = V(1) if bn = 1
IN – 3 = VN – 3 /2 R2 = V(0) if bn = 0
I0 = V0/2N – 1 R
For straight binary input, V(0) = 0 and V(1) =  VR, and the output voltage V0 is given by
RF RF RF RF
V0 =  ( VR) ( bN−1 + bN−2 + bN−3 + . . . . . . . . + b0 )
R 2R 22 R 2N−1 R
RF
Which is of the same form as equation 1 with K = N−1
VR
2 R
The output swings in only one direction and therefore is unipolar. If it is required to convert digital data in
bipolar format such as in sign magnitude. 1’s complement or 2’s complement format, then V(0)  0. In such
cases, V(0) is used to offset the output swing.
With V(1) and V(0) as the voltages applied to the resistor network for 1 and 0, respectively, the output
voltage V0 of figure above is given by
RF
V0 = − N−1
(2N−1 VN−1 + 2N−2 VN−2 + . . . . . . . . . + 21 V1 + 20 V0 )
2 R
An offset can also be produced in the output voltage V 0 by using the circuit. The offset voltage produced in
this circuit is
RF
− . Voff
Roff

R – 2R Ladder D/A Converter:

An R – 2R ladder D/A converter is shown in figure. It uses resistor of only two values, R and 2R. The inputs
to the resistor network are applied through digitally controlled switches. A switch is in position 0 or 1
corresponding to the digital input for that bit position being 0 or 1, respectively. To analyse this circuit, for
simplicity we consider a 3 – bit R – 2R ladder D/A network shown in figure below. In this circuit, we have
assumed the digital input as 001.
The circuit is simplified using thevenin’s theorem. Applying thevenin’s theorem at XX’ we obtain the circuit.
Similarly, applying thevenin’s theorem at YY’ and ZZ’, we obtain the circuits of figure respectively. Here, LSB
has been assumed as 1 and the equivalent voltage obtained is VR/23.
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 Similarly, for the digital input of 010 and 100, the equivalent voltage are VR/22 and VR/21, respectively. The
value of the equivalent resistance is 3R in each case. Therefore, we obtain an equivalent circuit of figure
which is given in the figure. For the circuit of figure, the output analog voltage V 0 is given by
RF VR RF VR RF VR
V0 =  ( . b0 + . b1 + . b2 )
3R 23 3R 23 3R 21
RF V
=(
3R
) . ( 2R3 ) [4b2 + 2b1 + 1b0 ]
Equation shown that the analog output voltage is proportional to the digital input. In general, for an N – bit
D/A converter, the output voltage can be similarly determined and is given by
V0 = (2N – 1 bN – 1 + 2N – 2bN – 2 + ……….. + 22b2 + 21b1 + 20b0)
Where,
RF = 3 R and VR =  2NV.
The number of resistors required for an N – bit D/A converter is 2N in the case of R – 2R ladder D/A
converter, whereas it is only N in the case of a weighted – resistor D/A converter. But, because of the wide
spread in the resistance values for large N, the weighted – resistor D/A converter is not suitable. However,
the weighted – resistor network of figure can be modified to accommodate a large number of bits without
consequent spread in resistor values. One such circuit is shown in figure. Here, the bits are divided into
groups of four. The most significant four bits are applied in a manner similar to the one used in weighted –
resistor r, in addition to weighted resistors. This is done to produce input currents of OP AMP due to least
significant group of 4 – bits and the most significant group of 4 – bit in the ratio of 1:16
b b2 b0
(b3 = b6
=
b4
= 1/16)
7

The resistor r is determined in the following ways:

Let the b3 bit be 1 and b2, b1 and b0 bits be all 0. The portion of the circuit corresponding to this is shown in
figure (a) and its simplified version is shown in figure (b).

From figure (b), we obtain Iin assuming virtual short at the input of the OP AMP.
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 8
VR ( R)
7
Iin = r(8/7R) X 8
R+ (r+8/7R) (r+ R)
7
This current must be 1/16th of the current due to b7, which is VR/R. Therefore,
8
VR ( R) VR
7
8 8 =
R(r+ R)+ r( R) 16R
7 7
Or
r = 8R
With this value of r, it can be verified that the currents due to b2, b1 and b0 will be 1/16th of the currents
due to b6, b5 and b4 respectively.
The output analog voltage V0 of the modified D/A converter of figure for r = 8R is given by
V V V V V V V V
V0 = − ( RR R F b7 + 2RR R F b6 + 4RR R F b5 + 8RR R F b4 + 16R
R R
R F b3 + 32R R
R F b2 + 64R R
R F b1 + 128R R F b0 )
V R
= − ( 2R7 RF ).(27b7 + 26b6 + ………… + 21b1 + b0)
We observe from above equation that the analog output voltage is proportional to the digital input. The
number of resistors in this circuit is less and also the spread in the resistor values is reduced. This
configuration can be used for any number of bits.

Specification for D/A converters:

The characteristic of a D/A converter, which are generally specified by the manufacturers are:
1. Resolution
2. Linearity
3. Accuracy
4. Settling time
5. Temperature sensitivity

Analog to Digital Converters:

In a digital to analog converter, the possible number of digital inputs is fixed. For example, in a 3 – bit D/A
converter, there are 8 possible inputs. In contrast, in an analog to digital converter, the input analog
voltage can have any value in a range. But the digital output can have only 2N discrete values for an N- bit
A/D converter. Therefore, the whole range of analog voltage is required to be represented suitably in 2 N
intervals, and each interval then corresponds to a digital output.
Consider an analog voltage in the range of 0 to V and a 3 – bit digital output for any voltage in this range.
Let us divide the whole range of analog voltage in 8 intervals (3 – bit output) of the size S = V/8. Each
interval is assigned a unique digital value. This process is referred to as quantization. The intervals of the
analog voltage and their corresponding digital values are shown in figure. From this, we observe that the
whole range of voltage in an interval is represented by only one digital value. Therefore there is an error
referred to as quantization error, involved in this process of quantization.
In this case, the maximum quantization error for any analog input voltage V x in the given range is V/8.
The quantization error can be reduced if we choose the middle six intervals of size intervals of size S = V/7
and the top and the bottom intervals of size S/2 = V/14. The intervals, along with their assigned digital
values and equivalent analog output voltage if these digital signals are applied to a D/A converter, are
shown in figure. This shows that the maximum quantization error will be S/2 = V/14 for any analog input
voltage Va in the range 0 to V. The quantization error can also be specified in terms of LSB. For example in
1
the above case, the maximum quantization error is  2 LSB.
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 Question:
An analog voltage in the range of  V to +V is required to be converted into a 3 – bit 2’s complement digital
1
format. The digital value for 0V should be 000 and the maximum quantization error should not exceed  2
LSB.
Answer:
The digital value 000 should be assigned to the analog voltage interval 0V  S/2, as shown in figure. Since in
2’s complement representation, there is one more negative number than the number of positive numbers,
the analog voltage from V to +V should be divided in seven intervals, each of size S = 2V/7, and one digital
value is to be assigned to each interval. The extra digital output 100 can be used to represent the interval
V to 9V/7.

Some of the commonly used A/D converters are discussed below:

Parallel – Comparator A/D converter:

A 3 – bit parallel comparator A/D converter is shown in figure. Va is the analog voltage to be converted into
digital form. The voltage corresponding to full scale is V from which the reference voltages V R1, VR2, ………
are generated using the resistor network. The voltage Va is compared simultaneously with the reference
voltages by using comparators. A 7 – bit output is obtained from the comparator which is stored in latches.
This 7 – bit output is obtained from the comparators which is stored in latches. This 7 – bit digital signal is
converted to a 3 – bit output by using a decoder circuit. The comparator output and the 3 – bit output by
using a decoder circuit. The comparator outputs and the 3 – bit digital output for each interval of the
analog voltages.
The principal of parallel comparator A/D conversion is the simplest in concept and fastest. Its main
disadvantages are rapid increase in the number of comparators with the number of bits [(2 N – 1)
comparators are required for an N – bit converter] and the corresponding complications of the decoder
circuit.
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 Table:
Comparator output s and digital output of parallel comparator A/D converter
Analog circuit Comparator outputs Digital output
Va C7 C6 C5 C4 C3 C2 C1 B2 B1 B0
0  VA < VR1 0 0 0 0 0 0 0 0 0 0
VR1 < Va < VR2 0 0 0 0 0 0 1 0 0 1
VR2 < Va < VR3 0 0 0 0 0 1 1 0 1 0
VR3 < Va < VR4 0 0 0 0 1 1 1 0 1 1
VR4 < Va < VR5 0 0 0 1 1 1 1 1 0 0
VR5 < Va < VR6 0 0 1 1 1 1 1 1 0 1
VR6 < Va < VR7 0 1 1 1 1 1 1 1 1 0
VR7 < Va  V 1 1 1 1 1 1 1 1 1 1
Successive – Approximation A/D converter:
The principal of the successive approximation A/D conversion can be explained by the following example.
Consider an object of unknown weight in the range 0 to 1Kg. Suppose that a balance and a set of known
weights of ½, ¼ and 1/8 Kg are available. These known weights are to be used in a succession of trials to
determine the unknown weight.
We begin the process by placing the unknown weight Wa on one side of the balance and the ½ Kg known
weight on the other side and take a decision in the following way:
1. If Wa  1/2Kg, retain the 1/2Kg weight on the scale and add 1/4Kg weight to its side. Also write a 1 as
the most significant bit.
2. If Wa < ½ Kg, remove the ½ KG weight and place ¼ Kg weight in the scale. Corresponding to this, write a
0 as the most significant bit.
We continue to try weights, successively smaller by a factor of 2. If a weight is finally retained, it is
represented by a 1 and if removed then, by a 0. The complete process is illustrated in figure below.
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 The numerical significance to various binary digits are: ½ Kg to the most – significant bit, ¼ bit to the
1 1 1
next bit etc. For example, the binary number 101 represents a weight of (1 X 2 + 0 X 4 + 1 X 8) Kg =
5/8 Kg.
Let us consider an unknown weight slightly less than ½ Kg. From figure above, we find that the
3
successive approximation method gives a binary output of 011 for this, which represents a weight of 8
1
Kg. This shows a quantization error of 8 Kg. For reducing the quantization error, it is necessary to offset
the scale, i.e. to tilt the scale in favour of the unknown weight. The magnitude of the offset must be
1
equal to one – half of the smallest weight i.e. 16 Kg in this case. With this offset, the interval
corresponding to each binary output is shown in figure.

An A/D converter using the principal discussed above can be realized, as shown in figure. Here, the
comparator serves the function of the scale, the output of which is used for setting/resetting the bits at
the output of the programmer. This output is converted into equivalent analog voltage from which the
offset voltage is subtracted and then applied to the inverting input terminal of the comparator. It
should be noted that the offset weight was added on the side of the unknown weight and therefore, it
is to be subtracted from the known weight side for getting the equivalent effect. The outputs of the
programmer will change only when the clock equivalent effect. The outputs of the programmer sets
the MSB to 1 and all other bits to zero 0. This is converted into analog signal by the D/A converter and
the comparator compares it with the analog input voltage. If the analog input voltage V a  Vi, the
output voltage V0 of the comparator is HIGH which sets the next bits the next bit. Thus, a 1 is tried in
each bit of the D/A converter until the binary equivalent of the analog input voltage is obtained. For an
N – bit converter, the number of clocks pulses required would be N and hence it is slower than the
parallel comparator A/D converter.

Dual – Slope A/D converter:

The block diagram of a dual slope A/D converter is shown in figure below. It has four major blocks:
1. An integrator
2. A comparator
3. A binary counter
4. A switch driver
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 The conversion process beings at t = 0 with switch S1 in position 0 thereby connecting the analog voltage Va
to the input of the integrator. The integrator output
t V
v0 =  1/ ∫0 Va dt = − ( a ) t
This results in HIGH VC, thus enabling the AND gate and the clock pulses reach the clock (CK) input terminal
of the counter which was initially clear. The counter counts from 00…….00 to 111…….11 when 2 N – 1 clock
pulses are applied. At the next clock pulse 2N, the counter is cleared and Q becomes 1. This controls the
state of S1 which now moves to position 1 at T1, thereby connecting  VR to the input of the integrator. The
output of the integrator now starts to move in the positive direction. The counter continues to count until
v0 < 0. As soon as v0 goes positive at T2, Vc goes LOW disabling the AND gate. The counter will stop counting
in the absence of the clock pulses. The waveforms of voltages v0 and VC are shown in figure.

The time T1 given by:

T1 = 2NTC
Where TC is the time period of the clock pulses. When the switch S1 is in position 1, the output voltage of
the integrator is given by
V V
v0 =  a T1 + R (t − T1 )
 
v0 = 0 at t = T2
Therefore,
V Va
T2 – T1 = V a T1 = 2N TC
R VR
Let the count recorded in the counter be n at T2, therefore
V
T2 – T1 = n.TC = V a 2N TC
R
Which gives
V
n = V a 2N
R
This shows that the output of the counter is proportional to the analog voltage va. The output recorded in
the counter is numerically equal to analog voltage Va if VR = 2N
This type of A/D converter is often used in digital voltmeters because of its good conversion accuracy and
low cost. The disadvantage of the dual – slope A/D converter is its slow speed.
A/D converter using Voltage to Frequency Conversion:
An analog voltage can be converted into digital form, by producing pulses whose frequency is proportional
to the analog voltages. These pulses are counted by a counter for a fixed duration and the reading of the
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counter will be proportional to the frequency of the pulses and hence to the analog voltage.
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 A voltage to frequency converter is shown in figure. The analog voltage V a is applied to an integrator whose
output is applied at the inverting input terminal of a comparator. The non – inverting of the comparator is
connected to a reference voltage  VR. Initially the switch S is open and the voltage v0 decreases linearly
with time (v0 = Vat/), which is shown in figure. When the decreasing v0 reaches  Va at t = T, the
comparator output VC goes HIGH. This is used to switch S through a monostable multivibrator. When the
switch S is closed, the capacitor C discharges, thereby returning the integrator output v0 to 0. Since the
pulse width of the waveform VC is very small, a monostable multivibrator is used to keep the switch S
closed for a sufficient time to discharge the capacitor completely. The rate at which the capacitor discharge
upon the resistance of the switch.

Let the pulse width of the monostable mutivibrator be Td. Therefore, the switch S remains closed for Td
after which its opens and v0 starts decreasing again.
If the integration time T >> Td the frequency of the waveforms v0 and vc is given by
1 1 1 Va
f= = =
T+ Td T  VR
Thus, we obtain an output waveform whose frequency is proportional to the analog input voltage.
An A/D converter using the voltage to frequency (V/F) converter is shown in figure. The output of the V/F
converter is applied at the clock (CK) input of a counter through an AND gate. The AND gate is enabled for
a fixed time interval T1. The reading of the counter t t = T1 is given by
1 Va
n = fT1 = T1
 VR
Which is proportional to Va,

A/D Converter Using Voltage – to – Time Conversion:

In an A/D converter using V/F converter, the cycles of a variable frequency source are counted for a fixed
period. Alternatively, it is possible to make an A/D converter by counting the cycles of a fixed frequency
source for a variable period. For this, the analog voltage is required to be converted to a proportional time
period.
An A/D converter, which operates on this principle, is shown in figure.
A negative reference voltage  VR is applied to an integrator, whose output is connected to the inverting
input terminal of the comparator. The analog voltage V is applied at the non – inverting input terminal of
the comparator. The output of the comparator VC is at logica level 1 as long as the output of the integrator
v0 is less than Va. When v0 crosses Va at t = T, VC goes LOW. Then AND gate is enabled when VEN is LOW and
switch S remains open. When VEN goes HIGH, the switch S is closed, thereby discharging the capacitor. Also
the AND gate is disabled. The various waveforms are shown in figure. When the AND Gate is enabled the
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clock pulses will reach the clock (CK) input terminal of the counter. The output of the counter is the digital
output corresponding to Va.
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 The time T is given by

T= Va
VR
Which shows that T is proportional to Va.
The counter reading is n at t = T, then
fc 
n = fc.T = Va
VR
where fc is the clock frequency. The count n is proportional to Va.

Specification of A/D converter:

The following specification are usually specified by the manufactured of A/D converters.
1. Range of input voltage
2. Input impedance
3. Accuracy
4. Conversion time, and
5. Format of digital output

Question:
A 5 bit DAC has a current output for a digital input of 10100, an output current of 10mA is produced. What
will Iout be for a digital input of 11101?
Answer:
The digital input 101002 is equal to decimal 20. Since Iout = 10mA for this case, the proportionality factor is
0.5mA. Thus, IOut digital input 111012 = 29 is
Iout = 29 X (0.5) = 14.5mA

Question:
What is the largest value of the output voltage from 8 bit DAC that produces 1.0V for a digital input of
00110010?
Answer:
001100102 = 5010
1.0V = K X 50
Therefore, K = 20mV
The largest output will occur. For an input of 111111112 = 25510
Vout (max) = 20mV X 255 = 5.10V

Question:
A 10 bit DAC has a step size 10mV. Find full scale output voltage and the percentage resolution.
Answer:
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With 10 bit, there will be 210 – 1 = 1023 steps of 10mV each. The full scale output voltage will therefore be
10mV X 1023 = 10.23V
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 step size
% resolution = X 100%
full scale output
10mV
Hence, % resolution = X 100% = 0.1%
10.23V

Question:
For an 8 bit counter A/D converter driven by a 1000kHz clock. Find
i) The maximum conversion time
ii) The average conversion time
iii) The maximum conversion rate
Answer:
i) An 8 bit converter has a maximum of 28 = 256. With a 1000kHz clock, the counter advances at the rate
of 1 count each 1sec. To advance 256 count requires 256 X 1 X 10 – 6 = 0.256 m sec.
1
ii) The average conversion time is equal to half of maximum conversion time. thus, it is 2 X 0.256 = 0.128
m sec.
iii) The maximum conversion rate is determined by the longest conversion time since the converter has a
1
maximum conversion time of 0.256 msec, it is capable of making = 3906 conversion per
0.256 X 10−3
second.

Question:
What will happen to the operation of a digital ramp ADC if V in greater than full scale value Vout.
Answer:
It is clear that the output will never go LOW since the stair case voltage can never exceed V in. Thus pulse
will be continuously applied to the counter, so that the counter will repetitively count up from zero to
maximum, recycle back to zero, count up and so on. This will produce repetitive stair case waveforms at
Vout going from zero to full scale, and this will continue until Vin is decreased below dull scale.

Question:
An 8 it SAC has a resolution of 20mV. What will its digital output be for an analog input of 2.17V?
Answer:
2.17
mV = 108.5
20
So that step 108 would produce Vout = 2.16V and step 109 would produce 2.18V, the SAC always produces
a final Vout that is at the step below Vin. Therefore, for the case, Vin = 2.17V, the digital result would be
10810 = 01101102
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 CHAPTER – 10
Semiconductor Memories:
Memory Organization and Operation:
The basic element of a semiconductor memory is a FLIP – FLOP which has been discussed. The information
is stored in binary form. There are a number of locations in a memory chip, each location being meant for
one word of digital information. The number of locations and the number of bits comprising the word vary
from memory to memory. The size of a memory chip is specified by two numbers M and N as M X N bits.
The number M specifies the number of locations available in the memory and N is the number of bits at
each location available in the memory and N is the number of bits at each location. In other words, this
means that M words of N bits each can be stored in the memory. The commonly used values of the
number of words per chip are 64, 26, 512, 1024, 2048, 4096 etc whereas the common values for the word
size are 1, 4 and 8 etc. Memories requiring higher number of words and/on larger word sizes can be
formed by using these chips.
The block diagram of a memory device is shown in figure. Each of the M locations of the memory is defined
by the unique address and therefore, for accessing any one of the M locations, P inputs are required,
where 2P = M. This set of lines is referred to as address inputs or address bus. The address is specified in
the binary form. For convenience, octal and hexadecimal representation are commonly employed.

In fact, the address input is applied to P to M decoder circuit which activates one of its M outputs
depending on the address and thus the desired memory location is selected.

Question:
Consider a memory of size 16 words. Find the binary address of each location.
Answer:
Since M = 16, therefore, 2P = M gives P = 4, i.e for selecting one out of 16 words, a 4 – bit address is
required. The address is specified as A3 A2 A1 A0, where A3 represents the most significant bit (MSB) and A0
represents the least significant bit (LSB) of the address. The address of each location is given.
The number of inputs required to store the data into or read the data from each memory locations is N.
One set of N lines is required for storing the data into the memory referred to as data inputs and another
set of N lines is required for reading the data already stored in the memory, which is referred to as data
outputs. In some memory chips, the same set of the lines is used for data input as well as data output and
is referred to as data bus. This means that the data is time multiplexed. It is used as input for some specific
time and as output for some time. This offers saving in the number of pins on the IC chips.
A number of control inputs are required to give command to the device to perform the desired operation.
For example, a command signal is required to tell the memory whether a write or a read operation is
desired. Other command inputs chip enable (CE), chip select (CS) etc.

Table:
Memory addresses for above question
Word Binary address
Number A3 A2 A1 A0
87

0 0 0 0 0
1 0 0 0 1
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2 0 0 1 0
 3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
0 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

In addition to the above mentioned functional pins, a minimum of two pins are required for power supply
and ground. The internal organization of a 16 X 4 memory chip is illustrated in figure. The write and red
operations are discussed.

Expanding Memory size:

In many memory applications the required capacity i.e. the number of words and/or word size, cannot be
satisfied by a single available memory IC chip. Therefore, several similar chips have to be obtained suitably
to provide the desired number of words and/or word size.
Expanding word size:
If it is required to have a memory of work size n and the word size of the available memory ICs is N (n > N),
then a number of similar ICs can be combined together to achieve the desired word size. The number of IC
chips required is an integer, next higher to the value n/N. These chips are to be connected in the following
way.
1. Connect the corresponding address liens of each chip individually, i.e. A0 of each chip is connected
together and it becomes A0 of the overall memory. Similarly, connect other address lines together.
2. Connect the RD input of each IC together and it becomes the read input for the overall memory.
Similarly, connect the WR and CS input.
Now the number of data – input/output lines will be equal to the product of the number of chips used
and the word size of each chip. The following example illustrate the above procedure clearly.
Question:
Obtain a 16 X 8 memory using 16 X 4 memory ICs.
Answer:
Since the word size required is n = 8 and the word size of the available IC is N = 4, therefore, n/N = 2 chips
are required to obtain the desired memory.
Since each chip can store 16 4 – bit words and we want to store 16 8 – bit words, each chip is required to
88

store half of each word. Figure shows the relevant connections of two chips. Here, we have assumed
bidirectional input/output (I/O) lines which is common in many available memory chips. In this 16 X 8
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 memory, the higher order four bits (D7, D6, D5, D4) of each 8 – bit word are located in memory M1 and
lower order four bits (D3, D2, D1, D0) are located in memory M0.

Expanding word capacity:

Memory chips can be combined together to produce a memory, with the desired number of locations. To
obtain a memory of capacity m words, using the memory chips with M words each, the number of chips
required is an integer next higher to the value m/M. These chips are to be connected in the following ways.

1. Connect the corresponding address lines of each chip individually.

2. Connect the RD input of each chip together. Similarly, connect the WR inputs.
3. Use a decoder of proper size and connect each of its output to one of the CS terminals of memory
chips. For example, if eight chips are to be connected a 3 – line to 8 – line decoder is required to select
one out of eight chips at any one time.
The following example clearly illustrate the above procedure.

Question:
Obtain a 2048 X 8 memory using 256 X 8 memory chips.
Answer:
2048
The number of chips required is 256 = 8. At any one time, only one of the 2048 locations is to be accessed,
which will be in one of the eight chips. That means only one of the eight chips must get selected at a time.
For selecting one out of 2048 locations, the number of address lines required is 11 (211 = 2048). The lower
order eight bits of the address A7 – A0 will be same for each chip, and the higher order three bits of the
address A10 – A8 must select one out of eight chips. For this purpose, a 3 – line to 8 – line decoder is
required. The memory connections are shown in figure. Here, we have assumed a common terminal (R/W ̅)
̅ , whereas logic 0 is to be applied
for read and write. For the read operation, logic 1 is to be applied to R/W
for the write operation. The chip select input is assumed to be active low. The addresses of the chips are
given
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 Table:
Addresses of the memory chips
Memory chip Address (hex.)
M0 000 – 0FF
M1 100 – 1FF
M2 200 – 2FF
M3 300 – 3FF
M4 400 – 4FF
M5 500 – 5FF
M6 600 – 6FF
M7 700 – 7FF
Classification and characteristics of memories:
Various memory devices can be classified on the basis of their principle of operation, physical
characteristics, mode of access, technology used for fabrication etc.
Principle of operation:
Memories can be classified according to their principle of operation. The most commonly used memories
are:
1. Sequential accessed memory 3. Read only memory (ROM)
2. Read and write memory (RAM) 4. Content addressable memory (CAM)
In the sequential accessed memories, the memory locations are accessed, for writing into or reading from,
in a sequential fashion. Therefore, the time required for accessing a memory location (referred to as access
time) for writing into or reading from is different for different location.
There are two types of sequentially accessed memories. These are:
1. Shift registers 2. Charge coupled devices (CCD)
Shift registers can be either static or dynamic. In a static memory, the contents of the memory location do
not change with time as long as power is on. On the other hand, in dynamic memories the information is
stored in MOS capacitors which changes with time and, therefore it ahs to be refreshed at regular
intervals. The dynamic memories are simpler, less expensive require less power, have high packing density
in comparison to static memories, and are therefore widely used in digital systems. However, the cost of
additional circuitry required for refreshing may increase the system cost.
The charge coupled devices are implemented using MOS technology. These devices have high density and
low cost.
The sequentially accessed memories using shift registers and CCD memories.
The other mode of access of a memory location is called as random access in which the access time is same
for each memory location is called as random access in which the access time is same for each memory
location. The read and write memory is a random access memory and is referred to as RAM. RAMs can be
static or dynamic. The detailed operation of RAM.
Read only memory (ROM), as the name suggests, is meant only for reading the information from it. This
does not mean that information is not written into it, because unless some information is stored into it,
there cannot be anything to read from. Actually the process of entering information into this type of
memory is much more complicated than for RAM and is done outside the system where it is used.
Therefore, it is called as read only memory. It is used to store information which is fixed such as tables for
various functions, fixed data and instruction. The ROM is a random access memory.
The various types of read only memories are further sub classified on the basis of the technique employed
for storing information into the memory (referred to as programming) or their erasability properties.
A read only memory is either programmed at the time of manufacturing according to the information
specified by the user (referred to as custom programmed or mask programmed), which cannot be changed
after packaging. Those programmed by the user are referred to as programmable ROM (PPROM). A PROM
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can be programmed only once after is contents are permanently fixed as ROM.
Another category of PROM is reprogrammable, i.e. it can be programmed again and again. This is referred
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to as erasable and programmable ROM.

 Depending upon the technique used for erasing, they are referred to as EPROM, (if ultraviolet radiation is
used for erasing) or EAROM (if the contents are alterable electrically). The detailed operation of various
types of ROMs.
Content addressable memory (CAM) is a special purpose random access memory which performs
association operation in addition ot read/write operations.
Physical Properties:
Memories can be classified according to their physical characteristic, such as
1. Erasable or non – erasable
2. Volatile and non – volatile
Erasable or Non – Erasable Memories:
A memory in which the information stored can be erased and new information stored is called erasable
memory. On the other hand, the information stored in the non – erasable memory cannot be erased, for
example ROM is non – erasable. The erasable memories can further be sub – classified as:
1. Location by location erasable, in which the desired memory locations can be erased one by one and
new information can be entered. For example, in electrically – alterable read only memory (EAROM),
the contents of a location have to be erased first before a new information can be entered. On the
other hand, for read and write memory (RAM) and content addressable memory (CAM), the erasing
operation is automatically performed whenever new information is entered in a memory location.
2. All memory locations are simultaneously erasable, in which the contents of all the locations of the
memory chip get erased simultaneously by exposing the memory chip to ultraviolet (UV) radiation.
Such a memory is referred to as erasable – programmable read only memory (EPROM).
Volatile or Non – Volatile Memories:
If the information stored in a memory is lest when electrical power is switched off, the memory is referred
to as volatile memory. For example, the RAM is a volatile memory. On the other hand, in a volatile
memory, the information once stored remains intact until changed deliberately. All types of ROMs are non
– volatile memories.
Fabrication Technology:
Memories can be classified on the basis of the fabrication technology used. The two broad categories of
memories based on fabrication technology used are:
1. Bipolar
2. Unipolar (MOS)
Static RAM, ROM and PROM can be fabricated using either bipolar technology (TTL, ECL etc) or MOS
technology, whereas dynamic RAM, EPROM and EAROM can be fabricated only using unipolar devices
(MOSFETs)
Read only Memory:
A read only memory (ROM) is a semiconductor memory device used to store information which is
permanent in nature. It has become an important part of many digital systems because of its low cost, high
speed, system design flexibility and data non – volatility. The read only memory has a variety of
applications in digital systems. Such as implementation of combinational logic and sequential logic,
character generation, look up tale, microprocessor programme storage etc.
ROMs are well suited for LSI manufacturing processes and are available in many forms. Two major
semiconductor technologies are used for manufacturing of ROM integrated circuits, viz. bipolar
technology, MOS technology, which differ primarily in access time. In general, bipolar devices are faster
and have higher drive capability, whereas MOS devices require less silicon area and consume less power.
With improvement in MOS technology, it is now possible to make MOS memories with speeds comparable
to those bipolar memories.
The process of entering information into a ROM is referred to as programming the ROM. Depending on the
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programming process employed, the ROMs are categorized as:

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 1. Mask programmable read only memories, which are referred to as ROMs. In these memories, the data
pattern must be programmed as part of the fabrication process. Once programmed, the data pattern
can never b changed. These are highly suited for very high volume usage due to their low cost.
2. Programmable read only memories, which are referred to as PROMs. A PROM is electrically
programmable. i.e the data pattern is defined after final packaging rather than when the device is
fabricated. The programming is done with an equipment referred to as PROM programmer. The
programming techniques used.
3. Erasable programmable read only memories, which are referred to as EPROMs. As the name suggests,
in these memories data can be written any number of times, i.e. they are reprogrammable.
Reprogrammable ROMs are possible only in MOS technology. For erasing the content of the memory,
one of the following two methods are employed.
a) Exposing the chip to ultraviolet radiation for about 30 minutes.
b) Erasing electrically by applying voltage of proper polarity and amplitude. Electrically erasable PROM
is also referred to as E2PROM or EAROM.

ROM Organization:
A read only memory is an array of selectively open and closed unidirectional contacts. The address decoder
is usually divided in two parts for simplifying the decoder design. One half of the address lines are decoded
by one decoder used to energize one of the row lines, whereas the other half of the address lines are
decoded by another decoder used to activate column lines. This method of addressing is referred to as two
dimensional, X – Y, or coincident – selection, addressing. A unidirectional switch is incorporated at the
junction of every row and column.
A 16 – bit ROM array is shown in figure. To select any one of the 16 bits, a 4 – bit address (A3 A2 A1 A0) is
required. The lower order two bits (A1 A0) are decoded by the decoder DL which selects one of the four
rows, whereas the higher order two bits (A3 A2) are decoded by the decoder DH which activates one of the
four column sense amplifier.
The diode matrix is formed by connecting one diode along with a switch between each row and column.
For example, the diode D21 is connected between row 2 and column 1.
The output is enabled by applying logic 1 at the chip select (CS) input.
Programming a ROM means to selectively open and close the switches in series with the diode. For
example, if the switch of the diode D21 is in closed position and if the address input is 0110, row 2 is
activated connecting it to column 1. Also, the sense amplifier of column 1 is enabled which gives logic 1
output if the chip is selected (CS = 1). This shows that a logic 1 is stored at the address 0110. On the other
hand, if the switch of diode D21 is open, logic 0 is stored at the address 0110.

Read and Write Memory:

Many digital systems require memories in which is should be possible to write into or read from any
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memory location with the same speed. In such memories, the data stored at any location can be changed
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 during the operation of the system. This type of memory is known as a read/write memory and is usually
referred to as RAM (Random access memory).
The basic storage cell of a RAM is a FLIP – FLOP which simply consists of two cross coupled inverters as
shown in figure. A RAM is an array of these storage cells requiring as many FLIP – FLOPs as the bit storage
capacity of the RAM, which is usually a large number. Therefore, simpler FLIP – FLOP circuits using bipolar
or MOS transistors are used for RAM in order to save silicon chip area, reduce cost, increase speed of
operation and reduce power dissipation.
Bipolar RAMs are static, whereas the MOS RAMs can be static or dynamic. In general, bipolar RAMs are
faster (access time is of the order of a few tens of nanoseconds) and smaller in size (contains 1024 memory
cells or less) than the MOS RAMs, which have access time of the order of a few hundreds of nanoseconds
and storage capacity, upto 64K bits. With improvements in MOS technology, it has become possible to
make MOS RAMs with speeds comparable to those of bipolar RAMs.
Question:
How many memory locations are possible with the address lines
a) 8 b) 12 c) 16
Answer:
a) With 8 address lines there will be total 28 i.e. 256 memory locations from OOH to FFH.
b) With 12 address lines there will be total 212 i.e. 4096 memory locations. The range in Hexadecimal
address will be from OOOH to FFFH.
c) With 16 address lines, there will be 216 i.e. 65536 memory locations. The range in hexadecimal address
will be from OOOH to FFFH.
Question:
a) How many 128 X 8 RAM chips are required to provide a memory capacity of 2048 bytes?
b) How many lines of address bus must be used to access 2048 bytes of memory? How many lines of
these will be common to each chip?
c) How many bits must be decoded for chip select? What is the size of decoder?
Answer:
2048
a) No. of chips required = 128 = 16
b) Address lines for 2048 bytes will be P = log22048 = 11
Thus seven lines will be common
c) The number of lines to be decoded will be 11 – 7 = 4 so the sizes of the decoder will be 4 to 16.
Question:
A microprocessor uses RAM chips of 1024 X 1 capacity
a) How many chips will be required and how many address lines will be connected to provide the capacity
of 1024 bytes?
b) How many chips will be required to obtain a memory of capacity of 16K bytes?
Answer:
a) As only 1024 bytes are required. Hence, the number of RAM chips required will be 8. There are 10
address lines an chip which will be connected together.
b) For 16K bytes of memory, the number of required RAMs will be 16 X 8 i.e. 128. These chips will be
arranged in 16 rows of 8 chips in each row. Hence, there will be different output line and each output
line of the decoder will be connected to the common chip select pin of each row.
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 CHAPTER – 11
Programmable Logic devices:
Various ICs for performing basic digital operations and other functions such as multiplexers, Demultilexer,
adders, comparators, code converters, shift registers and counters etc. These ICs are referred to as fixed
function ICs i.e. each one of them performs a specific, fixed function. These devices are designed by their
manufacturers and are manufactured in large quantities to meet the needs of a wide variety of
applications and are readily available.
To design a circuit a designer can select from the available ICs most appropriate for the circuit, usually
working from a block diagram design concept. The design may have to be modified to meet the special
requirements of these devices. The advantages of this method are:
1. Low development cost,
2. Fast turn around of designs
3. Relatively easy to test the circuits
Some of the disadvantages of this method are:
1. Large board space requirements,
2. Large power requirements
3. Lack of security i.e. the circuits can be copied by others
4. Additional cost, space, power requirements etc required to modify the design or to introduce more
features.
To overcome the disadvantages of design using fixed – function ICs, application specific integrated
circuits (ASICs) are designed by the users to meet the specific requirements of a circuit and are
produced by an IC manufacture (foundry) as per specifications supplied by the users. Usually, the
designs are too complex to be implemented using fixed function ICs.
The advantages of this method are:
1. Reduced space requirement
2. Reduced power requirement
3. If produced in large volumes, the cost is considerably reduced.
4. Large reduction in size through the use of high level of integration
5. Designs implemented in this form are almost impossible to copy.
The disadvantages of this method are:
1. Initial development cost may be enormous
2. Testing methods may have to be developed which may also increase the cost and effort.
Another approach which has the advantages of both the above methods is the use of programmable
logic device (PLDs). A programmable logic device is an IC that is user configurable and is capable of
implementing logic functions. It is an LSI chip contain a ‘regular’ structure and allows the designer to
customize it for any specific application i.e. it is programmed by the user to perform a function
required for his application.
PLDs have the following advantages of fixed function ICs:
i) Short design cycle
ii) Low development cost
The advantages over fixed function ICs are:
i) Reduction in board space requirements
ii) Reduction in power requirements
iii) Design security
iv) Compact circuitry
v) Higher switching speed
PLDs have many of the advantages of ASICs as given below:
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i) Higher densities
ii) Lower quantity production costs
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iii) Design security

 iv) Reduced power requirement
v) Reduced space requirement
The PLDs allow designer more flexibilities to experiment with designs because these can be
reprogrammed in seconds. The design deficiencies and modification etc can be carried out in short
time thereby reducing the possibility of huge cost over runs.
PLDs are also useful for prototyping ASIC designs since foundry produced ASICs may require months of
costly development.
Because of various advantages of PLDs mentioned above, a large number of PLDs have been produced
by IC manufactures with variety of flexibilities and options available for a circuit designer and have
become very popular. The architecture and various other features of PLDs such as ROMs,
programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays
(FPGA). The use of these devices requires changes in the traditional design methods, although the basic
concepts remain the same.

ROM as a PLD:
A read only memory is basically a combinational circuit and can be used to implement a logic function. A
ROM of size M X N has M number of locations and N number of bits can be stored at each location. The
number of address inputs is PP, where 2P = M and the number of data output lines is N. It can also be
considered as a logic device with P inputs and N outputs as shown in figure.

The 16 – bit ROM array has four inputs and one output, i.e. M = 16, N = 1 and P = 4. The bit pattern stored,
can be considered as truth table with A3 A2 A1 A0 as 4 – bit input and Y as the output which is same as the
bit stored. The logic function corresponding to this is
Y = m (0, 6, 9, 12, 13, 15)
In general, a P variable N outputs logic function can be implemented using a ROM of size 2 P X N since all
the possible 2P minterms are effectively generated as is clear from the above discussion.
If a mask programmable ROM is used, the user can specify the bit pattern to be stored according to the
requirements of the logic function, whereas the user can himself program it in case of PROM, EPROM and
E2PROM. Since programmable ROMs can be used for logic design, therefore, it is also referred to as a
programmable logic device (PLD).
The advantages of using ROM as a programmable logic device are:
1. Ease of design since no simplification or minimization of logic function is required.
2. Design can be changed, modified rapidly
3. It is usually faster than discrete SSI/MSI circuit.
4. Cost is reduced.
There are few disadvantages also of ROM – based circuits, such as non – utilization of complete circuit,
increased power requirement and enormous increase in size with increase in number of input variables
making it impractical.

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