VLSI Design Lab Manual Roll No-

EXPERIMENT NO. 3

Aim: 1. Examine functionality of VHDL programming of Encoder and Decoder

using Xilinx ISE/Vivado software.

2.Examine functionality of VHDL programming of Encoder and Decoder on

FPGA/CPLD board.

Apparatus : Xilinx ISE 14.7i

Theory :

1. Encoder:
The combinational circuits that change the binary information into N output lines are
known as Encoders. The binary information is passed in the form of 2 N input lines. The
output lines define the N-bit code for the binary information. In simple words,
the Encoder performs the reverse operation of the Decoder. At a time, only one input line
is activated for simplicity. The produced N-bit output code is equivalent to the binary
information.

8 to 3 line Encoder:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder,
there is a total of eight inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e.,
A0, A1, and A2. In 8-input lines, one input-line is set to true at a time to get the respective
binary code in the output side. Below are the block diagram and the truth table of the 8 to 3
line encoder.

At any time, only one of these 8 inputs can be ‘1’ in order to get the respective
binary code at the output. The Truth table of 8 to 3 encoder is shown below,
 VLSI Design Lab Manual Roll No-

From Truth table, we can write the Boolean functions for each output as
A2 = Y7+Y6+Y5+Y4
A1= Y7+Y6+Y3+Y2

A0= Y7+Y5+Y3+Y1

We can implement the above two Boolean functions by using two input OR gates.
The circuit diagram of 8 to 3 encoder is shown in the following figure.
VLSI Design Lab Manual Roll No-

2. Decoder:
A decoder is a combinational logic circuit that is used to change the code into a set of
signals. It is the reverse process of an encoder. A decoder circuit takes multiple inputs and
gives multiple outputs. A decoder circuit takes binary data of ‘n’ inputs into ‘2^n’ unique
output. In addition to input pins, the decoder has a enable pin. This enables the pin when
negated, to make the circuit inactive. in this article, we discuss 3 to 8 line Decoder and
demultiplexer.

Let 3 to 8 Decoder has three inputs A2,A1 & A0 and four outputs Y7,Y6,Y5,Y4,Y3,Y2,Y1
& Y0. The block diagram of 3 to 8 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is
‘1’. The Truth table of 3 to 8 decoder is shown below.
 VLSI Design Lab Manual Roll No-
From Truth table, we can write the Boolean functions for each output as

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Each output is having one product term. So, there are four product terms in
total. We can implement these four product terms by using four AND gates
having three inputs each & two inverters. The circuit diagram of 3 to 8 decoder is
shown in the following figure.

Code
8:3 ENCODER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder;

architecture Behavioral of encoder is

begin
process(D)
 VLSI Design Lab Manual Roll No-
begin
case D is
when "00000001" => Y <= "000";
when "00000010" => Y <= "001";
when "00000100" => Y <= "010";
when "00001000" => Y <= "011";
when "00010000" => Y <= "100";
when "00100000" => Y <= "101";
when "01000000" => Y <= "110";
when "10000000" => Y <= "111";
when others => Y <= "000"; -- Default case to handle all other input scenarios
end case;
end process;
end Behavioral;

RTL schematic

Test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY ehjnhhh IS
END ehjnhhh;
 VLSI Design Lab Manual Roll No-

ARCHITECTURE behavior OF ehjnhhh IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT encoder
PORT(
D : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
signal D : std_logic_vector(7 downto 0) := (others => '0');

--Outputs
signal Y : std_logic_vector(2 downto 0);
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: encoder PORT MAP (
D => D,
Y => Y
);
begin
-- hold reset state for 100 ns.

D<="00000001";
wait for 100 ns;
D<="00000010";
wait for 100 ns;
D<="00000100";
wait for 100 ns;
D<="00001000";
wait for 100 ns;
D<="00010000";
wait for 100 ns;
D<="00100000";
wait for 100 ns;
D<="01000000";
wait for 100 ns;
D<="10000000";
wait for 100 ns;

--wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;

END;

Waveform
 VLSI Design Lab Manual Roll No-

CODE

3:8 DECODER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decod is

Port ( I : in STD_LOGIC_VECTOR (2 downto 0);

Y : out STD_LOGIC_VECTOR (7 downto 0));

end decod;

architecture Behavioral of decod is

begin

process(I)

begin

case I is

when "000" => Y <= "00000001";

when "001" => Y <= "00000010";

when "010" => Y <= "00000100";

 VLSI Design Lab Manual Roll No-
when "011" => Y <= "00001000";

when "100" => Y <= "00010000";

when "101" => Y <= "00100000";

when "110" => Y <= "01000000";

when "111" => Y <= "10000000";

when others => Y <= "00000000"; -- Default case to handle all other input scenarios

end case;

end process;

end Behavioral;

RTL

TESTBENCH CODE
 VLSI Design Lab Manual Roll No-

Conclusion:
From this experiment we examine and simulated functionality of VHDL
programming of Encoder and Decoder using Xilinx ISE software. Also
Examine functionality of VHDL programming of Encoder and Decoder on
FPGA/CPLD board.