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Undergraduate level QP on analog and digital electronics

This document is an examination paper for the subject 'Analog & Digital Electronics' for AMIETE – CS/IT, dated June 2019. It consists of 9 questions, with Question 1 being compulsory and covering various topics related to electronics, including amplifier gain, diode rectifiers, and digital logic. Students are required to answer a total of 5 questions from the remaining 8, ensuring at least two from each part.
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0% found this document useful (0 votes)
3 views3 pages

Undergraduate level QP on analog and digital electronics

This document is an examination paper for the subject 'Analog & Digital Electronics' for AMIETE – CS/IT, dated June 2019. It consists of 9 questions, with Question 1 being compulsory and covering various topics related to electronics, including amplifier gain, diode rectifiers, and digital logic. Students are required to answer a total of 5 questions from the remaining 8, ensuring at least two from each part.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

ROLL NO.

___________________

Code: AC103/AT103 Subject: ANALOG & DIGITAL ELECTRONICS

AMIETE – CS/IT {NEW SCHEME}

Time: 3 Hours June 2019 Max. Marks: 100

PLEASE WRITE YOUR ROLL NO. AT THE SPACE PROVIDED ON EACH PAGE
IMMEDIATELY AFTER RECEIVING THE QUESTION PAPER.
NOTE: There are 9 Questions in all.
• Question 1 is compulsory and carries 20 marks. Answer to Q.1 must be written in
the space provided for it in the answer book supplied and nowhere else.
• The answer sheet for the Q.1 will be collected by the invigilator after 45 minutes of
the commencement of the examination.
• Out of the remaining EIGHT Questions answer any FIVE Questions, selecting at
least TWO questions from each part, each question carries 16 marks.
• Any required data not explicitly given, may be suitably assumed and stated.

Q.1 Choose the correct or the best alternative in the following: (2×10)

a. The open loop gain of an amplifier is 200. If negative feedback with β=0.2 is
used, the closed loop gain will be
(A) 200 (B) 40.12
(C) 4.878 (D) 2.2

b. The theoretical maximum efficiency of a half wave diode rectifier is


(A) 40.6% (B) 50%
(C) 81.2% (D) slightly less than 100%

c. In CE amplifier circuit, voltage gain is directly proportional to


(A) β (B) collector supply voltage
(C) base resistance (D) None of these

d. A Colpitt’s oscillator uses


(A) a tapped inductor (B) an inductor & two capacitors
(C) Both (A) and (B) (D) Either (A) or (B)

e. If the midband gain of an amplifier is 40 dB the gain at half power frequency is


(A) 37 dB (B) 30 dB
(C) 20 dB (D) 13dB

f. In a 4 input AND gate, the total number of high outputs for 16 input states are
(A) 16 (B) 8
(C) 4 (D) 1

g. In a four variable k-map, 8 adjacent cells give a


(A) 2 variable term (B) single variable term
(C) 3 variable term (D) 4 variable term

AC103/AT103 /June 2019 1 AMIETE – CS/IT {NEW SCHEME}


ROLL NO. ___________________

Code: AC103/AT103 Subject: ANALOG & DIGITAL ELECTRONICS


h. Parallel adder is
(A) sequential circuit (B) combinational circuit
(C) Either (A) or (B) (D) None of these

i. A 4:1 MUX requires ________ data select line.


(A) 1 (B) 2
(C) 3 (D) 4

j. In a positive edge triggered JK FF J=1, K=0 and clock pulse is rising Q will be
(A) 0 (B) 1
(C) No change (D) Toggle

PART A
Answer at least TWO questions. Each question carries 16 marks.

Q.2 a. Draw the dc equivalent circuit for a diode and the piecewise linear equivalent
circuit. Discuss the application of each. (8)
b. In the below given circuit the zener diode is non-ideal, having a knee voltage
VZ0=9V and a dynamic resistance rZ = 5Ω. If the supply voltage VS varies from
15 to 30 V, determine the range of variation of the output voltage V0, also
comment on the result. (8)

Q.3 a. Draw the circuit diagram of a basic clamper circuit and explain the operation
briefly along with suitable waveforms. (8)

b. The voltage waveform Vi of Figure (a) is applied to the input of the circuit of
Figure (b), Show the output V0 waveform and mark the voltage levels. Find the
PIV of the diode, assumed to be ideal. (8)

Q.4 a. Explain BJT common-emitter configuration and draw a circuit for determining
common-emitter characteristics. (8)

AC103/AT103 /June 2019 2 AMIETE – CS/IT {NEW SCHEME}


ROLL NO. ___________________

Code: AC103/AT103 Subject: ANALOG & DIGITAL ELECTRONICS

b. In the circuit of figure shown below β = 99 and VBE = 0.7 V. Calculate the
quiescent values of IB, IC, IE & VCE. (8)
RB = 5KΩ
RE = 7KΩ
RC = 4KΩ
VCC = +15V
VEE = –15V

Q.5 a. For a voltage series feedback amplifier, find expression for input and output
resistance. (8)
b. Sketch the circuit diagram of Hartley oscillator and explain its working in detail. (8)

PART - B
Answer at least TWO questions. Each question carries 16 marks.

Q.6 a. Find the 11’s complement of following numbers: (4)


(i) (935)12 (ii) (267)12

b. X and Y are successive digits in positional number system and (XY)r = (25)10
and (YX)r = (31)10. Determine the value of X, Y and r. (4)

c. Why the Gray code is also known as reflected code? Write a brief note on
Gray code and its applications. (8)

Q.7 a. Minimize the following boolean function using K-Map:


F(A,B,C,D) = ∑ m(0,1,2,8,10,11,14,15) • d (9,12) (8)

b. Write a boolean expression for the following state:


“Z is TRUE if either X or Y is FALSE, otherwise Z is FALSE.” Write a truth
table for this expression. (8)

Q.8 a. How many 3:8 line decoder with enable input are required to construct 6:64
line decoder without using any other logic? Draw its block diagram also. (8)

b. Implement a full subtractor using two 4:1 Multiplexer. (8)

Q.9 a. Explain the procedure for conversion of RS Flip Flop to JK Flip Flop. (5)

b. What is race around condition? How it can be avoided? (5)

c. Design a binary counter with following binary sequence using D flip flop: (6)
0, 1, 3, 2, 6, 4, 5, 7 & repeat

AC103/AT103 /June 2019 3 AMIETE – CS/IT {NEW SCHEME}

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