MSE684: Introduction to Advanced

Microelectronics Packaging
Dr. Nilesh Badwe
Assistant Professor,
Department of Materials Science and Engineering,
IIT Kanpur
5. Substrates
 What is a Substrate?
• A dimensionally stable carrier that serve as an interface between ICs and the rest of the components
typically on PCBs in the system
• Contains wiring & interconnects connecting to fine-pitch chip I/Os on top side and coarse pitch board I/Os
on the bottom side
• A single or multi-layer wiring of conductors and insulators formed by thick or thin film processes

• ICs are connected to the substrates through wire-bonding or flip-chip method

 Substrate Functions
• Efficient transmission of signal and distribution of power to and from the ICs

• Heat dissipation

• Mechanical protection to the ICs

• Vibration, physical handling, etc.

• Chemical protection to the ICs

• Moisture, corrosive chemicals, etc.
 Anatomy of Substrates - 1
• Core: Bare unmetallized substrate on which
alternating layers of dielectric and metallic
patterns are built
• Provides mechanical stability to the substrate and
package
• Organic laminates, glass, ceramic, metal, and silicon
• Thickness: 30 – 800 µm (Packages can also be coreless)
• Material properties:
• High modulus to support metal wiring and minimize
warpage
• Low coefficient of thermal expansion (CTE) to reduce stress
 Anatomy of Substrates - 2
• Dielectric: Electrically insulating material
• Metal oxides, polymers, glasses
• Material properties:
• Low dielectric constant
• High resistivity
• High toughness and ductility

• Vias: metalized holes (typically Cu)

• Provide electrical connections between one wiring layer to
the next
• Blind via (between outer layer and inner layer), stacked vs
staggered via, fully/partially filled via
 Anatomy of Substrates - 3
• Pads: Ends of vias for external electrical connections

• Lines and traces: Conducting wire patterns for signal

and power transmission to and from vias

• Surface metallization: Coating on pads to preserve

underlying copper from oxidation
• Cu prone to oxidation during storage and assembly process
• Organic Solderability Preservative (OSP), Electroless Ni
• Electroplated Ni + matte Sn: 7.5 μm Sn over 5 μm Ni
Immersion Au (ENIG), Electroless Ni Electroless Pd • Electroplated Ni + hard Au: 0.75–1.25 μm Au (99.7%) over 5 μm Ni
Immersion Au (ENEPIG), Immersion silver (Im-Ag), • Electroplated Ni + soft Au: 0.75–1.25 μm Au (99.9%) over 5 μm Ni
Immersion tin (Im-Sn), Hot air solder leveling (HASL) • Eless Ni + imm Au (99.9% Au): 0.02–0.1 μm Au over 4.5 μm Ni
• Hot-air solder leveling (HASL) (Sn-Pb): 1.5–5 μm
• Organic solderability preservative (OSP): 0.2–0.5 μm
 Anatomy of Substrates - 4

• Solder mask or passivation layer: Insulating layer

deposited on the outer surfaces of the substrates
• Low wettability to molten solder
• Help prevent solder bridging between adjacent pads
• Protect underlying conductor patterns from oxidation
• Prevents chemical attack on dielectric material during
surface finish plating
Package Substrate Material Properties
 Desired Material Properties - 1
• High Thermal Stability:
• Ceramics and silicon have high melting temperature
• Glasses soften at > 600C (adequate thermal stability)
• Polymers may soften at solder assembly temperatures (Tg ~ 150 – 300C)

• Low Coefficient of Thermal Expansion (CTE):

• Si: 3 ppm/K
• CTE mismatch between substrate and Si can lead to high stresses during operation
• Ceramics: 3 – 7 ppm/K
• Polymers > 20 ppm/K
• Inorganic reinforcement (silica, alumina powder) used to lower polymer CTE
 Desired Material Properties - 2
• High Modulus:
• Minimizes warpage
• Ceramics (>150 GPa), Glass ( 65 - 80 GPa), Si (120 – 130 GPa)
• Polymers (0.1 – 40 GPa)

• High insulation strength/breakdown voltage:

• Ceramics preferred for high power/voltage applications for better electrical reliability

• High electrical resistivity:

• Minimizes power leakage between closely spaced conductors
• Ceramic, glass, and polymers have excellent resistivity
• Insulating liner used in silicon substrates
 Desired Material Properties - 3
• Dielectric constant/permittivity:
• Speed of signal transmission depend on the permittivity of
the dielectric medium
• Organic materials have lower dielectric constants and are
preferred in high speed computing applications over
ceramics
• Higher dielectric constant materials are used as embedded
capacitors for improving power delivery efficiency in the
package

• Hermiticity:
• Ceramic, glass, and silicon are hermitic (no moisture or gas absorptions)
• Prevent failures related to corrosion and electromigration
 Desired Material Properties - 4
• Good ductility:
• Ceramics, glass, and silicon are brittle à handling concerns during manufacturing with thin,
large panels

• Surface flatness:
• Glass, Si have smooth surfaces
• Helps in fine patterning of Cu traces using photolithography

• Low temperature processability:

• Processing temperatures for polymers are low (< 250C) à low manufacturing cost
 Thick Film/Ceramic Substrates
• Thick films of ceramics for insulator and metal paste for conductors

• Sheet casting/screen printing process followed by high temperature firing/sintering

for manufacturing

• Layer thickness: 50 – 100 µm, multiple layers up to 100 can be co-fired

• Advantages: High rigidity, high thermal stability, low electrical loss, and hermiticity

• Disadvantage: Expensive, high temperature processing

 Ceramic Substrate Assembly Process

Tummala, R.R., 2001. Fundamentals of microsystems packaging.

 Glass-Ceramic based Substrates
• Ceramics: • Glass - ceramics:
• Alumina (most common in 1980s): • Alumina + Alumino silicates w/ Li, B glassy phase

• Low loss, high dielectric strength, low cost

• Low CTE and dielectric constant (controllable)
• High CTE à Reliability challenges

• Needs sintering temperatures > 1400∘C à • Sintering temperature ~ 850∘C; glassy phases
incompatible with several metals melt at lower temperature, Low Temperature
Co-fired Ceramics (LTCC)

• Typical metals used for conducting lines: Mo, Pt, • Can use high conductivity metals like Cu, Ag, Ni,
Pt-Pd Ag-Pd alloys
 Applications of LTCC
• High Performance • RF and mm-wave (5G, 6G): • Automotive and High
Computing: • Low dielectric loss and high Power
precision circuitry enables RF
• Low CTE à high reliability Interconnects • High temperature stability
enables high power
• High dielectric constant for low packages with high
loss RF capacitors reliability

Ack: Venky Sundaram, PDC course 2023

 Thin Film/Organic Substrates
• Thin films of polymers for insulator and copper for
conductors
• Polymer films: liquid or dry film deposition
• Copper: lithography and electrodeposition

• Layer thickness: 5 – 50 µm

• Advantages: High wiring density, low cost, thin form

factors, low dielectric constant, CTE matching with PWB,

• Disadvantages: Low thermal stability, moisture absorption,

low strength, high CTE
 Core Materials-1
• Organic resin (e.g. epoxy) + Inorganic reinforcement (glass fiber and/or silica particles) +
additives (e.g. flame retardants)

• FR-4/FR-5: Most common series of organic

laminate core materials. Comprised of one of
several functional types of epoxy resins for a
range of 𝑇g
• More epoxy groups à Higher Tg
• Bifunctional 110C
• Tetrafunctional 130 – 140C
• Multifunctional 170 – 190C
 Core Materials-2
• Early 2000s, Pb-Sn eutectic solder (Tm = 183C) was
replaced with lead-free solders, primarily Sn-Ag-Cu (Tm
= 217C)
• Need for high Tg polymers:
• Cyanate Esters: Excellent electrical properties but brittle and
poor adhesion to Cu
• Polyimide: Very high moisture absorption and poor reliability
• Cyanate esters blended with epoxy resins à BT system
• Bismaleimide-Triazine (BT):
• High 𝑇g
• Excellent adhesion to Cu
• Good thermo-mechanical properties, high toughness
• Used in high performance package substrates
Properties of Core Materials
 Production Process for Copper Clad Laminates (CCLs)
• Prepreg: Polymer resin impregnated into
woven glass fabrics and partially cured to
enable handling, while retaining adhesive
properties

• Laminate: Final organic core material

fabricated by hot pressing several prepregs
(to achieve final thickness) with copper foils
on both surfaces, a fully cured material
ready for through via fabrication

Woven glass Prepreg

 Organic Substrate
Manufacturing
• Through core vias
• Drilled mechanically (more common) or
UV/CO2 laser
• Diameter 60-150 µm

• Subtractive Process:
• Photoresist pattern
• Cu etching to create a pattern
• Photoresist strip-off
 Subtractive Process for Core Metallization - 1
• After the via drilling, they are filled with Cu
• Core patterns mainly used for power delivery
• Need thick Cu à feature size not critical à
cheaper subtractive process is used
• Electroless Cu deposition (< 1 µm) for seed
layer followed by Cu electrodeposition
• Electrodeposition:
• Electrolyte: CuSO4, H2SO4 and additives like
brightener and levelers
• Current: Cu2+ + 2e- à Cu
• Final Cu thickness ~ 35 – 50 µm
Cu Electroless Deposition Process
• Smallest achievable feature ~ 100 µm
 Subtractive Process for Core Metallization - 2
• Photolithography (3 Steps):
• Lamination of dry-film photoresist (PR)
• UV beam (355 nm) exposure to create desired pattern
• Development of the photoresist

• Subtractive Cu etching
• Alkaline ammonia, hydrogen peroxide–sulfuric
acid, copper chloride

• Stripping of Photoresist
 Semi-additive Process
• Build-up layers need fine patterning
• Semi-additive process:
• Deposition (additive) of an electroless Cu seed layer
• Patterning the circuit using electrolytic plating
through a patterned (opened) photoresist mask
• Etching (subtractive) this seed layer from the
undesired areas
• Subtractive part involves removal of very thin Cu
seed layer (0.2-0.4 µm) unlike purely subtractive
process à fine features achievable
• Cleaning steps are critical to ensure good connection
• Most common build-up process flow used in between Cu layers
organic substrate manufacturing • Note: Flat surface with differential Cu electroplating
thicknesses
 Properties of Dielectric Materials
• Ajinomoto build up film (ABF™): • BCB (Benzocyclobutene) dielectric:
• Polymer epoxy blended with silica • Low loss tangent
• Loss tangent modified with silica fillers • Needs high temp curing and Poor adhesion
• Most commonly used dielectric in organic substrates
 Laser Via Processing
• Laser ablation process is driven by absorption of the laser wavelength by a
particular material i.e. energy absorption à ablation

• Cu acts as • Excited dimer

Excimer laser protective layer • Noble gas halide
(126-351 nm) YAG UV laser CO2 laser (IR) • Thermal à debris (metastable state)
(355 nm) (9.3-10.6 µm) • Very fine features
 Recap: Subtractive vs Semi-additive Processes
• Subtractive: Core layers (thick planes for power delivery network)
• Semi additive: build-up layers (fine features for signal routing)

Trapezoidal shaped - Concerns achieving features < 20 µm

I shaped - Feature < 10 µm achievable

Coreless Technology
• Thinner with higher performance
• Requires stiffener to limit/control
warpage

Stiffener

Si Chip
 Organic Substrate
Manufacturing
Process

Shi, S., Tortorici, P., Vadlamani, S. and Chatterjee, P., 2021. Fundamentals of advanced
materials and processes in organic substrate technology. In 3D Microelectronic
Packaging (pp. 397-429). Springer, Singapore.
 Organic Substrate Manufacturing (Alternate
Slide)

https://www.youtube.com/watch?v=HiJHMBPcOyg
 Routing Example for Multilayer Build-up
• Pitch = 100 µm
• Bump diameter = 40 µm

• Calculate the size of wiring for accessing

• Two signal layers
• Three signal layers
• Four signal layers
Wire routing direction
• Can you comment on the no. of build-up
film/metal layers required for each of
these?

• Smaller dimensions à Less no. of layers for a given bump size and pitch à Reduced
manufacturing complexities
 High Volume Application of Organic
Substrate in CPUs
• Can you find?
• Conformally coated through via
• Conformally coated buried via
• Cu via created through
subtractive process
• Cu via created through semi-
additive process
 Substrates for Different Applications

• Substrates for notebook/laptop

applications à thinner and smaller
• Recent generation packages have 4-2-4
layers

• Desktop and Server application

substrates are thicker and larger
Intel i5 4th Gen notebook processor with 3-2-3 substrate
• Intel Xeon substrates had 8-2-8 layers
3 build-up metal layers – 2 core metal layers – 3 build-up metal layers about 8-10 years ago
 Package-on-Package (POP)
• Smartphone and tablet applications

• Memory chip attached to top substrate through

wire-bonding

• Logic processor chip is assembled by flip-chip

process onto the bottom package substrate

• Top package attached to the bottom package Apple iPhone/iPad A8 process

around the logic IC using BGAs
 Thin Film/Glass Substrates

Motivation for glass substrates Anatomy of glass substrate

Ack: Venky Sundaram, PDC course 2023

 Thin Film/Glass Substrates
• Amorphous material/glass (borosilicates, alumino borosilicates) used as a core with
polymers as the rest of the dielectric layers

• Glass: Fast cooling of heated viscous mixture of dry material à different drawing process
• Polymer films: liquid or dry film deposition
• Copper: lithography and electrodeposition

• Core thickness: 30 – 100 µm

• Advantages: Smooth surface finish, small form factors

• Disadvantages: Brittleness
 Glass Substrates Manufacturing
• Polymer layer between glass and Cu
used as a buffer to reduce CTE
mismatch and improve adhesion

• Via drilling through laser (Via-in-via)

• Deep UV laser photons break chemical
bonds leading to cold ablation
• Far-infrared laser à thermal interaction
à heat generated to vapourize the glass

• The rest of the process similar to

organic substrates (lamination,
photoresist, Cu patterning)

What process can be used for the polymer lamination in step 2?

 Thin Glass Roll for Substrates

30 – 100 µm Glass roll for 30 µm Glass core substrate

substrate core manufacturing
Sep 2023 - Intel announced Glass-based Substrates
 Ultra Thin Film Substrates/Silicon Substrates

Controlled collapse
chip connection,
same as flip chip

• Si - best-understood material
• Silicon used as a interposer on organic substrate or fan-out package substrate;
• Interposer: Usually uses organic substrate as the main substrate for PCB mounting
• Ultra thin films of SiO2 for insulator and copper for conductors
• Applications in mobile processors (iPhone), high performance GPUs (AMD Radeon)
 Silicon Substrates Manufacturing
• Silica/SiO2: thermal oxidation or chemical
vapour deposition
• Copper: lithography and
electrodeposition
• Deep reactive ion etching (Bosch process)
used for via formation
• Ti, TiN, Ta layers between SiO2 and Cu as
diffusion barrier
• Passivation layer to prevent bridging:
Silicon nitride (SiNx)
• Secondary passivation polyimide
(Kapton) à stress buffer + adhesion layer
for metal plating
Bosch Process: https://www.youtube.com/watch?v=6Wva2a_4IA4&
 Intel’s EMIB Technology (2.5D packaging)

https://www.youtube.com/watch?v=mRQFJFmYMak&
 Summary 1
• Substrates: Provide wiring to connect fine pitch ICs (40 – 100 µm) to board with
pitch 400 – 800 µm

• Typical structure includes core, dielectrics, vias, lines, traces, pads, surface
metallization, and passivation layer (solder mask, SiNx etc)

• Key material properties: thermal stability, CTE, modulus, resistivity,

permittivity, ductility, flatness, process temperature
• Optimization to achieve the best mechanical strength/reliability, electrical, and thermal
performance along with low cost manufacturing
 Summary 2
• Thick film/Ceramic substrates: Rigid, thermally stable but
expensive

• Thin film/Organic substrates: Polymer material,

inexpensive, challenges with CTE mismatch, thermal
stability, used in low-cost applications

• Thin film/Glass substrates: Core made of glass with

polymer layers as dielectrics

• Ultra thin film/Silicon substrates: Si based substrate as an

interposer (2.5D packaging) with very high wiring density
for high performance applications
 Future Needs to Package Substrates

Ack: Venky Sundaram, PDC course 2023