MODULE 1

BINARY ARITHMETIC
Binary arithmetic is essential part of all the digital computers and many other digital system.

Binary Addition
It is a key for binary subtraction, multiplication, division.
There are four rules of binary addition.
0+0=0
0+1=1
1+0=1
1+1=0 plus a carry of 1 to next higher column
In fourth case, a binary addition is creating a sum of 1 + 1 = 10 i.e. 0 is written in the given
column and a carry of 1 over to the next column.
Example1
Add binary number 10011 and 1001
Solution

Example 2
Add binary number 100111 and 11011
Solution
Binary Subtraction
Subtraction and Borrow, these two words will be used very frequently for the binary subtraction.
There are four rules of binary subtraction.
0-0=0
0-1=1 with a borrow from the next column
1-0=1
0-0=0
Example 1
Subtract binary number 01110 from 10101
Solution

Binary Multiplication
Binary multiplication is similar to decimal multiplication. It is simpler than decimal multiplication
because only 0s and 1s are involved.
There are four rules of binary multiplication.
0 x 0=0
0 x 1=0
1 x 0=0
1 x 1=1
Example
Multiply binary number 1010 and 1001
Solution

Binary Division
Binary division is similar to decimal division. It is called as the long division procedure.
Example

Representation of Signed Numbers

We need to represent both positive and negative numbers. Two forms are there for representing
such numbers:
• Sign-magnitude form
• Complement form
o 1’s complement
o 2’s complement
Most digital computers do subtraction by 2’s complement method. Advantage of both methodsis
reduction in hardware. Instead of having separate digital circuits for addition and subtraction,only
adding is required.
In 2’s (or 1’s )complement system for representing signed numbers,
1. If the number is positive ,the magnitude is represented in its true binary form and a sign
bit 0 is placed in front of the MSB.
2. If the number is negative ,the magnitude is represented in its 2’s or1’s complement form
and a sign bit 1 is placed in front.

Sign-magnitude Form
When a signed binary number is represented in sign-magnitude, the left-most bit is the sign bit
and the remaining bits are the magnitude bits. A 0-sign bit indicates a positive number, anda
1 sign bit indicates a negative number. The magnitude bits are in true binary for both positive
and negative numbers.
For example, the decimal number +25 is expressed as an 8-bit signed binary number using the
sign-magnitude form as,
00011001
Sign bit Magnitude bitsThe
decimal number -25 is expressed as 10011001.
Notice that the only difference between +25 and 225 is the sign bit because the magnitude bits
are in true binary for both positive and negative numbers.
In the sign-magnitude form, a negative number has the same magnitude bits as the
corresponding positive number but the sign bit is a 1 rather than a zero.

1’s Complement Form

The 1’s complement of a binary number is found by changing all 1s to 0s and all 0s to 1s, as
illustrated below:
10101110 Binary number
↓↓↓↓↓↓↓↓
01010001 1’s complement

2’s Complement Form

Methods of obtaining the 2’s complement of a number:
 1. By obtaining the 1’s complement of the given number (by changing all 0s to 1s and 1s
to 0s)and then adding 1.
Example:
10101110 Binary number
01010001 1’s complement
1
01010010 2’s complement

2. By subtracting the given n-bit number N from 2n.

Example:
10101110 Binary number
Number of bits (n)= 8
2n = 28= 256
10000000 Binary of 256

10101110 256 - 25 (2n – N)

01010010 2’s complement

3. Starting at the LSB ,copying down each bit up to and include the first 1 bit encountered
and complementing the remaining bits.
Example:
10101110 Binary number

↓↓↓↓↓↓↓↓

01010010 2’s complement

Special case in 2’s complement form:
When a signed number has a 1 in the sign bit and all 0’s for the magnitude bits, then the decimal
equivalent is -2n, n is number of bits in the magnitude.
Example:
1000
Sign bit Magnitude bits
Number of magnitude bits = 3
-2n = -23 = -8
i.e., the decimal equivalent of 1 0 0 0 = -8.
Characteristics of 2’s Complement Numbers:
1. There is one unique zero.
2. The 2’s complement of 0 is 0.
3. The left most bit cannot be used to express a quantity. It is a sign bit. If it is a 1 ,the
number is negative and if it is 0.
 4. For an n-bit word which includes the sign bit, there are 2n-1-1positive integers, 2n-1
negative integers and one 0,for a total of 2n.
Example:
Consider a 4-bit word,
then n is 4 = 2(4-1)-1 positive integers = 23-1 = 7 positive integers
also 24-1 = 23 = 8 negative integers
Total combination =2n = 24 = 16 combinations
5. Significant information is contained in the 1s of the positive numbers and 0s of the
negative numbers.
6. A negative number may be converted into a positive number by finding its 2’s
complement.

1’s Complement Arithmetic

• 1’s complement is obtained by complementing each bit of the number ,that is changing
all 0s to 1s and all 1s to 0s.
• In 1’s complement subtraction, add the 1’s complement of the subtrahend to the
minuend.
• If there is a carry out, bring the carry around and add it to the LSB. This is called the
end around carry.
• If the MSB is 0, the result is positive and true binary.
• If the MSB is a 1, the result is negative and is in its 1’s complement form.

Example:
1. Subtract 14 from 25 using the 8 bit 1’s complement arithmetic.
25 = 00011001
14 = 00001110
-14 = 11110001

00011001 Binary of 25

11110001 1’s complement of -14

1 00001010
1 Add the end around carry.
00001011
The MSB is 0. So, the result is positive and is in its normal binary form. Therefore, the
result is +11.
 2. Add -25 to +14 using the 8 bit 1’s complement method.
14 = 00001110
25 = 00011001
-25= 11100110
00001110 Binary of 14

11100110 1’s complement of -25

11110100 No carry

There is no carry and the MSB is 1. So, the result is negative and is in its 1’s
complement form .The 1’s complement of 11110100 is 00001011. Answer is -11.

3. Add -25 to -14 using the 8 bit 1’s complement form.

14 = 00001110
-14 = 11110001
25 = 00011001
-25= 11100110
11100110 Binary of -25

11110001 1’s complement of -14

1 11010111

1
11011000
The MSB is 1. So, the result is a negative and is in its 1’s complement form. The 1’s
complement of 11011000 is 00100111. Answer is -39.

2’s Complement Arithmetic

• The word length of a computer is fixed.
• That is if a 4bit number is added to another 4-bit number, the result will only be four
bits
• Carry from the fourth bit will overflow.
• In the 2’s complement subtraction, add the 2’s complement of the subtrahend to the
minuend .
• If there is carry out, ignore it.
• If the MSB is 0, the result is positive and in its true binary form.
• If the MSB is 1, the result is negative and in its 2’s complement form.
 Example:
1. Subtract 14 from 46 using 8 bit 2’s complement arithmetic.
46=00101110
14=00001110
-14=11110010
00101110 Binary of 46

11110010 1’s complement of -14

100100000
Ignore the carry. The MSB is 0,so the result is positive and is in normal binary form.

2. Add -75 to +26 using the 8bit 2’s complement arithmetic

26=00011010
75=01001011
-75=10110101
00011010 Binary of 26

10110101 2’s complement of -75

11001111
There is no carry, the MSB is 1. So, the result is negative and is in 2’s complement
form.

Binary Codes
WHAT IS BINARY CODE?
Binary code, used in digital computers, based on a binary number system in which there are only
two possible states, off and on, usually symbolized by 0 and 1. ... In binary code, each decimal
number (0-9) is represented by a set of four binary digits, or bits.

Weighted and Non-Weighted Codes

BCD Code
• Binary coded decimal(BCD) is a class of binary encodings of decimal
• The digits of a decimal number are encoded one at a time into group of four binary digits
• Combines the features of both decimal and binary numbers
• To represent decimal digits from 0 to 9 it is necessary to use a sequence of at least four
binary digits
• Such a sequence of binary digits which represent a decimal digit is called a code word

BCD Code

● Obey position weighting principle

● Each position of the number Do not obey positional weighting
represents a specific weight principle
● In each group of 4 bits the sum of
the weights of those positions
where the binary digit is 1 is equal
to the decimal digit
● May be either positively -weighted
or negatively -weighted

The 8421 BCD code

The 8421 BCD code
• Each decimal digit from 0 to 9 is coded by a 4 bit binary number
• It is a weighted code and is also sequential(each succeeding code word is one binary
number greater than its preceding code word.)
• Main advantage of this code code is its ease of conversion to and from decimal For
example: decimal digit 14 can be coded as 0001 0100
• Main disadvantage is that it is less efficient than the pure binary in the sense it requires
more bits
• Another disadvantage is arithmetic operations are more Complex than they are in pure
binary.

BCD Arithmetic
• Disadvantage of the 8421 code is that the rules of binary addition and subtraction do not
apply to the entire 8421 number not only to the individual 4- bit groups

• The BCD addition is therefore performed by individually adding the corresponding digits
of the decimal numbers expressed in 4 bit binary groups starting from the LSD .
• If there is a carry out of one group to the next group or if the result is an illegal code then
6 (0 1 10 ) is added to the sum term of that group and the resulting carry is added to the
next group
• The BCD subtraction is performed by subtracting the digits of each 4- bit group of the
subtrahend and from the corresponding 4 bit group of the minuend in binary starting from
the LSD.
• If there is a borrow from the next group then 6 (0 1 10) is subtracted from the difference
term of this group period this is done to skip the six illegal States.
 Nine’s complement and ten’s complement

● 9’s complement of a decimal number is obtained by subtracting each digit of that decimal
number from 9
● The 10’s complement of a digital number is obtained by adding a one to its 9’s complement
● To perform decimal subtraction using the 9’s complement method obtain the 9’s
complement of the subtrahend and add it to the minuend
● Call this number as the Intermediate result
● If there is a carry it indicates that the answer is positive ,add the carry to the LSD of this
result to get the answer the carrier is called the end around carry
● If there is no carry it indicates that the answer is negative and the Intermediate result is its 9
‘s complement take the 9’s complement of this result and place a negative sign in front to get
the answer
● To perform decimal subtraction using the 10’s complement method obtain the 10’s
complement of the substrahend and and add it to the minuend
● If there is a carry ignore it ,the presence of the Carrie indicates that the answer is positive the
result is the result obtained is itself the answer
● if there is no carry it indicates that the answer is negative and the result obtained is its 10’s
complement obtain the 10’s complement of the result and place in negative sign in front to
get the answer

Examples

Find the 9’s complement of the following decimal numbers:

 Gray Code

● The gray code is unweighted and is not an arithmetic code that is there are no specific
weights assigned to the bit positions.
● The most important feature of the gray code is that it exhibits only a single bit change
from one codeword to the next in sequence this property is important in many
applications such as shaft position encoders
Binary to gray code conversion
The rules for conversion are:-
1. The most significant bit ( leftmost ) in the gray code is the same as the corresponding MSB
in the binary number
2. Going from left to right, add each adjacent pair of binary code to get the next gray code bit
.Discard carries

For example convert the binary number 10110 to gray code

Gray to binary code conversion

The rules for conversion are:-
1. The most significant bit (leftmost ) in the gray code is the same as the corresponding MSB in
the binary code
2. Add each binary code bit generated to the gray code bit in the next adjacent position. Discard
carries
For example convert the gray code 11011 to binary

Error –Detecting Codes

• When a binary data is transmitted and processed ,it is susceptible to noise that can alter or
distort its contents
• The 1s may get changed to 0s and 0s to ones.
• Because digital system must be accurate to the the digit , errors can pose a serious problem .
• Several schemes have been devised to detect the occurrence of a single bit error in a binary
word so that whenever such an error occurs the concerned binary word can be corrected and
retransmitted.

Parity
• Simplest technique for detecting errors is that of adding an extra bit known as the parity bit
to each word being transmitted.
• There are two types of parity odd parity and even parity.
• For odd parity the parity bit is set to a 0 or a 1 at the transmitter such that the total number of
1 bits in the word including the parity bit is an odd number.
• For even parity the parity bit is set to a 0 or a 1 at the transmitter such that the total number
of 1 bit in the word including the parity bit is an even number.
Parity
• When the digital data is received a parity checking system generates an error signal if the
total number of 1 s is even in an odd parity system or odd in an even parity system.
• This parity check can always detect a single bit error but cannot detect two or more errors
within the same word
• Odd parity is used more often than even parity because even parity does not detect the
situation where all zeros are created by a short circuit or some other fault condition
In an even parity scheme,which of the following words contain an error

a)10101010 b)11110110 c)10111001

Solution:-
a) the number of 1s in the word is even(4).Therefore there is no error
b) the number of 1s in the word is even(6).Therefore there is no error
c) the number of 1s in the word is odd (5).So this word has an error

In an odd parity scheme,which of the following words contain an error

a)10110111 b)10011010 c)11101010

Solution:-
the number of 1s in the word is even(6).So this word has an error
the number of 1s in the word is even(4).So this word has an error
the number of 1s in the word is odd (5).Therefore there is no error

Check sums
• Simple parity cannot detect two errors within the same word
• To overcome:-use two-dimensional parity
• As each word is transmitted ,it is added to the sum of the previously transmitted word and
the sum retained at the transmitters end
• At the end of transmission ,the sum (called checksum) up to that time is sent to the receiver.
• The receiver can check its sum with the transmitted sum.
• If two sum are the same ,then no errors were detected at the receivers end
• If an error were detected at the receiver end ,receiving end asks for retransmission
Block Parity
• When several binary words are transmitted or stored in succession ,the resulting
collection of bits can be regarded as a block of data having rows and columns
• Parity bits can be assigned to both rows and columns
Error -Detecting Codes

➢ When a binary data is transmitted and processed ,it is susceptible to noise that can alter or
distort its contents

➢ The 1s may get changed to 0s and 0s to ones.

➢ Because digital system must be accurate to the the digit , errors can pose a serious
problem .

➢ Several schemes have been devised to detect the occurrence of a single biterror in
a binary word so that whenever such an error occurs the concernedbinary word can
be corrected and retransmitted

Parity
➢ Simplest technique for detecting errors is that of adding an extra bit known as the parity
bit to each word being transmitted.
➢ There are two types of parity odd parity and even parity.
➢ For odd parity the parity bit is set to a 0 or a 1 at the transmitter such that the total
number of 1 bits in the word including the parity bit is an odd number.
➢ For even parity the parity bit is set to a 0 or a 1 at the transmitter such that the total
number of 1 bit in the word including the parity bit is an even number.
Parity

• When the digital data is received a parity checking system generates an error signal if the
total number of 1 s is even in an odd parity system or odd in an even parity system.
• This parity check can always detect a single bit error but cannot detect two or more errors
within the same word
• Odd parity is used more often than even parity because even parity does not detect the
situation where all zeros are created by a short circuit or some other fault condition

In an even parity scheme,which of the following words contain an error

a)10101010 b)11110110 c)10111001
Solution:-
a)the number of 1s in the word is even(4).Therefore there is no error
b)the number of 1s in the word is even(6).Therefore there is no error
c)the number of 1s in the word is odd (5).So this word has an error

In an odd parity scheme,which of the following words contain an error

a)10110111 b)10011010 c)11101010
Solution:-
a)the number of 1s in the word is even(6).So this word has an error
b)the number of 1s in the word is even(4).So this word has an error
c)the number of 1s in the word is odd (5).Therefore there is no error
Check sums
• Simple parity cannot detect two errors within the same word
• To overcome:-use two-dimensional parity
• As each word is transmitted ,it is added to the sum of the previously transmitted word and
the sum retained at the transmitters end
• At the end of transmission ,the sum (called checksum) up to that time is sent to the
receiver.
• The receiver can check its sum with the transmitted sum.
• If two sum are the same ,then no errors were detected at the receivers end
• If an error were detected at the receiver end ,receiving end asks for retransmission

Block Parity
●When several binary words are transmitted or stored in succession ,the resulting
collection of bits can be regarded as a block of data having rows and columns
●Parity bits can be assigned to both rows and columns
Error -Correcting Codes
●A code is said to be an error correcting code,if the correct code word can always
be detected from the erroneous word.

●If the location of an error has been determined ,then by complementing the
erroneous digit ,the message can be corrected.

●One type of error correcting code is the Hamming code.

The 7-bit Hamming Code

●To transmit 4 data bits ,3 parity bits located in positions 20,21,22are added to
make a 7 bit code word which is then transmitted.

●The word format be as shown below :

D7 D6 D5 P4 D3 P2 P1
D bits are data bits and the P bits are the parity bits
I.e 4 bit data +3 parity bits gives us =7 bit
Parity bits are placed in powers of 2
ALPHANUMERIC CODES
●Alphanumeric codes are codes used to encode the characters of alphabets in
addition to decimal digits

●They are used primarily for transmitting data between computers and its I/O
devices such as printers ,keyboards and video display terminals.

●The most popular modern alphanumeric codes are:-

○ASCII code

○EBCDIC code
The EBCDIC Code
●EBCDIC full form Extended Binary Coded Decimal Interchange Code

●Pronounced as ‘eb-si-dik

●Is an 8 bit alphanumeric code

●Using 8 bit 28(=256)bit patterns can be formed.

●EBCDIC code can be use to encode all the symbols and control characters found
in ASCII

FROM QUESTION PAPERS

1. Explain about the error detecting codes-(9 MARKS-2018)
2. Error detection codes with an example-(essay-2019)
BOOLEAN ALGEBRA
LOGIC OPERATIONS
AND
Logic operations include any • OR
operations that
• NOT
manipulate Boolean values.
• NAND
Boolean values are either true or false.
Various Logic operations are.. • NOR
• X-OR
• X-NOR
Basic Gates
Q = AB + BC(B+C)
 Axioms of Boolean Algebra

Set of logical expressions that we accept without proof and upon

which we build a set of useful theorems
Axiom 1: 0.0=0 Axiom 6: 0+1=1
Axiom 2: 0.1=0 Axiom 7: 1+0=1
Axiom 3: 1.0=0 Axiom 8: 1+1=1
Axiom 4: 1.1=1 Axiom 9: ¯1=0
Axiom 5: 0+0=0 Axiom 10: ¯0=1
Complementation rule:
The term complementation means to invert ,i.e to change 0s to
1s and 1s t 0s.
AND rule & OR rule:
Commutative rule:
Commutative Law allow change in positon of AND or Or
variables.There are two commutative Law:-
Law 1: A+B=B+A
Commutative rule:
Law 2: A.B=B.A
Association rule:
Association rule:
Distributive rule:
Distributive rule:
Distributive rule:
Idempotence Laws Identity Laws
1. A.A = A 1.A.1 = A
2. A+A = A 2. A + 1 = 1
Complementation/Negation Laws Absorption Laws
1. A.A’ = 0 1. A + A.B = A
2. A+A’ = 1 2. A(A + B) = A
Double Negation Law
1. (A’)’ = A
CONSENSUS THEOREM:
TRANSPOSITION THEOREM:
Reducing Boolean Expression

Every boolean expression must be reduced to a simple term

As the elements represent a corresponding element of
hardware ,the minimual element reduces the cost and
increases reliability.
The procedure is as follows:-
Multiply all variables necessary to remove parantheses.
Look for identical terms .Only one term is retained and all
others are dropped.
AB+AB+AB+AB=AB
Look for a variable and its negation in the same term .The
term must be dropped.For example,
A.BB=A.0=0;
ABCB=AB.0=0
Reducing Boolean Expression

The procedure is as follows:-

Look for pairs of terms that are identical except for one
variable which may be missing in one of the terms.The larger
term can be dropped.
ABCD+ABC=ABC(D+1)=ABC.1=ABC
Look for the pair of terms which have the same variables ,with
one or more variables complemented.If a variable in one of such
a pair is complemented while in the second term it is not
,then such a term can be combinedd into a single term with
the variable dropped.For example,
ABCD+ABCD=ABC(D+D)=ABC .1=ABC AB(C+D)+AB(C +
D)=AB[(C+D)+(C +D)]=AB.1=AB
Reduce the
expression

1 A[B+C(AB +AC)]
2 A+B[AC+(BCD)]
3 A+BC(AB+ABC)
4 (B+BC)(B+BC )(B+D)
5 AB+ABC+BC=AC+BC
Additional Theorm

Theorem ( 1)
X.f(X,X, Y, ....., Z)=X.f(1,0,Y,....Z)
This theorm states that if a function containing expression /terms
with X and X is multiplied by X,then all the Xs and Xs in the function
can be replaced by 1s and 0s ,respectively.This is permissible
because

X.X=X=X.1 and X.X=X.0

Additional Theorm

Theorem (2)
X+f(X,X,Y,....Z)=X+f(0,1,Y,....Z)

This theorm states that if a function containing expression /terms

with X and X is added to X,then all the X s and Xs in the function can
be replaced by 0s and 1s ,respectively.

X+X=X=X+0 and X+X=1=X+1

Karnaugh Map
Introduction

Boolean expressions can be simplified algebraically

But this never ensures the minimal expression obtained is real
minimal.
The Karnaugh-map (K-Map) is a systematic method of
simplyfing Boolean expression
K-map is a chart or a graph ,composed of an arrangement of
adjacent cells ,each representing a particular combination in
sum or product form.
Like Truth Table,it shows relationship between logic input and
desired output.
Introduction

A n-variable function can have 2n possible combination of

product terms in SOP form,or 2n possible combination of sum
terms in POS form.
A two variable K-map will have 22=4 cells or squares,a three
variable map will have 23=8 cells or squares.
Any Boolean expression can be expressed in a standard or
canonical or expanded sum (OR )of products (AND)–SOP
form or in a standard or canonical or expanded
product(AND)of sums (OR)–POS form .
A standard SOP :is one in which a number of product
terms,each one of which contains all variables of the function
either in complemented or non-complemented form ,summed
together.
Introduction

A standard POS :-form is one in which a number of sum

terms,each one of which contains all the variables of function
either in complemented or non-complemented form are
multiplied together.
Each of the product terms in the standard SOP form is called a
minterm
Each of the sum terms in the standard POS form is called a
maxterm
Minterms and maxterms are represented as binary terms of 0s
and 1s .
Introduction

For minterms ,binary words are formed by

Non complemented variable represented as 1
complemented variable represented as 0
The decimal equivalent of the binary word is expressed as a
subscript of lower case m,i.e m0,m2,m5,m7 etc.
For maxterms ,binary words are formed by
Non complemented variable represented as 0
The complemented variable
decimal equivalent represented
of the binary as 1
word is expressed as a
subscript of upper case m,i.e M0,M2,M5,M7 etc.
Expansion Of A Boolean Expression To SOP Form
Steps:-
1 Write down all the terms

2 If one or more variables are missing in any term,expand that

term by multiplying it with the sum of each one of themissing

variable and its complement.
3 Drop out the redundant term
Another Method:-
1 Write down all the terms

2 Put Xs in terms where variables must be inserted to form a

minterm.
3 Replace the non -complemented variables by 1s and the
complemented variables by 0s ,and use all combinations of Xs in
terms of 0s and 1s to generate minterms.
4 Drop out all the redundant terms.
Example
Expand A + B to minterms andmaxterms.
The given expression is a two variable function.
In the first term A,the variable B is missing; so ,multiply it by
(B+B).
In the second term B,the variable A is missing ;so multiply it by
(A+A).
A +B
= A(B + B) +B(A +A)
= AB +A B +BA + B A
= AB +A B +AB + A B
= AB +A B + AB
= 01 + 00 +10
= m1 + m0 +m2
= Σm(0, 1, 2)
A standard SOP can always be converted to a standard POS form
By treating the missing minterms of the SOP form as the
maxterms of the POS form.
Similarly a standard POS form can be converted to a standard
SOP form ,
By treating the missing maxterms of the POS form as the
minterms of the corresponding SOP form.
Example

The minterm m3 is missing in the SOPform.

Therefore ,the maxterm M3 will be ppresent in the POS form.
Q
Hence the POS form is M3i.e A +B
Another method:-
A +B

= A.X +X.B
= 0X + X0
= 00 +01+00+10
= 00+01 +10
= Σ(0, 1, 2)
Expansion Of A Boolean Expression To POS Form

The expansion of a Boolean expression to the standard POS form is

conducted as follows:-
1 If one or more variable are missing in any sum term,expand

that term by adding the product of each of the missing ters

and its complement.
2 Drop out the redundant terms.
Another Method:-
1 Put Xs in terms whenever variables must be inserted to forma

maxterm.
2 Replace the complemented variables by 1s and the
non-complemented variables by 0s and use all combinations of
Xs in terms of 0s and 1s to generate maxterms.
3 Drop out the redundant terms.
Expansion Of A Boolean Expression To POS Form

Expand A(B+A)B to maxterms and minterms

The given expression is a two variable function in the POS
form .
Expansion Of A Boolean Expression To POS Form

Expand A(B+A)B to maxterms and minterms

The given expression is a two variable function in the POS
form .
The variable B is missing in the first term A.So add B B to it.
Expansion Of A Boolean Expression To POS Form

Expand A(B+A)B to maxterms and minterms

The given expression is a two variable function in the POS
form .
The variable B is missing in the first term A.So add B B to it. The
second term contains all the variables.So leave it as it is.
Expansion Of A Boolean Expression To POS Form

Expand A(B+A)B to maxterms and minterms

The given expression is a two variable function in the POS
form .
The variable B is missing in the first term A.So add B B to it. The
second term contains all the variables.So leave it as it is.
The variable A is missing in the third term B .So ,add AA to it.
 A = A+BB = (A +B)(A +B) B = B +
AA = (B +A)(B +A)

Duality rule 11 :-A+BC=(A+B)(A+C)

or

A(B + A)B = (A + B)(A +B)(A +B)(B +A)(B +A)

= (A +B)(A + B)(A + B)
= (00)(01)(10)
= M0.M1.M2
Y
= M(0, 1, 2)
The maxterm M3 is missing in POS form.So,the SOP form will
contain only minterm m3
Also,

A −→ 0X = (00)(01) = M0.M1
(A +B) −→ (01) = M1
B −→ X0 = (00)(10) = M0.M2
Therefore,
Y
A(A+ B)B = M(0, 1, 2)
Example:
Expand A(A+B)(A+B+C ) to maxterms andminterms
The given expression is a three variable function in POS form .
The variable B and C are missing in the first term A.
So, add BB and CC to it
The variable C is missing in secord term (A +B) So,
add CC to it.
The third term (A + B + C) contains all three variables.So, leave it as it
is.

A = BB + CC
= (A + B)(A + B) + CC
= (A + B + CC)(A +B + CC)
= (A + B + C)(A + B + C)(A + B + C)(A+ B + C)
Example:
Expand A(A+B)(A+B+C ) to maxtermsand minterms
the given expression is a three variable function in POS form.

A = A + BB + CC = (A + B)(A + B) + CC
= (A + B + CC)(A + B + CC)
= (A + B +C)(A+ B + C)(A + B + C)(A + B + C)
A+ B = A+ B + CC
= (A + B +C)(A+ B + C)
Example:
Expand A(A+B)(A+B+C ) to maxterms andminterms
the given expression is a three variable function in POS form.
the variable B and C are missing in the first term A.So, add BB and CC
to it.

A = A + BB + CC = (A + B)(A + B) + CC
= (A + B + CC)(A + B + CC)
= (A + B +C)(A+ B + C)(A + B + C)(A + B + C)
A+ B = A+ B + CC
= (A + B +C)(A+ B + C)
Example:
Expand A(A+B)(A+B+C ) to maxterms andminterms
the given expression is a three variable function in POS form.
the variable B and C are missing in the first term A.So, add BB and CC
to it.
The variable C is missing in the second term (A+B) .So add CC to it.

A = A + BB + CC = (A + B)(A + B) + CC
= (A + B + CC)(A + B + CC)
= (A + B +C)(A+ B + C)(A + B + C)(A + B + C)
A+ B = A+ B + CC
= (A + B +C)(A+ B + C)
Example:
Expand A(A+B)(A+B+C ) to maxterms andminterms
the given expression is a three variable function in POS form.
the variable B and C are missing in the first term A.So, add BB and CC
to it.
The variable C is missing in the second term (A+B) .So add CC to it. The
third term (A+B+C) contains all the three variables .So leave it as it is .

A = A + BB + CC = (A + B)(A + B) + CC
= (A + B + CC)(A + B + CC)
= (A + B +C)(A+ B + C)(A+ B + C)(A+ B + C)
A+ B = A+ B + CC
= (A + B +C)(A+ B + C)
Continued...
Therefore,

A(A + B)(A + B + C) = (A + B + C)(A + B + C)(A + B + C)(A + B + C) (A+ B + B + C)(A + B + C)

= (000)(001)(010)(011)(100)(101)
= M0.M1.M2.M3.M4.M5
Y
= M(0, 1, 2, 3, 4, 5)

The maxterms M6and M7 are missing in the POS form.

So,the SOP form will contain the minterms 6 and 7 .
Σ
Therefore ,the given expression in SOP form is m(6,7)
Continued.........

Also.

A −→ 0XX = (000)(001)(010(011)
= M0.M1.M2.M3
A+ B −→ = (100)(101) = M4.M5 A+ B
+C = 101 = M5

Therefore,
Q
A(A+B)(A+B+C)= M(0,1,2,3,4,5)
Two-variable K -Map

A two variable expression can have 22 = 4 possible

combinationsof the input variables A and B.
Each of these combinations ,AB,AB,AB and AB is called a
minterm.
They can be represented in decimal as m0,m1,m2,m3, letter m
stands for minterm.
The presence (absence ) of minterm in the expression indicates
that the output of the logic circuit asssumes a logic 1(logic 0)
level for that combination of input variables.
Consider the expression ,AB + AB + AB.It can be expressed
using minterms as
Σ
m0 + m +m1 =3 m(0, 2, 3)
and should be read as the sum of minterms 0,2 and 3.It can
also be represented in terms of a truth table .
Two-variable K -Map
Minterm Inputs Output
A B f
0 0 0 1
1 0 1 0
2 1 0 1
3 1 1 1
The first column indicates the minterm designated
The second column indicates the input combnations
The last column indicates the presence of that minterm in the
output expression .
A 1 in the output column indicates that the output contains
that particular minterms in its sum and 0 in that column
indictes that the particular minterm does not appear in the
expression for output.
Such information about the two-variable expression can also
be indicated by a two variable K-map.
Mapping Of SOP Expressions
A two variable K-Map has 22 = 4 squares.
These squares are called cells.
Each square on the K-map represents a unique minterm.
A 1 placed in any square indicates the corresponding minterm is
included in the output expression and a 0 or no entry in square
indicates that the corresponding minterm does not appear in
the expression for ouput.
Figure:Two-variable K-Map

B
0 1

0 AB AB

A
1 AB AB
Two-variable K-Map

Figure:Two-variable K-Map

B
0 1

0 1 0
A
1 1 1
Map the expression AB +AB

The given expression in minterms is

Σ
m1 +m2 = m(1, 2)
The K-map is shown below:
B
0 1

0 0 1
A
1 1 0
Minimization of SOP Expression

To minimize a Boolean expression given in the SOP form by

using the K-map
we have to look for adjacent squares having 1’s that is
,minterms adjacent to each other, and combine to form larger
squares to eliminate some variables .
two squares are said to be adjacent to each other ,if their
minterm differ in only one variable .
for e.g , in two variable K-map ,m0 and m1 i.e A B and AB differ
only in variable B.
so ,they may be combined to form a 2-square to eliminate the
variable B .
Minimization of SOP Expression

Similarly ,minterms m0(AB) and m2(AB);m1(AB) and

m3(AB);and m2(AB) and m3(AB) are adjacent to each other
However ,minterms m0(AB) and m3(AB) and m1(AB) and
m2(AB) are not adjacent to each other,because they differ in
more than one variable.
Two minterms which are adjacent to each other can be
combined to form a bigger square called a 2-square or a pair.
This eliminates one variable -the variable that is not common to
both the minterms.
For example:

m0 and m1 can be combined to yield,

f1 = m0 +m1 = A B +AB = A

Figure: f1 = A

B
0 1

0 1 1
A
1 0 0
For example:

m0 and m2 can be combined to yield,

f2 = m0 +m2 = A B +AB = B

Figure: f2 = B

B
0 1

0 1 0
A
1 1 0
For example:

m1 and m3 can be combined to yield,

f3 = m1 +m3 = AB + AB = B

Figure: f3 = B

B
0 1

0 0 1
A
1 0 1
For example:

m2 and m3 can be combined to yield,

f4 = m2 +m3 = AB + AB = A

Figure: f4 = A

B
0 1

0 0 0
A
1 1 1
For example:
m0 , m1, m2 and m3 can be combined to yield,

f5 = m0 + m1 + m2 + m3 = AB + AB + AB + AB
= A+A
=1

Figure: f5 = 1

B
0 1

0 1 1
A
1 1 1

A 4-square eliminates 2 variables.A 4-square is called a quad

Reduce the expression AB+AB+AB using mapping

Express in terms of minterms,the given expression is

m0 + m1 +m3
The diagram for K -map is
Figure: f = A +B B

0 1

0 1 1
A
1 1
A
f
= B
Mapping of POS Expression

Each sum term in the standard POS expression is called a

maxterm.
A function in two variables (A,B) has four possible maxterms,
A+B,A+B,A+B,A+B
They are represented as M0, M1, M2and M3 respectively.
Treats the non-complemented variable as a 0 and the
complement variable as a 1 and the complemented variable as
a 1.
For mapping a POS expression on to the K-map 0s are placed in
squares corresponding to the maxterms which are present in
the expression and 1s are placed in squares corresponding to
the maxterms which are not present in the expression.
Figure:The maxterm of a two -variable K-map

B
0 1

0 A+B A+B
A
1 A+B A+B
Plot the expression (A+B)(A+B)(A+B)on the K-map

Q
The given expression in terms of maxterms is M(0, 2, 3).
B
0 1

0 0 1
A
1 0 0
Minimization of POS Expressions

To obtain minimal expression in the POS form, map the given

expression ont to the K-map and combine the adjacent 0s into as
large square as possible .
Read the squares putting the complemented variable if its
value remains constant as 1 and the non-complemented
variable if its value remains constant as a 0 along the entire
square and then write them in sum term
Various maxterm combinations and the corresponding reduced
expression as shown in figure in next slides.
The possible maxterm groupings in a two -variable K-map

Figure: f1 = A B Figure: f3 = B B Figure: f5 = 0

0 1 0 1 B
0 1
0 0 0 0 0 1
0 0 0
1 1 1 1 0 1
A A A
1 0 0

Figure:f2 = B Figure:f4 =A

B B
0 1 0 1

0 1 0 0 1 1
A A
1 1 0 1 0 0
Reduce the expression (A+B)(A+B)(A+B) using mapping

Q
the given expression in terms of maxterms is M(0, 1, 3)
The diagram below shows the K-map and its reduction

Figure: f = AB

B
0 1
A
f
0 0 0 = B
A
1 1 0

In the given expression ,the maxterm M2 is absent.

This is indicated by a 1 on K-map.
Σ
The corresponding SOP expression is m2or AB.
This realization is the same as that for POS form.
Three -Variable K-MAP

A function in three variable (A,B,C)expressed in SOP form can

have eight possible combination.
A B C,A BC,ABC,ABC,AB C,ABC,ABC and ABC
Each one of these combinations designated by
m0, m1, m2, m3, m4, m5, m6 and m7 respectively is called
minterm.
A is the MBS of the minterm designator and C is the LSB.
Three -Variable K-MAP

In the POS form ,the eight possibel combinations

are:A+ B +C,A+ B + C, A+ B + C, A+B +C, A +B +
C, A + B +C, A+ B +C and A +B +C
Each of these combinations designated by
M0, M1, M2, M3, M4, M5, M6 and M7 respectively is called a
maxterm.
A is the MSB of the maxterm designator and C is the LSB.
A three -variable K-MAP has ,23 = 8 square or cells,each
square on the map represents a minterm or maxterm.
The minterm and maxterm of a three variable K-MAP

Figure:(a)Minterms Figure:(a)Maxterms

BC BC
00 01 11 10 00 01 11 10

0 ABC ABC ABC ABC 0 A+B+C A+B+C A+B+C A+B+C

A A
1 ABC ABC ABC ABC 1 A+B+C A+B+C A+B+C A+B+C
Map the expression ABC+ABC+ABC+ABC+ABC

BC
00 01 11 10

0
A
1
Map the expression ABC+ABC+ABC+ABC+ABC

BC
00 01 11 10

0 0 1 0 1
A
1 0 1 1 1
Map the expression (A+B+C)(A+B+C)(A+B+C)(A+B+C
)(A+B+C)

BC
00 01 11 10

0
A
1
Map the expression (A+B+C)(A+B+C)(A+B+C)(A+B+C
)(A+B+C)

BC
00 01 11 10

0 0 1 0 1
A
1 1 0 0 0
Minimization of SOP and POS Expression

For reducing the Boolean expression in SOP form plotted on

the K-MAP,look at the 1s present on the map.
These represent the minterms.
Look for the minterms present adjacent to each other,in order
to combine them into larger squares.
Combining of adjacent sqaures in K-map containg 1s for the
purpose of simplification of a SOP expression is called
LOOPING
Some of the minterms may have many adjacencies.Always start
with the minterms with the least numbers of adjacencies and
try to form a large square as possible.
The larger squares must form a geometric square or rectangle .
Minimization of SOP and POS Expression

They can be formed even by wrapping around,but cannot be

formed by using diagonal configurations.
Two squares are said to be adjacent to each other ,if they are
physically adjacent to each other or can be made adjacent to
each other by wrapping around.
Reading K-map
Some possible combinations of minterms in a three-variable
K-map(in SOP)
Reading the K-map

Some possible combinations of maxterms in the three-variable

K-map (in POS form)
 Σ
Reduce the expression m(0, 2, 3, 4, 5, 6) using mapping
BC
00 01 11 10

0 1 1 1
A
1 1 1 1
 Σ
Reduce the expression m(0, 2, 3, 4, 5, 6) using mapping
BC
00 01 11 10

0 1 1 1
A
1 1 1 1

f = C + AB +AB
 Q
Reduce the expression M(0, 1, 2, 3, 4, 7) using mapping
BC
00 01 11 10

0 0 0 0 0
A
1 0 0
 Q
Reduce the expression M(0, 1, 2, 3, 4, 7) using mapping
BC
00 01 11 10

0 0 0 0 0
A
1 0 0

f = (B +C)(B +C)(A)
 Σ
Obtain the minimal expression for m(1, 2, 4, 6, 7)
Four Variable K-map
A four variable (A,B,C,D)expression can have 24 = 16 possible combinations.

Figure:SOP form Figure:POS form

CD CD
00 01 11 10 00 01 11 10

00 00

01 01
AB AB
11 11

10 10
Four Variable K-map
A four variable (A,B,C,D)expression can have 24 = 16 possible combinations.
 Σ
Reduce using mapping the expression m(0, 1, 2, 3, 5, 7, 8, 9, 10, 12, 13)
CD
CD
00 01 11 10
00 01 11 10

00
00 1 1 1 1
01 0 0
01 1 1
AB
AB 11
0 0
11 1 1
10
0
10 1 1 1

Figure:
Figure: f = BD + AC +AD
f = (A+B +D)(A +C + D)(A +B +C)
 Q
Reduce using mapping the expression M(2, 8, 9, 10, 11, 12, 14)
CD
CD
00 01 11 10
00 01 11 10
00 0
00 1 1 1
01
AB 01 1 1 1 1
11 0 0 AB
11 1 1
10 0 0 0 0
10

f = (A+B)(A +D)(B +C +D)

Don’t Care Combinations
The expression seen till now have been completely specified
for every combination of the input variables,that is minterms
(maxterms )has been specified as a 1 or a 0.
It often occurs that for certain input combinations, the value
of the output is unspecified either because the input
combination are invalid or because the precise value of the
output is of no consequence.
The combinations for which the values of the expression are
not specified are called don’t care combinations and such
expressions ,therefore stand incompletely specifed.
The output is a don’t care for these individual combination .
For example in 8421 CODE the binary states
1001,1010,1011,1100,1101,1110,1111 are invalid and the
corresponding outputs are don’t cares.
The don’t care terms are denoted by d,X or φ
Don’t Care Combinations

During the process of design using an SOP map each don’t care
is treated as a1 if it is helpful in map reduction ,otherwise it is
treated as a 0 and left alone.
During the process of design of using a POS map,each don’t
care is treated as a 0 if it is useful in map reduction,otherwise it
is treatedd as a1 and left alone.
The SOP expression with don’t cares can be converted into
POS form by keeping the don’t cares as they are and writing
the missing mintermsof the SOP form as the maxterm of the
POS form .
Similarly ,to convert a POS expression with don’t cares into
SOP expression, keep the don’t cares of POS expression as
they are and write the missing maxterms of the POS
expression as the minterms of the SOP expression.
Don’t Care Combinations
Σ
Reduce the expression m(1, 5, 6, 12, 13, 14)+d(2, 4)
CD
00 01 11 10

00 1 X

01 X 1 1
AB
11 1 1 f = BC + DB+ ACD
1
10
Don’t Care Combinations

CD
00 01 11 10

00 0 0 X

01 X 0
AB
11 f = (B +D)(A +B)(C +D)
0
10 0 0 0 0
 COMBINATIONAL CIRCUITS
A combinational circuit is the digital logic circuit in which the output depends
on the combination of inputs.
Given the current inputs, one can analyse and say what the output must be.

HALF-ADDER
A combinational circuit that performs the addition of 2 bits is called a half
adder. Half-adder is used to add two bits. Therefore, half-adder has two inputs
and two outputs, with SUM and CARRY.
The Boolean expressions for SUM and CARRY are
SUM = AB’+A’B CARRY = AB These expressions shows`that, SUM output is
EX-OR gate and the CARRY output is AND gate. Figure shows the be
implementation of half-adder with all the combinations including the
implementation using NAND gates only.
Figure shows truth table of half adder:
FULL-ADDER
One that perform the addition of 3 bits (2 significant bit and a previous carry) is
a full adder.
Truth table of full adder:

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Figure of full adder:

MAGNITUDE COMPARATOR
Magnitude comparator is a combinational circuit that compare 2 digital or
binary number in order to find out whether one binary number is equal, less
than or greater than the other binary number. We logically design a circuit for
which we will have two inputs one for A and other for B and have three output
terminals, one for A > B condition, one for A = B condition and one for A < B
condition.
A A>B

N bit comparator A=B

B A<B

1-BIT COMPARATOR
A comparator used to compare two bits is called a single bit comparator. It
consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.
Truth table of 1 bit comparator:
A B A<B A=B A>B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

From the above truth table logical expressions for each output can be
expressed as follows:
A>B: AB'
A<B: A'B
A=B: A'B' + AB
From the above expressions we can derive the following formula:
(A<B)+(A>B) = A’B+AB’
Taking complement both sides
((A<B) + (A>B))’ = (A’B + AB’)
((A<B) + (A>B))’ = (A’B’) (AB’)
((A<B) + (A>B))’ = (A+B’) (A’+B)
((A<B) + (A>B))’ = (AA’ + AB + A’B’ + BB’)
((A<B) + (A>B))’ = (AB + A’B’)
Thus ((A<B) + (A>B))’ = (A=B)
By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below:

2-BIT COMPARATOR
A comparator used to compare two binary numbers each of two bits is called a
2-bit Magnitude comparator. It consists of four inputs and three outputs to
generate less than, equal to and greater than between two binary numbers.
The truth table for a 2-bit comparator is given below:
From the above truth table K-map for each output can be drawn as follows:
From the above K-maps logical expressions for each output can be expressed
as follows:

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below:

MULTIPLEXERS
It is a combinational circuit which have many data inputs and single output
depending on control or select inputs. Multiplexers are mainly used to increase
amount of the data that can be sent over the network within certain amount of time
and bandwidth.
2 INPUT MULTIPLEXER
In 2 input multiplexer, there are only 2 inputs. Block diagram and truth table
are given below:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4 INPUT MULTIPLEXER

In 4 input multiplexer, There is a total of 4 inputs.

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

Subject Digital:
Module 2:
Topic covered : Sequential circuits - flip flops: RS flip flop, D flip flop, JK, T flip flop (block
diagram, logic diagram, truth table, characteristics equation)

● 1. Introduction:
Switching circuits may be combinational switching circuits or sequential switching
circuits.
1. Combinational switching circuits are you so cute whose output levels at any
instant of time are depended only on the level present at the Inputs at that time
where Prior input level conditions have no effect on the process and output
because combinational logic circuits have no memory.
2. Whereas the sequential switching circuits are those whose output level at any
instant of time are depended not only on the level present at the inputs at that
time, but also on the pri or input level conditions.
It means that sequential switching circuits have memory and thus it is made up of combinational
circuits and memory elements. The most important memory element is the flip-flop which is
made up of an assembly of logic gates. Even though a logic GATE by itself has no storage
capability but several logic gates can be connected together in a way that permit information to
be stored.
A flip- flop (FF), also known as bistable multivibrator which has two stable States. It can
remain in either of the states indefinitely. Its state it can be charged by applying the proper
triggering signal. General flip flop symbol is shown below.

The flip-flop has two outputs labelled as Q and Q dash . The Q is the normal output and Q dash
is the inverted output as shown in above figure. The state of flip-flop always refers to the state of
normal output Q were as inverted output Q dash is in the opposite state. A flip flop is said to be
in HIGH state or logic 1 state or SET state when Q=1, and in LOW state or logic 0state or
RESET state or clear state when Q dash= 0. A flip-flop can have one or more inputs. These
inputs are used to cause the flip-flop to switch back (flip)and forth(flop) between its possible
output States. A flip-flop input has to be pulsed momentarily to cause a change in the flip-flop
output and the output will remain in that new state even after the input pulse has been removed.
This is called flip-flop's memory characteristic. A flip-flop serves as a storage device. It stores a
1 when it'sQ output is a 1, and stores a 0 when it's Q output is 0.
The term' latch' is used for certain flip-flops. It refers to non clocked flip flop, because these flip
flops 'latch on' to a 1 or a 0 immediately upon receiving the input pulse called SET or RESET.
Gate latches are latches which respond to the inputs and latch on to a 1 or 0 only when they are
enabled. In the absence of ENABLE or gating signal, the lach does not respond to the change in
its input.

● 2. The S-R latch :

The simplest type of flip flop is called an S-R latch . It has two outputs labelled as Q, Q dash
and two inputs labelled as S and R. The state of latch corresponds to the level of Q (ie. HIGH or
LOW or 1 or 0 ) and Q dash is the complement of that state. The output as well as it's
complement are available for each file flop.
Active HIGH S-R latch and it's truth table is shown below:

Q0 represents the state of the flip-flop before applying the inputs. The name of the latch S-R or
SET-RESET, is derived from the name of its inputs.
When the SET input is made HIGH, Q becomes 1 ( and Q dash becomes 0). When the RESET
input is made HIGH ,Q becomes 0 ( and Q dash becomes 1).
If both the inputs S and R are made LOW, there is no Change in the state of the latch .
If both the outputs are made HIGH , the output is unpredictable.
The S-R latch is also called R-S latch or S-C(SET-CLEAR) latch.

● 2.1 The NOR Gate S-R latch :

An S-R latch can be constructed using two cross coupled NORr gates or NAND gates. Using
two NOR gates, an active HIGH S-R latch can be constructed and using to navigate and active
low SR latch can be constructed.
Figure below shows the logic diagram of an active high SR latch composed of two cross
coupled NOR gates where the output of each gate is connected to one of the input of the other
gate.

1. Let us assume that the latches initially SET ,ie Q=1, Q dash =0. If the input are S=0 and
R=0, the inputs to G1 are 0 ( R ) and 0 ( Q dash)and so it's output is 1, ie. Q remains as
1. The input to G2 are 0( S) and 1(Q) and so it's output is 0,i e, Q dash remains as 0.
That is ,S=0 and R=0 do not result in a change of state.
Similarly v,if Q=0 and Q dash =1 initially and if S=0 and R=0 are the inputs applied ,the
inputs to G2 are 0(Q) and 0(S) and so it's output is a 1,i.e, Q dash remains as 1. The
input to G1 are 0(R ) and 1(Q dash) and so it's output is 0,i.e,Q remains as 0. This
implies the light remains in the same state, when S=0,R=0 is applied.
2. If Q=1 and Q dash =0 initially ,and if inputs S=1 and R=0 are applied ,the inputs to G2
are 1(S) and 1(Q )and so it's output is a 0 ,i.e, Q dash remains 0. The inputs to G1 are 0
(R ) and 0 ( Q dash) and so it's output is a 1,i.e. Q remains as 1. If Q=0 and Q dash =1
initially and if inputs S= 1 and R =0are applied ,the inputs to G2 are 1( S) and 0 (Q) and
so it's output is a 0 ,i.e Q dash goes to 0. The inputs to G2 are 0 (R ) and 0 ( Qdash)
,and so it's output is 1,i.e Q goes to 1. This implies that irrespective of the present state,
the output of S-R latch goes to SET state,i.e state 1 after application of the input, S=1
and R=0.
3. IfQ=1 and Q dash=0 initially,and if inputs S=0,R=1 are applied the inputs to G1 are 1 ( R)
and 0 ( Q dash) and so it's output is 0 ,i.e Q goes to 0. The inputs to G2 are 0 (S) and
0(Q) ,and so it's output is 1,IE.Q dash goes to 1. If Q=0 and Q dash =1 initially, and if
inputs S=0 and R =1 are applied, the inputs to G1 are 1 (R ) and 1( Q dash) ,and so the
output of G1 is 0,i.e Q remains as 0. The inputs to G2 are 0 (S) and 0(Q dash) ,and so
the output of G2 is 1,i.e Q dash remains as 1. This implies that whatever may be it's
present state, when S=0,R=1 are applied the flip flop first to RESET state ,i.e state 0.
4. When both the inputs S and R are 1 ,the corresponding outputs will be Q=0 and Q
dash=0, which is invalid.

● 2.2. The NAND Gate S-R latch :

An active - LOW S-R latch can be constructed using two cross- coupled NAND gates.
Since the NAND Gate is equivalent to an active -LOW OR gate , an active- LOW S-R using OR
gates is represented as well as the logic diagram and truth table of an active- LOW S-R latch
are represented below.

An active - LOW NAND latch can be converted into an active- HIGH NANAD latch by inserting
the inverters at the S and R inputs . Logic diagram and truth table of an active- HIGH NANAD
latch is represented below.

● 3. GRATED LATCHES :

● 3.1 The Gated S- R latch :

Output can change state anytime the input conditions are changed. This type of latches are
called as asynchronous latches. A gated S-R large requires an ENABLE (EN) input. Its S and
R inputs will control the state of flip-flop only when the ENABLE is HIGH. When the ENABLE is
LOW , the inputs become ineffective and no change of state can take place. The ENABLE input
may be a clock. So a gated SR latch is called clocked SR latch orr synchronous SR latch. Since
this type of flip-flop response to the changes in inputs only as long as the clock is HIGH, this
type of flip-flops are also called level triggered flip flops. The logic diagram the logic symbol
and the truth table for the gated SR latch are shown below in which the invalid state occurs
when both S and R are simultaneously HIGH .
 ● 3.2 The Gated D - latch :

It is not necessary to have separate S and R inputs to a latch if the input combinations S= R=0
and S=R=1 are never needed, the S and R are always the complement of each other. So we
can construct a latch with a single input (S) and obtain the R input by inverting it. This single
input is labelled as D (for data) and the device is called a D- latch . Show another type of gated
latch is the gated D latch. It differs from the SR latch in that it has only one input in addition to
EN . When D= 1, we have S=1 and R=0, causing the latch to SET when ENABLED. When D=0,
we have S=0 and R=1, causing the latch to RESET when ENABLED . When EN is LOW, the
latch is ineffective. The logic diagram , the logic symbol and the truth table of the gated D latch
is shown below.

● 4. EDGE- TRIGGERED FLIP- FLOPS :

Digital system can operate either synchronously or asynchronouorly. In asynchronous

system, the outputs of logic circuits can change state any time when one or more of the input
change. An asynchronous system is difficult to design and troubleshoot. In synchronous
system, the exact times at which any output can change states are determined by a signal
commonly called the clock. The flip flops using the clock signal are called the clocked flip
flops. Control signals are effective only if they are applied in synchronous with the clock signal.
The clock signal is distributed to all parts of the system and most of the system outputs can
change state only when the clock make a transition. Clocked flip flops maybe positive edge
triggered on negative edge triggered. Positive edge triggered flip flops are those in which
state transactions take place only at the positive going ( 0- 1,or LOW - HIGH) ads of clock pulse
and negative edge triggered flip flops are those in which state transaction takes place only at
the negative going (1-0, or HIGH - LOW) edge of clock signal. Positive edge triggered is
indicated by a triangle at the clock terminal of the flip-flop. Negative edge triggered is indicated
by a triangle with a bubble at the clock terminal of the flip-flop. 10 major triggered flip flops are
sensitive to their inputs only at the transition of the clock. There are three basic types of edge
triggered flip flops:
1. S-R flip flop
2. J-K flip flop
3. D flip flop.
the edge triggering is also called as dynamic triggering.

● Generation of Narrow Spikes :

anaro positive spike is generated at the rising edge of the clock using an inverter and an AND
Gate . The inverter produce a delay of a few nanoseconds (NS) . The AND gate produces an
output spike that is HIGH only for a few NS, when CLK and CLK dash are both HIGH. This
results in a narrow pulse at the output of AND gate which occurs at the positive going transition
of the clock signal. Similarly a narrow positive spike is generated at the falling edge of the clock
by using an inverter and an active - LOW AND gate as shown below.

● 4.1. The Edge - triggered S-R Flip flop :

The S and R are inputs of SR flip flop are synchronous control inputs because data on which
input affect the flip flops output only on the triggering edge of the clock pulse.
1. When S is HIGH and R is LOW ,the Q outputs goes HIGH on the positive going edge of
the clock pulse and flip flop is SET. (if it is already in SET state it remains SET).
2. When S is LOW and R is HIGH,the Q output goes LOW on the positive going edge of
clock pulse and flip flop is RESET that is cleared. (if it is already in RESET state,it
remains RESET).
3. When both S and R are LOW ,the output does not change from its prior state.
Similarly , negative edge triggered SR flip-flop triggers only when the clock input goes negative
i.e 1-0 as shown below.

Simplified circuit of the edge triggered SR flip flop:

It contains three sections they are as:

1. A basic NAND gate latch formed by NAND gates( active -LOW OR gate) G3amd G4.
2. A pulse steering circuit formed by NAND gates G1 and G2.
3. An edge(pulse transition) detector circuits.
The edge detector generates a positive spike at the positive going or negative going edge of
the clock pulse. The steering gates ' direct' or ' steer' the narrow spikes either to G3 and G4
depending on the state of S and R inputs.
 ● 4.2 The Edge - Triggered D Flip flop :

D flip flop has only one input terminal. The D flip flop may be obtained from a SR flip flop by
just putting one inverter between the S and R terminals. The the flip-flop has only one
synchronous control input in addition to the clock. This is called the D( data) input. The level
present at D will be stored in the flip flop at the instant of positive going transition occurs.i.e , if D
is a 1 and the clock is applied, Q goes to a 1and Q dash to a 0 at the rising edge of the pulse. If
D is 0 and the clock is applied, Q goes to 0 and Q dash to a 1 at the rising edge of the clock
pulse and thereafter remain so.

The negative edge triggered D flip flop operates in the same way as a positive edge triggered D
flip flop except that the change of state takes place at the negative going edge of the clock pulse
as shown below.

● 4.3 The Edge- triggered J-K Flip flop :

The functioning of JK flip flop is identical to that of the SR flip flop except that it has no invalid
state. The logic symbol and the truth table for the positive edge triggered JK flip flop as shown
below.

The logic symbol and truth table of the negative edge triggered JK a flip flop is shown below are
shown below.

Simplified circuit diagram of edge triggered JK flip flop.

 ● 4.4. The Edge Triggered T flip flop :

A T flip flop has a single control input labelled T for toggle.

1. When T is high the flip flop toggles on every new clock pulse.
2. When T is low the flip-flop remains in whatever state it was before.
3. It is easy to convert a JK flip flop to a functional equivalent of the T flip flop by just
connecting J and K together and labelling the common connection as T.
The logic symbol and truth table of Edge Triggered T flip flop are as .
SHIFT REGISTER
Introduction:
● Data may be available in parallel form or in serial form
❖ Parallel form: when multi-bit data are available simultaneously.
❖ Serial form: when the data bit appears sequentially (one after the
other) at a single terminal.
● Data may also be transfered in parallel form or in serial form
❖ Parallel data transfer : simultaneous transmission of all bits of
data from one device to another
❖ Serial data transfer: transmission of one bit of data at a time
form one device to another.
Serial data must be transmitted under the synchronization of the clock
(since the clock provides the mean to specify the time at which each new
bit is sampled)

• flip-flops(FF) can store only one bit of data(0 or 1), it is referred to as

single bit register.
When more bits of data are to be stored, number of flip-flops is used.

• Register: it is a set of FFs used to store binary data.

Storage capacity of register is the number of bits (0s & 1s) of digital
data it can retain.

• Loading a register: setting / resetting the individual FFs.

• Loading may be serial or parallel.

 ❖ Serial loading: data is transferred into the register in serial form
(one bit at a time).
❖ Parallel loading: data is transferred into the register in parallel
form (all FFs are triggered into their new states at the same time).
● Register may output data either in serial form or in parallel form.
❖ Serial output: data is transferred out of the register, one bit at a
time serially.
❖ Parallel output: entire data stored in register is available in parallel
form, and can be transferred out at the same time.
Shift register:
▪ Used basically for the storage and transfer of digital data.
▪ Shift register are a type of logic circuits closely related to counters.
(Main difference between shift registers and counters are,
shift register has no specified sequence of states,
whereas a counter has a specified sequence of states )
▪ Shift register is a very important digital building block

Data transmission in shift register

❖ A number of flip flops connected together such that data may be
shifted into and shifted out of them is called a Shift register.
❖ Data may be shifted into or out of the register either in serial form
or in parallel form.
❖ There are 4 basic types of shift register:
1. Serial in , serial out
 2. Serial in, parallel out
3. Parallel in, serial out
4. Parallel in, parallel out

1. Serial in , serial out:

● Accept data : serially
● Outputs data: serially

● Logic diagram of a 4-bit serial-in, serial-out shift register is

explained in 4 stages,
❑ i.e. 4 FFs, stores 4 bits of data.
❑ Q output of 1st FF is connected with to D input of the 2nd
FF, so on.
❑ When serial data is transferred into a register, each new bit is
clocked into the 1st FF at +ve going edge of each clock pulse.
❑ The bit that was previously stored by the first FF is
transferred to second FF and so on.
❑ Bit stored by the last FF is shifted out.

Process to store data bits 0101 in register. Initially Q1,Q2,Q3,Q4=0

Fig.9.5

Explanation:
Serial in, serial out (implementation with S-R and J-K FF):

2. Serial in, parallel out:

 ● In this type of register, data bit are entered into the register
serially, but the data stored in register is shifted out in parallel
form.
● Once the data bits are stored, each bit appears on its respective
output line and all bits are available simultaneously

3. Parallel in, serial out:

● In this, the data bits are entered simultaneously into their

respective stages on parallel lines.
But the data bits are transferred out of the register serially.

Explanation:
● There are four data lines A, B, C and D through which the data is
entered into the register in parallel form.
● The signal Shift/Load allows
a. The data to be entered in parallel form into the register.
b. The data to be shifted out serially from terminal Q4.

● When Shift/Load line is HIGH, gates G1, G2 and G3 are disabled, but
gates G4, G5 and G6 are enabled allowing the data bits to shift -right
from one stage to the next.

● When Shift/Load line is Low gates G4, G5 and G6 are disabled,

whereas gates G1, G2 and G3 are enabled allowing the data input to
appear at D inputs of the respective FFs.

● When a clock pulse is applied, these data bits are shifted to the Q
output terminals of FFs and therefore, data is inputted in one step.

● The OR gate allows either the normal shifting operation or the

parallel data entry depending on which AND gate are enabled by the
level on SHIFT /LOAD input.

4. Parallel in, parallel out:

● In this data is entered into the register in parallel form, and also
the data is taken out of the register in parallel form.
● Immediately following the simultaneous entry of all data bits, the
bits appear on the parallel outputs
Bidirectional shift register:
● Bidirectional shift register is one in which the data bits can be
shifted from left to right / from right to left.
Explanation:
● Fig.9.18 shows the logic diagram of the 4-bit serial-in, serial-out,
bidirectional shift register.

● Right/Left is the mode signal.

● When Right/Left is a 1, the logic circuit works as a shift -right shift

register.
● When Right/Left is a 0, it works as a shift-left shift register.
● The bidirectional operation is achieved by using the mode signal and
two AND gates and one OR gate for each stage as shown in figure.
● A HIGH on the Right/Left control input:
➢ Enables the AND gates G1,G2,G3 and G4 and
➢ Disables the AND gates G5,G6,G7 and G8 ,and
➢ The state of Q output of each FF is passed through the gate to
D input of the following FF.

● When a clock pulse occurs, the data bits are then effectively shifted
one place to the right.
● A LOW on the Right/Left control input :
➢ Enables the AND gates G5,G6,G7 and G8 and
➢ Disables the AND gates G1,G2,G3 and G4 and
➢ The Q output of FF is passed to the D input of the preceding
FF.
● When a clock pulse occurs, the data bits are then effectively shifted
one place to the left.

● Hence the circuit works as a bidirectional shift register.

Previous year questions:
2017
1. Define shift register [ 3 marks ]
2. (a). With neat diagram, explain shift register. [9 marks]
or
(b). Briefly discuss in detail about(i). Register (ii). Counter
Module 3
Basic structure of computer
Types of computers
A computer can be defined as a fast electronic calculating machine
that accepts the (data) digitized input information process it as per
the list of internally stored instructions and produces the resulting
information.
List of instructions is called program.
The internal storage is a called computer memory.
Computers differ widely in size, cost, computational power
and intended use.
Personal Computer

• widely used in homes, schools and business office

• common is desktop computers
• they have storage unit, visual display, audio output units
and a keyboard.
• Storage media: - hard disk, CD-ROMS and diskettes.
Workstations

• Have high -resolution graphics input/output capability

• Have more computational power than personal
computers.
• Used in engineering applications for interactive design
work.
Some other large and powerful computer systems are:
Enterprise systems(mainframes)
 • Used for business data processing from medium to large
corporations that require more computational powers.

Supercomputers

• Used for large scale numerical calculations.

• example like: weather forecasting, aircraft design and
simulation
• These systems communicate with each other through
Internet with a mechanism called as request and
response.

Functional units

Computer consists of 5 functionally independent main parts: -

1. input
2. memory
3. arithmetic and logic unit
4. output units
5. control units

Input Unit

• Computers accepts coded information through input units.

Example: keyboard
• When a key is pressed, the corresponding letter or digit is
translated into corresponding binary code
• and transmitted over a cable to either the memory or the
processor.
• Other input devices are: -joystick, trackball and mouses.

Output Unit

• Counterpart of input unit

• Function is to send processed result to outside world
Example: printer

Memory Unit

• Function is to store programs and data

• Two classes of storage
• Primary
• Secondary
Primary storage

• fast memory, operates at electronic speed.

• Program must be stored in memory while they are being executed.
• Memory contains a large number of semiconductor storage cells,
each capable of storing one bit of information
• These are not read individually, but as groups of fixed size called
words.
• Organized so that contents of one word, containing n bits, can be
stored or retrieved in one basic operation.
• A distinct address is associated with each word location.
• Address: - means numbers, that identify successive locations.
• to access a word: - specify its address and issue a control
• command that starts the storage or retrieval process.
• number of bits in each word: -word length of the computer
• Word length ranges from 16 to 64 bits.
• Programs must reside in memory during execution.
• Memory in which any location can be reached in short and fixed
amount of time after specifying its address is called random -
access memory (RAM)
• The time required to access one word is called the memory access
time.
• Memory of computer implemented as memory hierarchy
• Hierarchy of 3 or 4 levels of semiconductor RAM units (each of
different speeds and sizes.)
• Small fast RAM units are called caches.
• Largest and slowest unit is referred to as main memory.

Secondary storage

• Are cheaper than primary memory

• used when large amount of data and many programs have to be
stored and accessed infrequently
• example: magnetic tapes and disks, CD-ROMs.

Arithmetic and Logic Unit (ALU)

• Computer operations are executed in ALU

• Example: To add 2 numbers.: -locate in memory where they are
stored and then they are brought into processor and addition is
carried out.Sum is stored in memory /or retained by processor for
immediate use.
• Same is the process for multiplication, division etc
• When operands are brought into processor, they are stored in
highspeed storage element called register.
 Control Unit

• Coordination of the units is the amin job of control unit

• Acts as server centre: -sends signals to other units and
• senses their states.
• Generates timing signals: -responsible for data transfer
coordination between processor and the memory
• Also coordinates I/O transfer by timing signal

Performance

• The most important measure of the performance of a computer is

how quickly it can execute programs.
• The speed with which a computer executes program is affected
by the design of its hardware.
• For best performance, it is necessary to design the compilers, the
machine instruction set, and the hardware in a coordinated way.
• The total time required to execute the program is Elapsed time,
which is a measure of the performance of the entire computer
system.

Memory Location and Addresses

let’s consider how memory is organized: -

• contains millions of storage cells
• each stores a bit of information (0 or 1)
• 1 bit is a small information and seldom handled individually
• usually, we deal with a group of n bits to store or retrieve in a
single basic operation
• Group of n bit= a word of information
• n=word length
• Memory is schematically represented as collection of words.
 • Modern computers = word length 16 to 64 bits
• For example: -word length of computer=32 bits, single word can
store 32 bits (either in 2’s complement number or 4 ASCII
characters)
• A unit of 8 bits =1 byte.
• Accessing the memory (to store /to retrieve) a single item of
information (either a byte or a word), needs district names or
addresses for each item location.
• To name addresses: -use numbers from 0 through 2^k − 1,
k=some value, as successive locations in memory.
• 2^k addresses =address space of computer.

Byte Addressability
We look at 3 new terms
• the bit
• the byte:8 bits
• the word: ranges from 16 to 64 bit
• Impractical: -assign individual address to each bit in memory.
• Practical Solution: -successive address refers to successive byte
locations in the memory.
• Byte-addressable memory is used for this assignment.
• Byte locations have address 0, 1, 2, ...... thus, if the word length
of the machine is 32-bits, locations are located 0, 4, 8, .....
consisting four bytes.
Memory Operations:

• To execute an instruction
➢ The processor control circuits must cause the word containing the instruction to
be transferred from memory to the processor
➢ Operands and results must be moved between the memory and the processor.
• Two basic operations involving the memory are needed
• Load(or Read or Fetch)
• Store (or Write)
• Load operation:
➢ Transfer a copy of content of a specific memory location to the processor register.
➢ Address need to be specified – Load
➢ Memory content remains unchanged. Load operation is performed as follows:-
1. The processor sends the address of the desired location to the memory and
requests that its contents be read.
2. The memory reads the data stored at that address and sends them to the
processor.

• Store operation:
➢ Transfer an item of information from processor to a specific memory location,
destroying the former contents of that location.
➢ Overwrite the content in memory.
➢ Address and Data need to be specified - Store
➢ The processor sends the address of the desired location to the memory, together
with the data to be written into location.

Instructions and Instruction Sequencing

Task carried out by a computer program consists of a sequence of small steps

A computer must have instructions capable of performing 4 types of operation:-
➢ Data transfer between the memory and the processor registers
➢ Arithmetic and logic operations on data
➢ Program sequencing and control.
➢ I/O transfers
Instructions and Instruction Sequencing: Notations

Register Transfer Notation

• Transfer of information from one location in the computer to another.
• Possible location involved in transfer are
➢ memory locations
➢ processor register
➢ Registers in the I/ O subsystem.
• Location is identified by symbolic name standing for its hardware binary address.
• names of addresses of memory locations may be LOC,PLACE,A,VAR2
• Processor register may be R0, R5.
• I/O register names may be DATAIN, OUTSTATUS and so on.
• Contents of a location are denoted by placing square brackets around the name of the
location.
R1 − [LOC]
Means that contents of memory location LOC are transferred into
Processor registers.

Another example:
Consider the operation that adds the contents of register R1 and R2 and then places their sum
into R3.

R3 −[R1]+[R2]
This type of notation is known as Register Transfer Notation (RTN)

Assembly Language Notation

Another Type:-
• represent machine instructions and programs
• called assembly language format
• Transfer from memory location LOC to processor register R1

Memory location(LOC)=)Processor (R1)

MOV LOC,R1
• Contents of LOC are unchanged by execution of the statement
• Old contents of R1 are overwritten
Add R1, R2, R3
• add 2 numbers in processor registerR1 and R2
• place the sum in R3
•

Basic Instruction Type

• Consider a high level language statement to add 2 numbers
C=A+B
 • When compiled,
▪ 3 variables A,B and C are assigned to distinct locations in memory
▪ The above high level language statement requires action
C <−[A]+[B]

to take place in computer.

▪ Steps are as follows:-
➢ Fetch A and B from memory location
➢ Transfer it to processor and sum is computed
➢ Result sent back to memory and stored in C.

Add A,B,C
• Operands A and B are called source operands and C is destination operands.
• Add is the operation to be performed on operands.
Storage In Memory of the Above Instruction
• Suppose each operand needs k bits
• Above instruction has 3 operands ,so 3k bits are needed
• Add is denoted by additional bits.
• The modern 32 bit address space of computer ,3 address instruction is too large to fit in 1
word(32 bit)
• Therefore, we need multiple words to be used for single instruction.

Another approach for the previous the instruction in previous slide:-

• use sequence of simple instructions to erform same task
• each instruction having only 1 or 2 operands.
• Use 2-address instructions of the form
Operation Source, Destination
Example:
Add A,B
B <−[A]+[B]
• Sum is calculated ,send to memory and stored in location B
• Above operation replaces the content of location B
• Disadvantage :B’s contents are destroyed

Solution for the above problem is :-

• Use an instruction that copies the contents
Move B,C
performs the operation
C <− [B]
leaves the contents of B unchanged.
Move B,C Add A,C
• Source operands are specified first ,followed by destination
Another Problem:
• Two address instructions will not normally fit into one word.
 • we move on to one-address instruction
Add A
• Second operand is understood implicitly to be a unique location ,processor register
called as accumulator
• Thus the instruction means add the contents of memory location A to contents of the
accumulator register and place the sum back into the accumulator

Some examples of one -address instruction are:-

• Load A:copies the contents of memory location A into accumulator
• Store A: copies the contents of accumulator into memory location A.
C <− [A]+[B]
• the above instruction can be rewritten as
Load A
Add B
Store C

• Early computers had only single accumulator

• Modern computers have many general purpose registers( 8 to 32)
• Advantage: Access to data in these registers is faster than memory locations
• Number of registers are small ,only few bits needed to specify which register takes part in
operation.
• 32 register can be addressed by only 5 bit (25 = 32)

Let Ri represents a general purpose register.

Load A, Ri
Store Ri, A
Add A, Ri
are generations of Load ,Store and Add instructions.

Instruction Execution and Straight -Line Sequencing

• Consider the instruction
C <−[A]+[B]
for illustration
• Assumptions:-
➢ Computer allows only one memory operand per instruction
➢ Has number of processor registers
➢ Word length=32 bits
➢ Memory = byte addressable
➢ 3 instructions of a program are stored at successive locations, starts at i location
➢ each instruction=4 bytes long
➢ 2nd instruction=i+4
➢ 3rd instruction=i+8
How a program is executed?
• Processor contains a register called the Program Counter(PC)
➢ It holds the instruction to be executed next
• To begin execution:-
➢ the address of its first instruction must be placed into PC
➢ Processor control circuit use the information in PC to fetch and execute instruction
one at a time, in order of increasing addresses. This is called as straight line
sequencing
➢ During the execution of each instruction: PC is incremented by4 to point to next
instruction.
➢ After the move instruction at location i+8 is executed, the PC contains the value
i+12 which is the address of the first instruction of the next program segment.

• Executing an instruction is a 2 phase procedure.

➢ 1stPhase :Instruction Fetch (instruction is fetched from memory whose address is
in PC).Instruction is placed in instruction register(IR) in processor
➢ 2ndPhase :Instruction Execute(instruction in IR is examined to determine which
operation to perform, corresponding operation is performed by processor like:- )
✓ Fetching operands from memory/processor register
✓ perform arithematic or logic operation
✓ storing the result in the destination location.
➢ At some point during this phase contents of PC are advanced to point to next
instruction.

Branching
• Task: add a list of n numbers
• Address of memory location containing n numbers :NUM1,NUM2,NUM3......NUMn
 • Add instruction: add each number to contents of register R0
• Result after addition placed in R0

Figure: A straight line program of adding n numbers

Improvement on the above scenario:-
• Place Add instruction in a program loop
• Loop: sequence of instructions executed as many times as needed.
• starts at location LOOP and ends at the instruction Branch>0
• During each pass through this loop ,the address of the next list entry is determined and
that entry is fetched and added to R0
• Number of entries in the list =n
• Stored in location=N

• Register R1 is used as a counter

➢ to determine number of times the loop is executed
• Contents of location N loaded to register R1 at beginning
• Decrement R1:reduces the contents of R1 by 1 each time through the loop
• Execution of the loop is repeated as long as the result of the decrement >0.
• Branch instruction: loads a new value into the program counter. As a result the processor
fetches and executes the instruction at this new address called the branch target.
• Conditional branch: causes a branch only if the specified condition is satisfied
 Figure: Using a loop to add n numbers

Condition Codes

• The processor keeps track of information of result of various operations for use by
subsequent conditional branch instruction.
• The information is recorded in individual bits called conditional code flag
• Flag are grouped in special processor register called condition code register or status
register

Commonly used flag are:-

N (negative):
• Set to 1 if
➢ Result is negative otherwise cleared to 0.
➢ Result of an arithmetic or logic operation is negative or zero.
➢ also effected by instructions that transfer data such as
Move, Load or Store
➢ also used in conditional branch instruction

Commonly used flag are:-

Z (zero):
• Set to 1 if
➢ Result is 0.
➢ Result of an arithmetic or logic operation is negative or zero.
➢ also effected by instructions that transfer data such as
Move, Load or Store
➢ I also used in conditional branch instruction
Commonly used flag are:-
V (overflow):
• Set to 1 if
➢ Arithmetic overflow occurs otherwise set to 0.
C (carry):
• Set to 1 if
➢ If a carry -out results from operation otherwise cleared to 0.

Generating Memory Addresses

• In the Loop to add numbers, the block must refer to different address during each pass.
• Memory address cannot be given directly in a single Add instruction in the loop.
Otherwise it would be need to be modified on each pass through the loop.
• Only possibility: a processor register Ri is used to hold memory address of an operand
and incremented by 4 at each pass.

Addressing Modes
• Computer programs are written in high level language
• High level language has constants, local and global variables, pointers and arrays
 • When this High level language is translated into assembly language compiler must
implement elements of high level language using facilities provided in the instruction set
of computer.
Definition
The different ways in which the location of an operand is specifiedin an instruction are referred
to as Addressing Modes

Implementation of Variables and Constants

• Variables and Constants are the simplest data types
• In assembly language variables are represented using either register or memory location
• Thus the two modes of representation are:-
➢ Register Mode: operand is contents of a processor register and name of the register
is given in the instruction
➢ Absolute/Direct mode: operand is in a memory location, address of this location is
given explicitly in the instruction.

Implementation of Variables and Constants: Examples

Move LOC,R2
Uses these two modes.
• Processor registers are used as temporary storage locations where the data in a register
are accessed using the Register mode.
• The Absolute mode can represent global variables in a program.

A declaration:-
Integer A, B;
• In a high-level language program will cause the compiler to allocate a memory location
to each of the variables A and B.
• Whenever they are referenced later in the program, the compiler can generate assembly
language instructions that use the Absolute mode to access these variables.

Implementation of Constants
Address and data constants can be represented in assembly language using the immediate mode.
Definition
Immediate mode - The operand is given explicitly in the instruction.
For example, the instruction
Move 200 immediate, RO places the value 200 in register RO.

A common convention is to use the sharp sign (#) in front of the value to indicate that this value
is to be used as an immediate operand.

Hence, we write the instruction above in the form

Move #200, RO
Example:
A=B+6
In high level language is complied as follows
Move B, R1
Add #6, R1
Move R1, A

Indirection and Pointers

• In this addressing mode, the instruction does not give the operand or its address
explicitly.
• Instead, it provides information from which the memory address of the operand can be
determined.
• We refer to this address as the effective address (EA) of the operand.
Definition
Indirect mode - The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction.

We denote indirection by placing the name of the register or the memory address given in the
instruction in parentheses.

Indexing And Arrays

• Useful in dealing with lists and arrays.
• Index mode - The effective address of the operand is generated by adding a constant
value to the contents of a register.
➢ Register:-special register for this purpose or general purpose registers in the
processor.
➢ here it is called index register
➢ Notation:-X(Ri)
 ➢ X :-constant value ,Ri: name of the register involved.
➢ Effective address of an operand is:- EA=X+[Ri]

Base with Index Mode

• Another version of the Index mode uses 2 registers which can be denoted as (Ri, Rj)
• Here, a second register may be used to contain the offset X.
• The second register is usually called the base register.
• The effective-address of the operand is given by EA=[Ri]+[Rj]
• This form of indexed addressing provides more flexibility in accessing operands because
both components of the effective-address can be changed.

Base with Index & Offset Mode

• Another version of the Index mode uses 2 registers plus a constant, which can be denoted
as X(Ri, Rj)
• The effective-address of the operand is given by
EA=X+[Ri]+[Rj]
• This added flexibility is useful in accessing multiple components inside each item in a
record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing-
mode.
• In other words, this mode implements a 3-dimensional array.

Base with Index & Offset Mode

 • Another version of the Index mode uses 2 registers plus a constant, which can be denoted
as X(Ri, Rj)
• The effective-address of the operand is given by
EA=X+[Ri]+[Rj]
• This added flexibility is useful in accessing multiple components inside each item in a
record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing-
mode.
• In other words, this mode implements a 3-dimensional array.

Relative Addressing
• The Index mode defined using general-purpose processor registers.
• If the program counters, PC, is used instead of a general purpose register.
• Then, X(PC) can be used to address a memory location that is X bytes away from the
location presently pointed to by the program counter.
• Since the addressed location is identified ”relative” to the program counter, the name
Relative mode is associated with this type of addressing.
Definition
Relative mode - The effective address is determined by the Index mode using the program
counter in place of the general-purpose register Ri.

Additional Modes
• Modes are useful for accessing data items in successive locations.
➢ Auto increment mode:-The effective address of an operand is the contents of a
register specified in the instruction.
➢ After accessing the operands, the contents of this register are automatically
incremented to point to next item in a list.
➢ Notation:(Ri)+
➢ the increment amount is 1 implicitly
➢ but in byte addressable memory with 32bit word length ,increment must be 4.

• Modes are useful for accessing data items in successive locations.

➢ Auto decrement mode:-The contents of a register specified in the instruction are
first automatically decremented and are then used as the effective address of the
operand.
➢ Notation:¯(Ri)

Figure: Auto increment addressing mode used in program

Basic Input/Output operations
I/O implementation

Tremendous speed difference between CPU & I/O devices.

• Program controlled I/O
• Memory mapped I/O
• Interrupt driven I/O
• DMA
I/O devices connected to processor through “device interfaces” which consist of
buffer register and status control flag.
Input devices : DATAIN & SIN
Output devices : DATAOUT & SOUT
Input devices stores a new character code in DATAIN and informs CPU by setting
SIN to 1. CPU reads it and SIN automatically cleared to 0.
When output device is ready to display, it set SOUT to 1. CPU transfers a character
to DATAOUT and SOUT automatically sets to 0.
• Program controlled I/O , in which the processor repeatedly checks a status
flag to achieve the required synchronization between the processor and I/O
device.
We says that processor polls the devices.
READWAIT Branch to READWAIT if SIN=0
Input from DATAIN to R1
• Memory mapped I/O
Device and memory shar a common address space.
I/O operations looks just like memory read/write. No special commands for
I/O.
With memory-mapped I/O , any machine instructions that can access
memory can be used to transfer data to or from an I/O device.
MoveByte DATAIN, R1
MoveByte R1, DATAOUT
Addition of two Signed Binary Numbers
Consider the two signed binary numbers A & B, which are represented in
2’s complement form. We can perform the addition of these two numbers,
which is similar to the addition of two unsigned binary numbers. But, if the
resultant sum contains carry out from sign bit, then discard ignore

it in order to get the correct value.

If resultant sum is positive, you can find the magnitude of it directly. But, if
the resultant sum is negative, then take 2’s complement of it in order to get
the magnitude.

Example 1

Let us perform the addition of two decimal numbers +7 and +4 using 2’s
complement method.

The 2’s complement representations of +7 and +4 with 5 bits each are

shown below.

+710 = 001112

+410 = 001002

The addition of these two numbers is

+710 ++410 = 001112+001002

⇒+710 ++410 = 010112.

The resultant sum contains 5 bits. So, there is no carry out from sign bit.
The sign bit ‘0’ indicates that the resultant sum is positive. So, the
magnitude of sum is 11 in decimal number system. Therefore, addition of
two positive numbers will give another positive number.
Example 2

Let us perform the addition of two decimal numbers -7 and -4 using 2’s
complement method.

The 2’s complement representation of -7 and -4 with 5 bits each are

shown below.

−710 = 110012

−410 = 111002

The addition of these two numbers is

−710 + −410 = 110012 + 111002

⇒−710 + −410 = 1101012.

The resultant sum contains 6 bits. In this case, carry is obtained from sign
bit. So, we can remove it

Resultant sum after removing carry is −7

10 + −410 = 101012.

The sign bit ‘1’ indicates that the resultant sum is negative. So, by taking
2’s complement of it we will get the magnitude of resultant sum as 11 in
decimal number system. Therefore, addition of two negative numbers will
give another negative number.
Subtraction of two Signed Binary Numbers
Consider the two signed binary numbers A & B, which are represented in
2’s complement form. We know that 2’s complement of positive number
gives a negative number. So, whenever we have to subtract a number B
from number A, then take 2’s complement of B and add it to A. So,
mathematically we can write it as

A - B = A + 2′scomplementofB

Similarly, if we have to subtract the number A from number B, then take 2’s
complement of A and add it to B. So, mathematically we can write it as

B - A = B + 2′scomplementofA

So, the subtraction of two signed binary numbers is similar to the addition
of two signed binary numbers. But, we have to take 2’s complement of the
number, which is supposed to be subtracted. This is the advantage of 2’s
complement technique. Follow, the same rules of addition of two signed
binary numbers.

Example 3

Let us perform the subtraction of two decimal numbers +7 and +4 using

2’s complement method.

The subtraction of these two numbers is

+710 − +410 = +710 + −410.

The 2’s complement representation of +7 and -4 with 5 bits each are

shown below.

+710 = 001112

+410 = 111002

⇒+710 + +410 = 001112 + 111002 = 000112

Here, the carry obtained from sign bit. So, we can remove it. The resultant
sum after removing carry is

+710 + +410 = 000112

The sign bit ‘0’ indicates that the resultant sum is positive. So, the
magnitude of it is 3 in decimal number system. Therefore, subtraction of
two decimal numbers +7 and +4 is +3.

Example 4

Let us perform the subtraction of two decimal numbers +4 and +7 using

2’s complement method.

The subtraction of these two numbers is

+410 − +710 = +410 + −710.

The 2’s complement representation of +4 and -7 with 5 bits each are

shown below.

+410 = 001002

−710 = 110012

⇒+410 + −710 = 001002 + 110012 = 111012

Here, carry is not obtained from sign bit. The sign bit ‘1’ indicates that the
resultant sum is negative. So, by taking 2’s complement of it we will get the
magnitude of resultant sum as 3 in decimal number system. Therefore,
subtraction of two decimal numbers +4 and +7 is -3
Multiplication Algorithm in Signed Magnitude
Representation
Multiplication of two fixed point binary number in signed magnitude
representation is done with process of successive shift and add operation.

In the multiplication process we are considering successive bits of the

multiplier, least significant bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied
down.

The numbers copied down in successive lines are shifted one position to
the left from the previous number.
Finally numbers are added and their sum form the product.

The sign of the product is determined from the sign of the multiplicand and
multiplier. If they are alike, sign of the product is positive else negative.
Booth’s Algorithm
Booth algorithm gives a procedure for multiplying binary integers in signed
2’s complement representation in efficient way, i.e., less number of
additions/subtractions required. It operates on the fact that strings of 0’s in
the multiplier require no addition but just shifting and a string of 1’s in the
multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to
2^m.

As in all multiplication schemes, booth algorithm requires examination of

the multiplier bits and shifting of the partial product. Prior to the shifting, the
multiplicand may be added to the partial product, subtracted from the
partial product, or left unchanged according to following rules:

1. The multiplicand is subtracted from the partial product upon

encountering the first least significant 1 in a string of 1’s in the
multiplier
2. The multiplicand is added to the partial product upon encountering
the first 0 (provided that there was a previous ‘1’) in a string of 0’s in
the multiplier.
3. The partial product does not change when the multiplier bit is
identical to the previous multiplier bit.

Hardware Implementation of Booths Algorithm – The hardware

implementation of the booth algorithm requires the register configuration
shown in the figure below.
Booth’s Algorithm Flowchart –

We name the register as A, B and Q, AC, BR and QR respectively. Qn

designates the least significant bit of multiplier in the register QR. An extra
flip-flop Qn+1is appended to QR to facilitate a double inspection of the
multiplier.The flowchart for the booth algorithm is shown below.
AC and the appended bit Qn+1 are initially cleared to 0 and the sequence
SC is set to a number n equal to the number of bits in the multiplier. The
two bits of the multiplier in Qn and Qn+1are inspected. If the two bits are
equal to 10, it means that the first 1 in a string has been encountered. This
requires subtraction of the multiplicand from the partial product in AC. If the
2 bits are equal to 01, it means that the first 0 in a string of 0’s has been
encountered. This requires the addition of the multiplicand to the partial
product in AC.

When the two bits are equal, the partial product does not change. An
overflow cannot occur because the addition and subtraction of the
multiplicand follow each other. As a consequence, the 2 numbers that are
added always have a opposite signs, a condition that excludes an overflow.
The next step is to shift right the partial product and the multiplier (including
Qn+1). This is an arithmetic shift right (ashr) operation which AC and QR ti
the right and leaves the sign bit in AC unchanged. The sequence counter is
decremented and the computational loop is repeated n times.

Example – A numerical example of booth’s algorithm is shown below for n

= 4. It shows the step by step multiplication of -5 and -7.

MD = -5 = 1011, MD = 1011, MD'+1 = 0101

MR = -7 = 1001
The explanation of first step is as follows: Qn+1
AC = 0000, MR = 1001, Qn+1 = 0, SC = 4
Qn Qn+1 = 10
So, we do AC + (MD)'+1, which gives AC = 0101
On right shifting AC and MR, we get
AC = 0010, MR = 1100 and Qn+1 = 1
OPERATION AC MR Qn+1 SC

0000 1001 0 4

AC + MD’ + 1 0101 1001 0

ASHR 0010 1100 1 3

AC + MR 1101 1100 1
 OPERATION AC MR Qn+1 SC

ASHR 1110 1110 0 2

ASHR 1111 0111 0 1

AC + MD’ + 1 0010 0011 1 0

Product is calculated as follows:

Product = AC MR
Product = 0010 0011 = 35

Best Case and Worst Case Occurrence:

Best case is when there is a large block of consecutive 1’s and 0’s in the
multipliers, so that there is minimum number of logical operations taking
place, as in addition and subtraction.

Worst case is when there are pairs of alternate 0’s and 1’s, either 01 or 10
in the multipliers, so that maximum number of additions and subtractions
are required.
IEEE Floating point Number Representation −
IEEE (Institute of Electrical and Electronics Engineers) has standardized
Floating-Point Representation as following diagram.

So, actual number is (-1)s(1+m)x2(e-Bias), where s is the sign bit, m is the

mantissa, e is the exponent value, and Bias is the bias number. The sign
bit is 0 for positive number and 1 for negative number. Exponents are
represented by or two’s complement representation.

According to IEEE 754 standard, the floating-point number is represented

in following ways:

 Half Precision (16 bit): 1 sign bit, 5 bit exponent, and 10 bit mantissa
 Single Precision (32 bit): 1 sign bit, 8 bit exponent, and 23 bit
mantissa
 Double Precision (64 bit): 1 sign bit, 11 bit exponent, and 52 bit
mantissa
 Quadruple Precision (128 bit): 1 sign bit, 15 bit exponent, and 112 bit
mantissa

Special Value Representation −

There are some special values depended upon different values of the
exponent and mantissa in the IEEE 754 standard.

 All the exponent bits 0 with all mantissa bits 0 represents 0. If sign bit
is 0, then +0, else -0.
 All the exponent bits 1 with all mantissa bits 0 represents infinity. If
sign bit is 0, then +∞, else -∞.
 All the exponent bits 0 and mantissa bits non-zero represents
denormalized number.
 All the exponent bits 1 and mantissa bits non-zero represents error.
Instruction Execution Cycle

Instruction Execution

Instruction is command which is given by the user to computer. Execution is the process by
which a computer performs instruction. Instruction Execution means a program to be executed
by a processor consists of a set of instructions stored in memory.

Terminologies

Program Counter is a register in a computer processor that contains the address of the next
instruction which will be executed.

Memory Address Register (MAR) holds the Memory Location of data that needs to be accessed.

Instruction Register (IR) is a part of CPU control unit that stores the instruction currently being
executed or decoded.

Memory Buffer Register (MBR) stores the data being transferred to and from immediate access
store also known as Memory Data Register (MDR).

Control Unit (CU) decodes the program instruction in the IR, selecting machine resources such
as a data source register and a particular arithmetic operation.

Arithmetic Logic Unit (ALU) performs mathematical and logical operations.

Accumulator(AC) means the processor contains the single data register.

Instruction Register

❖ Fetched instruction is placed in the instruction register

❖ Categories:
• Processor-memory: Transfer data between processor and memory
• Processor-I/O: Data transferred to or from a peripheral device
• Data processing: Arithmetic or logic operation on data
• Control: Alter sequence of execution
Instruction Execution Cycle

❖ The time period during which one instruction is fetched from memory and execute when
computer given an instruction in machine language.
❖ Each instruction is further divided into sequence of phases.
❖ After the execution of program counter is incremented to point to the next instruction.

Process

I. Processor reads instruction from memory time.

II. Decodes the instruction.
III. Execute the instruction.
Fetch Cycle

• The Program Counter (PC) contains the address of the next instruction to be fetched.
• The address contained in the PC is copied to the Memory Address Register (MAR).
• The instruction is copied from the memory location contained in the MAR and placed in
the Memory Buffer Register (MBR).
• The entire instruction is copied from the MBR and placed in the Current Instruction
Register (CIR)

Execute Cycle

• The address part of the instruction is placed in the MAR

• The instruction is decoded and executed.
• The processor checks for interrupts and either branch to the relevant interrupt service
routine or start the cycle again.
 Sequencing of Control Signals

• To execute the instructions, the CPU must generate the control signals in the proper
sequence.
• Two techniques to generate the control signals are

1. Hardwired control
2. Micro programmed control

Hardwired Control

The Hardwired Control organization involves the control logic to be implemented with gates,
flip-flops, decoders, and other digital circuits.

The following image shows the block diagram of a Hardwired Control organization.

Design of Control Unit

• A Hard-wired Control consists of two decoders, a sequence counter, and a number of
logic gates.
• An instruction fetched from the memory unit is placed in the instruction register (IR).
• The component of an instruction register includes; I bit, the operation code, and bits 0
through 11.
• The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
• The outputs of the decoder are designated by the symbols D0 through D7.
• The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
• The operation codes from Bits 0 through 11 are applied to the control logic gates.
• The Sequence counter (SC) can count in binary from 0 through 15.
Micro-programmed Control

The Micro programmed Control organization is implemented by using the programming

approach.

In Micro programmed Control, the micro-operations are performed by executing a program

consisting of micro-instructions.

The following image shows the block diagram of a Micro programmed Control organization.

Design of Control Unit

• The Control memory address register specifies the address of the micro-instruction.
• The Control memory is assumed to be a ROM, within which all control information is
permanently stored.
• The control register holds the microinstruction fetched from the memory.
• The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
• While the micro-operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register to
read the next microinstruction.
• The next address generator is often referred to as a micro-program sequencer, as it
determines the address sequence that is read from control memory.
Control Signals
A pulse or frequency of electricity or light that represents a control command as it travels over a network, a
computer channel or wireless. Control signals are of two types: clocks and signals that set up communication
channels and control the flow of data.
There are three main types of control signals namely;
• Those that activate an ALU function.
• Those that activate a data path.
• Those that are signals on the external system bus or other external interface.
Clock: This is how the control unit “keeps time.” The control unit causes
one micro-operation (or a set of simultaneous micro-operations) to be
performed for each clock pulse. This is sometimes referred to as the
processor cycle time, or the clock cycle time.
Microinstructions
• A symbolic microprogram can be translated into its binary equivalent by means of an assembler.
• Each line of the assembly language microprogram defines a symbolic microinstruction.
• Each symbolic microinstruction is divided into five fields: label, microoperations, CD, BR, and AD.

Micro program:
• A sequence of microinstructions constitutes a microprogram.
• Since alterations of the microprogram are not needed once the control unit is in operation,
the control memory can be a read-only memory (ROM).
• ROM words are made permanent during the hardware production of the unit.
• The use of a micro program involves placing all control variables in words of ROM for
use by the control unit through successive read operations.
• The content of the word in ROM at a given address specifies a microinstruction.
Microcode:
• Microinstructions can be saved by employing subroutines that use common sections of microcode.
• For example, the sequence of micro-operations needed to generate the effective address of the operand
for an instruction is common to all memory reference instructions.
• This sequence could be a subroutine that is called from within many other routines to execute the
effective address computation.
Organization of micro programmed control unit
• The general configuration of a micro-programmed control unit is demonstrated in the block diagram of
Figure 4.1.
• The control memory is assumed to be a ROM, within which all control information is permanently
stored.
 figure 4.1: Micro-programmed control organization

The control memory address register specifies the address of the microinstruction, and the control data register
holds the microinstruction read from memory.
The microinstruction contains a control word that specifies one or more microoperations for the data processor.
Once these operations are executed, the control must determine the next address.
The location of the next microinstruction may be the one next in sequence, or it may be located somewhere
else in the control memory.
While the microoperations are being executed, the next address is computed in the next address generator
circuit and then transferred into the control address register to read the next microinstruction.
Thus a microinstruction contains bits for initiating microoperations in the data processor part and bits that
determine the address sequence for the control memory.
The next address generator is sometimes called a micro-program sequencer, as it determines the address
sequence that is read from control memory.
Typical functions of a micro-program sequencer are incrementing the control address register by one, loading
into the control address register an address from control memory, transferring an external address, or loading an
initial address to start the control operations.
The control data register holds the present microinstruction while the next address is computed and read from
memory.
The data register is sometimes called a pipeline register.
It allows the execution of the microoperations specified by the control word simultaneously with the generation
of the next microinstruction.
This configuration requires a two-phase clock, with one clock applied to the address register and the other to
the data register.
The main advantage of the micro programmed control is the fact that once the hardware configuration is
established; there should be no need for further hardware or wiring changes.
If we want to establish a different control sequence for the system, all we need to do is specify a different set
of microinstructions for control memory.

Address Sequencing
Microinstructions are stored in control memory in groups, with each group specifying a routine.
To appreciate the address sequencing in a micro-program control unit, let us specify the steps that the control
must undergo during the execution of a single computer instruction.

Step-1:
An initial address is loaded into the control address register when power is turned on in the computer.
This address is usually the address of the first microinstruction that activates the instruction fetch routine.
The fetch routine may be sequenced by incrementing the control address register through the rest of its
microinstructions.
At the end of the fetch routine, the instruction is in the instruction register of the computer.
Step-2:
The control memory next must go through the routine that determines the effective address of the operand.
A machine instruction may have bits that specify various addressing modes, such as indirect address and
index registers.
The effective address computation routine in control memory can be reached through a branch
microinstruction, which is conditioned on the status of the mode bits of the instruction.
When the effective address computation routine is completed, the address of the operand is available in the
memory address register.

Step-3:
The next step is to generate the microoperations that execute the instruction fetched from memory.
The microoperation steps to be generated in processor registers depend on the operation code part of the
instruction.
Each instruction has its own micro-program routine stored in a given location of control memory.
The transformation from the instruction code bits to an address in control memory where the routine is
located is referred to as a mapping process.
A mapping procedure is a rule that transforms the instruction code into a control memory address.

Step-4:
Once the required routine is reached, the microinstructions that execute the instruction may be sequenced by
incrementing the control address register.
Micro-programs that employ subroutines will require an external register for storing the return address.
Return addresses cannot be stored in ROM because the unit has no writing capability.
When the execution of the instruction is completed, control must return to the fetch routine.
This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch
routine.

In summary, the address sequencing capabilities required in a control memory are:

1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.
selection of address for control memory
 Figure 4.2: Selection of address for control memory
Above figure 4.2 shows a block diagram of a control memory and the associated hardware needed for
selecting the next microinstruction address.
The microinstruction in control memory contains a set of bits to initiate microoperations in computer
registers and other bits to specify the method by which the next address is obtained.
The diagram shows four different paths from which the control address register (CAR) receives the address.
The incrementer increments the content of the control address register by one, to select the next
microinstruction in sequence.
Branching is achieved by specifying the branch address in one of the fields of the microinstruction.
Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order
to determine its condition.
An external address is transferred into control memory via a mapping logic circuit.
The return address for a subroutine is stored in a special register whose value is then used when the micro-
program wishes to return from the subroutine.
The branch logic of figure 4.2 provides decision-making capabilities in the control unit.
The status conditions are special bits in the system that provide parameter information such as the carry-out
of an adder, the sign bit of a number, the mode bits of an instruction, and input or output status conditions.
The status bits, together with the field in the microinstruction that specifies a branch address, control the
conditional branch decisions generated in the branch logic.
A 1 output in the multiplexer generates a control signal to transfer the branch address from the
microinstruction into the control address register.
A 0 output in the multiplexer causes the address register to be incremented.

Mapping of an Instruction
A special type of branch exists when a microinstruction specifies a branch to the first word in control
memory where a microprogram routine for an instruction is located.
The status bits for this type of branch are the bits in the operation code part of the instruction.

For example, a computer with a simple instruction format as shown in figure 4.3 has an operation code of four
bits which can specify up to 16 distinct instructions.
Assume further that the control memory has 128 words, requiring an address of seven bits.
 One simple mapping process that converts the 4-bit operation code to a 7-bit address for control memory is
shown in figure 4.3.
This mapping consists of placing a 0 in the most significant bit of the address, transferring the four operation
code bits, and clearing the two least significant bits of the control address register.
This provides for each computer instruction a microprogram routine with a capacity of four
microinstructions.
If the routine needs more than four microinstructions, it can use addresses 1000000 through 1111111. If it
uses fewer than four microinstructions, the unused memory locations would be available for other routines.

Figure 4.3: Mapping from instruction code to microinstruction address

One can extend this concept to a more general mapping rule by using a ROM to specify the mapping
function.
The contents of the mapping ROM give the bits for the control address register.
In this way the microprogram routine that executes the instruction can be placed in any desired location in
control memory.
The mapping concept provides flexibility for adding instructions for control memory as the need arises.
Computer Hardware Configuration
 Figure 4.4: Computer hardware configuration
The block diagram of the computer is shown in Figure 4.4. It consists of
1. Two memory units:
Main memory -> for storing instructions and data, and
Control memory -> for storing the microprogram.
2. Six Registers:
Processor unit register: AC(accumulator),PC(Program Counter), AR(Address Register),
DR(Data Register)
Control unit register: CAR (Control Address Register), SBR(Subroutine Register)
3. Multiplexers:
The transfer of information among the registers in the processor is done through
multiplexers rather than a common bus.
4. ALU:
The arithmetic, logic, and shift unit performs microoperations with data from AC and DR
and places the result in AC.

DR can receive information from AC, PC, or memory.

AR can receive information from PC or DR.
PC can receive information only from AR.
Input data written to memory come from DR, and data read from memory can go only to
DR.

Microinstruction Format
The microinstruction format for the control memory is shown in figure 4.5. The 20 bits of the
microinstruction are divided into four functional parts as follows:
1. The three fields F1, F2, and F3 specify microoperations for the computer.
The microoperations are subdivided into three fields of three bits each. The three bits in each field are
encoded to specify seven distinct microoperations. This gives a total of 21 microoperations.
2. The CD field selects status bit conditions.
3. The BR field specifies the type of branch to be used.
4. The AD field contains a branch address. The address field is seven bits wide, since the control
memory has 128 = 27 words.

Figure 4.5: Microinstruction Format

□ As an example, a microinstruction can specify two simultaneous microoperations fromF2 and F3
and none from F1.
DR M[AR] with F2 = 100PC PC +
1 with F3 = 101
□ The nine bits of the microoperation fields will then be 000 100 101.
□ The CD (condition) field consists of two bits which are encoded to specify four status bitconditions
as listed in Table 4.1.
 Table 4.1: Condition Field

□ The BR (branch) field consists of two bits. It is used, in conjunction with the address fieldAD, to
choose the address of the next microinstruction shown in Table 4.2.

Table 4.2: Branch Field

Symbolic Microinstruction.
□ Each line of the assembly language microprogram defines a symbolic microinstruction.
□ Each symbolic microinstruction is divided into five fields: label, microoperations, CD,BR, and
AD. The fields specify the following Table 4.3.

1. Label The label field may be empty or it may specify a symbolic

address. A label is terminated with a colon (:).
2. Microoperations It consists of one, two, or three symbols, separated by
commas, from those defined in Table 5.3. There may be no
more than one symbol from each F field. The NOP symbol
is used when the microinstruction has no microoperations.
This will be translated by the assembler to nine zeros.
3. CD The CD field has one of the letters U, I, S, or Z.
4. BR The BR field contains one of the four symbols defined in
Table 5.2.
 5. AD The AD field specifies a value for the address field of the
microinstruction in one of three possible ways:
i. With a symbolic address, this must also appear as a
label.
ii. With the symbol NEXT to designate the next
address in sequence.
iii. When the BR field contains a RET or MAP symbol,
the AD field is left empty and is converted to seven
zeros by the assembler.
Table 4.3: Symbolic Microinstruction
Micro programmed sequencer for a control memory
Microprogram sequencer:
□ The basic components of a microprogrammed control unit are the control memory and the
circuits that select the next address.
□ The address selection part is called a microprogram sequencer.
□ A microprogram sequencer can be constructed with digital functions to suit a particular
application.
□ To guarantee a wide range of acceptability, an integrated circuit sequencer must providean
internal organization that can be adapted to a wide range of applications.
□ The purpose of a microprogram sequencer is to present an address to the control memoryso that
a microinstruction may be read and executed.
□ Commercial sequencers include within the unit an internal register stack used for
temporary storage of addresses during microprogram looping and subroutine calls.
□ Some sequencers provide an output register which can function as the address register forthe
control memory.
□ The block diagram of the microprogram sequencer is shown in figure 4.6.
□ There are two multiplexers in the circuit.
□ The first multiplexer selects an address from one of four sources and routes it into acontrol
address register CAR.
□ The second multiplexer tests the value of a selected status bit and the result of the test is
applied to an input logic circuit.
□ The output from CAR provides the address for the control memory.
□ The content of CAR is incremented and applied to one of the multiplexer inputs and tothe
subroutine registers SBR.
□ The other three inputs to multiplexer 1 come from the address field of the presentmicroinstruction,
from the output of SBR, and from an external source that maps the instruction.
□ Although the figure 4.6 shows a single subroutine register, a typical sequencer will have aregister
stack about four to eight levels deep. In this way, a number of subroutines can be active at the
same time.
□ The CD (condition) field of the microinstruction selects one of the status bits in thesecond
multiplexer.
□ If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise, it is equal to0.
□ The T value together with the two bits from the BR (branch) field goes to an input logiccircuit.
□ The input logic in a particular sequencer will determine the type of operations that are
available in the unit.
 3 2 10
l0 Input Load

1
S MUX 1 SBR
l1 Logic

T 0

1
Test Incremen
MUX 2 t
L Clock CAR
Select

Control
Memory
Microo AD
ps CD BR

Figure 4.6: Microprogram Sequencer for a control memory

Input Logic : Truth Table

BR Input MUX 1 Load SBR
I1 I0 T S1 S0 L
00 0 0 0 0 0 0
00 0 0 1 0 1 0
01 0 1 0 0 0 0
01 0 1 1 0 1 1
10 1 0 X 1 0 0
11 1 1 X 1 1 0
Table 4.4: Input Logic Truth Table for Microprogram Sequencer

Boolean Function:
S0 = I0
S1 = I0I1 + I0’TL =
I0’I1T

□ Typical sequencer operations are: increment, branch or jump, call and return from subroutine, load
an external address, push or pop the stack, and other address sequencing operations.
□ With three inputs, the sequencer can provide up to eight address sequencing operations.
□ Some commercial sequencers have three or four inputs in addition to the T input and thusprovide a
wider range of operations.

Central Processing Unit

General Register Organization :

The Central Processing Unit (CPU) is called the brain of the computer that performs data-processing
operations. Figure 3.1 shows the three major parts of CPU.
·

Intermediate data is stored in the register set during the execution of the instructions. Themicrooperations
required for executing the instructions are performed by the arithmetic logic unit whereas the control unit
takes care of transfer of information among the registers and guides the ALU. The control unit services the
transfer of information among the registers and instructs the ALU about which operation is to be
performed. The computer instruction set is meant forproviding the specifications for the design of the
CPU. The design of the CPU largely, involves choosing the hardware for implementing the machine
instructions. The need for memory locations arises for storing pointers, counters, return address,
temporary results and partial products. Memory access consumes the most of the time off an operation in a
computer. It is more convenient and more efficient to store these intermediate values in processor registers.
A common bus system is employed to contact registers that are included in the CPU in a large number.
Communications between registers is not only for direct data transfer but also for performing various micro-
operations. A bus organization for such CPU register shown in Figure 3.2, is connected to two multiplexers
(MUX) to form two buses A and B. The selected lines in each multiplexers select one register of the input
data for the particular bus.
OPERATION OF CONTROL UNIT:
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
1] MUX A selector (SELA): BUS A R2
[2] MUX B selector (SELB): BUS B R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 Out Bus

Control Word
 Encoding of register selection fields

Encoding of ALU operations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word

Stack organization:
 □ A stack is a storage device that stores information in such a manner that the item storedlast is the first
item retrieved.
□ The stack in digital computers is essentially a memory unit with an address register that can count only.
The register that holds the address for the stack is called a stack pointer (SP) because its value always
points at the top item in the stack.
□ The physical registers of a stack are always available for reading or writing. It is thecontent of the
word that is inserted or deleted.

Register stack:

Figure 5.1: Block diagram of a 64-word stack

□ A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite
number of memory words or registers. Figure shows the organization of a 64- word register stack.
□ The stack pointer register SP contains a binary number whose value is equal to the addressof the
word that is currently on top of the stack. Three items are placed in the stack: A, B, and C, in that
order. Item C is on top of the stack so that the content of SP is now 3.
□ To remove the top item, the stack is popped by reading the memory word at address 3 and
decrementing the content of SP. Item B is now on top of the stack since SP holds address 2.
□ To insert a new item, the stack is pushed by incrementing SP and writing a word in the next-
higher location in the stack.
□ In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
□ Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary). When 63
are incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but SP can accommodate
only the six least significant bits.
□ Similarly, when 000000 is decremented by 1, the result is 111111. The one-bit register FULL is
set to 1 when the stack is full, and the one-bit register EMTY is set to 1 when thestack is empty of
items.

□ DR is the data register that holds the binary data to be written into or read out of the stack.

PUSH:
 □ If the stack is not full (FULL =0), a new item is inserted with a push operation. The pushoperation
consists of the following sequences of microoperations:

SP ← SP + 1 Increment stack pointer

M [SP] ← DR WRITE ITEM ON TOP OF THE STACK
IF (SP = 0) then (FULL ← 1)Check is stack is full EMTY ← 0
Mark the stack not empty

□ The stack pointer is incremented so that it points to the address of next-higher word. Amemory
write operation inserts the word from DR into the top of the stack.
□ SP holds the address of the top of the stack and that M[SP] denotes the memory wordspecified by
the address presently available in SP.
□ The first item stored in the stack is at address 1. The last item is stored at address 0. If SP reaches 0,
the stack is full of items, so FULL is set to 1. This condition is reached if thetop item prior to the
last push was in location 63 and, after incrementing SP, the last item is stored in location 0.
□ Once an item is stored in location 0, there are no more empty registers in the stack. If an item is written
in the stack, obviously the stack cannot be empty, so EMTY is cleared to 0.

POP:
□ A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The popoperation
consists of the following sequences of microoperations:

DR ← M [SP] Read item on top of the stack

SP ← SP - 1 Decrement stack pointer
IF (SP = 0) then (EMTY ← 1) Check if stack is emptyFULL ←
0 Mark the stack not full
□ The top item is read from the stack into DR. The stack pointer is then decremented. If itsvalue reaches
zero, the stack is empty, so EMTY is set to 1.

□ This condition is reached if the item read was in location 1.

□ Once this item is read out, SP is decremented and reaches the value 0, which is the initial value of SP. If a
pop operation reads the item from location 0 and then SP is decremented, SP is changes to 111111, which
is equivalent to decimal 63.
□ In this configuration, the word in address 0 receives the last item in the stack. Note also that an erroneous
operation will result if the stack is pushed when FULL = 1 or popped when EMTY = 1.

Memory Stack.
 Figure 5.2: Computer memory with program, data, and stack segments

□ The implementation of a stack in the CPU is done by assigning a portion of memory to astack
operation and using a processor register as a stack pointer.
□ Figure 5.2 shows a portion of computer memory partitioned into three segments: program,data, and
stack.
□ The program counter PC points at the address of the next instruction in the program whichis used during
the fetch phase to read an instruction.
□ The address registers AR points at an array of data which is used during the execute phase to read an
operand.
□ The stack pointer SP points at the top of the stack which is used to push or pop items into or from the
stack.
□ The three registers are connected to a common address bus, and either one can provide an address for
memory.
□ As shown in Figure 5.2, the initial value of SP is 4001 and the stack grows with decreasing addresses.
Thus the first item stored in the stack is at address 4000, the second item is stored at address 3999, and the
last address that can be used for the stack is 3000.
□ We assume that the items in the stack communicate with a data register DR.

PUSH
□ A new item is inserted with the push operation as follows:
SP ← SP - 1 M[SP]
←DR
□ The stack pointer is decremented so that it points at the address of the next word.
□ A memory write operation inserts the word from DR into the top of the stack.

POP
□ A new item is deleted with a pop operation as follows:
DR ←
M[SP] SP
 ← SP + 1
□ The top item is read from the stack into DR.
□ The stack pointer is then incremented to point at the next item in the stack.
□ The two microoperations needed for either the push or pop are (1) an access to memorythrough
SP, and (2) updating SP.
□ Which of the two microoperations is done first and whether SP is updated by
incrementing or decrementing depends on the organization of the stack.
□ In figure. 5.2 the stack grows by decreasing the memory address. The stack may be
constructed to grow by increasing the memory also.
□ The advantage of a memory stack is that the CPU can refer to it without having to specify an address,
since the address is always available and automatically updated in the stack pointer.

Instruction formats:

Insruction fields:

OP-code field - specifies the operation to be performed

Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the effective address is determined.
The number of address fields in the instruction format depends on the internal organization of CPU
-The three most common CPU organizations:
ADDRESSING MODES :

* Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is
actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user
- to use the bits in the address field of the
instruction efficiently

TYPES OF ADDRESSING MODES :

Register Indirect Mode
Instruction specifies a register which contains the memory address of the operand
- Saving instruction bits since register addres is shorter than the memory address
- Slower to acquire an operand than both the register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)
Auto-increment or Auto-decrement features:
Same as the Register Indirect, but:
- When the address in the register is used to access memory, the value in the register is incremented
or decremented by 1 (after or before the execution of the instruction)
Direct Address Mode
Instruction specifies the memory address which can be used directly to the physical memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large physical memory space
- EA = IR(address), (IR(address): address field of IR)
Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that contains the
address of the operand
- When the abbreviated address is used, large physical memory can be addressed with a relatively
small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]

Relative Addressing Modes

The Address fields of an instruction specifies the part of the address(abbreviated address) which
can be used along with a designated register to calculate the address of the operand
PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of address bits

Indexed Addressing Mode

XR: Index Register:
- EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
 ADDRESSING MODES - EXAMPLES
Memory
Address
200 Load to AC Mode
PC = 200 Address = 500
201 Next instruction

202
450
R1 = 400
700
399
XR = 100
400 800

900
AC
500
325

600 300
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC  (500) */ 800
Immediate operand - /* AC  500 */ 500 702
Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325
Indexed address 600 /* AC  (XR+500) */ 900
Register - /* AC  R1 */ 400 800
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

cpe 252: Computer Organization 18

Data Transfer Instructions.

□ Data transfer instructions move data from one place in the computer to another withoutchanging
the data content.
□ The most common transfers are between memory and processor registers, betweenprocessor
registers and input or output, and between the processor registers themselves.
□ The load instruction has been used mostly to designate a transfer from memory to aprocessor
register, usually an accumulator.
□ The store instruction designates a transfer from a processor register into memory.
□ The move instruction has been used in computers with multiple CPU registers to designatea transfer
from one register to another. It has also been used for data transfers between CPU registers and memory
or between two memory words.
□ The exchange instruction swaps information between two registers or a register and amemory
word.
□ The input and output instructions transfer data among processor registers and input oroutput
terminals.
□ The push and pop instructions transfer data between processor registers and a memorystack.
Data Transfer Instructions with Different Addressing Modes
 DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions

Logical and bit manipulation instructions

Shift instructionsArithmetic
Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions

Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right thru carry RORC
Rotate left thru carry ROLC

Computer Organization 20

PROGRAM CONTROL INSTRUCTIONS :

□ It is sometimes convenient to supplement the ALU circuit in the CPU with a status register where status
bit conditions be stored for further analysis. Status bits are alsocalled condition-code bits or flag bits.
□ Figure 5.3 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four status bits are
symbolized by C, S, Z, and V. The bits are set or cleared as a result of an operation performed in the ALU.

Figure 5.3: Status Register Bits

1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if set to 0 if thebit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0’s. it is cleared to 0 otherwise. In other
words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusives-OR of the last two carries is equal to1, and cleared
to 0 otherwise. This is the condition for an overflow when negative numbers are in 2’s complement.
For the 8-bit ALU, V = 1 if the output is greater than + 127 or less than -128.
□ The status bits can be checked after an ALU operation to determine certain relationshipsthat exist
between the vales of A and B.
□ If bit V is set after the addition of two signed numbers, it indicates an overflow condition.
□ If Z is set after an exclusive-OR operation, it indicates that A = B.
□ A single bit in A can be checked to determine if it is 0 or 1 by masking all bits except thebit in question
and then checking the Z status bit.

Program Control Instructions

CMP and TST instructions do not retain their results of operations(- and AND, respectively).
They only set or clear certain Flags.
 CONDITIONAL BRANCH INSTRUCTIONS

Mnemonic Branch condition Tested condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B) BHI
Branch if higher A>B
BHE Branch if higher or equal A
BBLO Branch if lower A<B
BLOE Branch if lower or equal A
BBE Branch if equal A= B
BNE Branch if not equal A B
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A B BLT
Branch if less than A<B
BLE Branch if less or equal A B
BE Branch if equal A= B
BNE Branch if not equal A B

cpe 252: Computer Organization 22

SUBROUTINE CALL AND RETURN

SUBROUTINE CALL Call subroutine Jump
to subroutine Branch
to subroutine
Branch and save return address
Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine

- Same as the Branch or Conditional Branch

* Save the Return Address to get the address of the

location in the Calling Program upon exit from
the Subroutine
- Locations for storing Return Address: CALL
• Fixed Location in the subroutine(Memory) SP  SP - 1
• Fixed Location in memory M[SP]  PC
• In a processor Register PC  EA
• In a memory stack
- most efficient way RTN
PC  M[SP]
cpe 252: Computer Organization SP  SP 23
+ 1
PROGRAM INTERRUPT:
□ The concept of program interrupt is used to handle a variety of problems that arise out of
normal program sequence.
□ Program interrupt refers to the transfer of program control from a currently running program to
another service program as a result of an external or internal generated request. Control returns
to the original program after the service program is executed.
□ After a program has been interrupted and the service routine been executed, the CPU must
return to exactly the same state that it was when the interrupt occurred.
□ Only if this happens will the interrupted program be able to resume exactly as if nothing had
happened.
□ The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:

1. The content of the program counter

2. The content of all processor registers
3. The content of certain status conditions

□ The interrupt facility allows the running program to proceed until the input or output device
sets its ready flag. Whenever a flag is set to 1, the computer completes the execution of the
instruction in progress and then acknowledges the interrupt.
□ The result of this action is that the retune address is stared in location 0. The instruction in
location 1 is then performed; this initiates a service routine for the input or output transfer. The
service routine can be stored in location 1.

□ The service routine must have instructions to perform the following tasks:

1. Save contents of processor registers.

2. Check which flag is set.
3. Service the device whose flag is set.
4. Restore contents of processor registers.
5. Turn the interrupt facility on.
6. Return to the running program.
Types of interrupts.:
There are three major types of interrupts that cause a break in the normal execution of a program.
They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts

1) External interrupts:
□ External interrupts come from input-output (I/0) devices, from a timing device, from a circuit
monitoring the power supply, or from any other external source.
□ Examples that cause external interrupts are I/0 device requesting transfer of data, I/o device
finished transfer of data, elapsed time of an event, or power failure. Timeout interrupt may
result from a program that is in an endless loop and thus exceeded its time allocation.
□ Power failure interrupt may have as its service routine a program that transfers the complete
state of the CPU into a nondestructive memory in the few milliseconds before power ceases.
□ External interrupts are asynchronous. External interrupts depend on external conditions that
are independent of the program being executed at the time.

2) Internal interrupts:
□ Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal
interrupts are also called traps.
□ Examples of interrupts caused by internal error conditions are register overflow, attempt to
divide by zero, an invalid operation code, stack overflow, and protection violation. These
error conditions usually occur as a result of a premature termination of the instruction
execution. The service program that processes the internal interrupt determines the corrective
measure to be taken.
□ Internal interrupts are synchronous with the program. . If the program is rerun, the internal
interrupts will occur in the same place each time.

3) Software interrupts:
□ A software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call. It can be used by the programmer to initiate an interrupt procedure at any
desired point in the program.
□ The most common use of software interrupt is associated with a supervisor call instruction. This
instruction provides means for switching from a CPU user mode to the supervisor mode. Certain
operations in the computer may be assigned to the supervisor mode only, as for example, a
complex input or output transfer procedure. A program written by a user must run in the user
mode.
□ When an input or output transfer is required, the supervisor mode is requested by means of a
supervisor call instruction. This instruction causes a software interrupt that stores the old CPU
state and brings in a new PSW that belongs to the supervisor mode.
□ The calling program must pass information to the operating system in order to specify the
particular task requested.
Reverse Polish Notation (RPN) with appropriate example.
□ The postfix RPN notation, referred to as Reverse Polish Notation (RPN), places
theoperator after the operands.
□ The following examples demonstrate the three representations:
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
□ The reverse Polish notation is in a form suitable for stack manipulation.
The expression
A * B + C * D is written in reverse Polish
notation asA B * C D * +
□ The conversion from infix notation to reverse Polish notation must take into
considerationthe operational hierarchy adopted for infix notation.
□ This hierarchy dictates that we first perform all arithmetic inside inner parentheses, then
inside outer parentheses, and do multiplication and division operations before addition
and subtraction operations.

Evaluation of Arithmetic Expressions

□ Any arithmetic expression can be expressed in parenthesis-free Polish notation,
includingreverse Polish notation
(3 * 4) + (5 * 6) 34*56*+

RISC characteristics and CISC characteristics

RISC (Reduced Instruction Set Computer)
RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate
electronic circuitry in the control unit, which produces all the necessary signals, this approach of
the design of the control section of the processor is called RISC design. It is also called hard-wired
approach.
Examples of RISC processors:
• IBM RS6000, MC88100.
• DEC’s Alpha 21064, 21164 and 21264 processors
• Features of RISC Processors: The standard features of RISC processors are listed below:
 • RISC processors use a small and limited number of instructions.
• RISC machines mostly uses hardwired control unit.
• RISC processors consume less power and are having high performance.
• Each instruction is very simple and consistent.
• RISC processors uses simple addressing modes.
• RISC instruction is of uniform fixed length.

CISC (Complex Instruction Set Computer)

CISC stands for Complex Instruction Set Computer. If the control unit contains a number of
microelectronic circuitry to generate a set of control signals and each micro-circuitry is activated
by a microcode, this design approach is called CISC design.
Examples of CISC processors are:
• Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III
• Motorola’s 68000, 68020, 68040, etc.
• Features of CISC Processors: The standard features of CISC processors are listed below:
• CISC chips have a large amount of different and complex instructions.
• CISC machines generally make use of complex addressing modes.
• Different machine programs can be executed on CISC machine.
• CISC machines uses micro-program control unit.
• CISC processors are having limited number of registers.
RISC: Reduce the cycles per instruction at the cost of the number of instructions per program.
CISC: The CISC approach attempts to minimize the number of instructions per program but at
the cost of increase in number of cycles per instruction.

Characteristic of RISC –
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More number of general-purpose registers.
• Simple Addressing Modes.
• Less Data types.
• Pipeline can be achieved.
Characteristic of CISC –
• Complex instruction, hence complex instruction decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers as operation get performed in memory itself.
• Complex Addressing Modes.
• More Data types.
Example – Suppose we have to add two 8-bit number:
CISC approach: There will be a single command or instruction for this like ADD which will
perform the task.

RISC approach: Here programmer will write the first load command to load data in registers then
it will use a suitable operator and then it will store the result in the desired location.

So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are
longer and require more memory to get stored but require fewer transistors due to less complex
command.

Difference

RISC CISC

It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

It emphasizes on software to optimize the It emphasizes on hardware to optimize the

instruction set. instruction set.

It is a hard wired unit of programming in the Microprogramming unit in CISC

RISC Processor. Processor.

It requires multiple register sets to store the It requires a single register set to store the
instruction. instruction.

RISC has simple decoding of instruction. CISC has complex decoding of instruction.

Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
 It uses a large number of instruction that
It uses a limited number of instruction that
requires more time to execute the
requires less time to execute the instructions.
instructions.

It uses LOAD and STORE that are independent It uses LOAD and STORE instruction in
instructions in the register-to-register a program's the memory-to-memory interaction of a
interaction. program.

CISC has transistors to store complex

RISC has more transistors on memory registers.
instructions.

The execution time of RISC is very short. The execution time of CISC is longer.

RISC architecture can be used with high-end CISC architecture can be used with low-
applications like telecommunication, image end applications like home automation,
processing, video processing, etc. security system, etc.

It has fixed format instruction. It has variable format instruction.

The program written for RISC architecture needs Program written for CISC architecture
to take more space in memory. tends to take less space in memory.

Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the family, System/360, AMD and the Intel
SPARC. x86 CPUs.

University Questions
1.Compare the functions of RISC and CISC (9 Marks)2020
2.Explain the steps for branch address modification (9 Marks)2018
 Cache Memories
● Main memory (still) slow in comparison to processor speed.
● Main memory constrained by packaging, electronic characteristics and costs.
● Cache memory on the processor chip typically ten times faster than main memory.

Cache Memories:Locality of Reference

● Programs tend to spend their time “focused” on particular groups of instructions

■ Loops
■ Frequently called procedures.

● “Localized” areas of programs executed repeatedly during some time period

● Remainder of the program is accessed infrequently

● Temporal

■ Recently executed instruction likely to repeat soon

■ When first accessed, move to cache where it will be when referenced again
● Spatial

■ Instructions near an executed instruction likely to be executed soon

■ When fetching an instruction from memory, move its neighbors into cache as well

Cache Memories

Fig 5.14-Use of a cache memory

● Read request is received from the processor,

■ block of memory words containing the location specified are transferred
into the cache one word at a time.
■ Subsequently, when the program references any of the locations in this
block, the desired contents are read directly from the cache.
 ■ store a reasonable number of blocks at any given time

● correspondence between the main memory blocks and those in the cache is specified by a
mapping function.
● When the cache is full and a memory word (instruction or data) that is not in the cache is
referenced, the cache control hardware must decide which block should be removed to create
space for the new block that contains the referenced word.
● The collection of rules for making this decision constitutes the replacement algorithm.
● The cache control circuitry determines whether the requested word currently exists in the
cache.
● If it does, the Read or Write operation is performed on the appropriate cache location.
● In this case, a read or write hit is said to have occurred.
● In a Read operation, the main memory is not involved.
● For a Write operation, the system can proceed in 2 ways.
■ write-through protocol:the cache location and the main memory location are
updated simultaneously
■ write-back, or copy-back, protocol.update only the cache location and to mark it
as updated with an associated flag bit, often called the dirty or modified bit.
● The main memory location of the word is updated later, when the block containing
this marked word is to be removed from the cache to make
room for a new block.
● When the addressed word in a Read operation is not in the cache, a read miss occurs.
● The block of words that contains the requested word is copied from the main memory into the
cache.
● After the entire block is loaded into the cache, the particular word requested is forwarded to
the processor.
● Alternatively, this word may be sent to the processor as soon as it is read from the main
memory this approach, which is called load-through, or early restart,
● During a Write operation, if the addressed word is not in the cache, a write miss occurs.
● Then, if the write-through protocol is used, the information is written directly into the main
memory.
● In the case of the write-back protocol, the block containing the addressed word is first brought
into the cache, and then the desired word in the cache is overwritten with the new information.
 SECONDARY MEMORY
• As we all known that primary memory, is expensive as well
as limited. The faster primary memory are also volatile. If
we need to store large amount of data or programs
permanently, we need a cheaper and permanent memory.
Such memory is called secondary memory.

• Secondary storage commonly used for archival and backup

purposes. If a computer stops functioning, a secondary
storage device may be used to restore a recent backup to a
new system. Therefore, if you use a secondary storage
device to backup your data, make sure you run frequent
backups and test the data on a regular basis.
 Characteristics of secondary memory
• It is non-volatile, i.e. it retains data when
power is switched off
• It is large capacities to the tune of terabytes
• It is cheaper as compared to primary memory
• Durable
• Portable
 SECONDARY STORAGE DEVICES
• A secondary storage device refers to any non-
volatile storage device that is internal or
external to the computer.
• It can be any storage device beyond the
primary storage that enables permanent data
storage.
• A secondary storage device is also known as
an auxiliary storage device, backup storage
device, tier 2 storage, or external storage.
Different types of storage devices are

Hard Disk
CD- ROM
Floppy Disk
Memory Card
Flash Drive
1. HARD DISK
• Hard disk drive is made up of a series of circular
disks called platters arranged one over the other
almost ½ inches apart around a spindle.
• Disks are made of non-magnetic material like
aluminum alloy and coated with 10-20 nm of
magnetic material.
• Standard diameter of these disks is 14 inches and
they rotate with speeds varying from 4200 rpm
(rotations per minute) for personal computers to
15000 rpm for servers.
• Data is stored by magnetizing or
demagnetizing the magnetic coating.
• A magnetic reader arm is used to read data
from and write data to the disks. A typical
modern HDD has capacity in terabytes (TB).
2. CD-ROM
• CD stands for Compact Disk. CDs are circular
disks that use optical rays, usually lasers, to
read and write data.
• They are very cheap as you can get 700 MB of
storage space for less than a dollar. CDs are
inserted in CD drives built into CPU cabinet.
• They are portable as you can eject the drive,
remove the CD and carry it with you.
There are three types of CDs.

• CD-ROM (Compact Disk – Read Only Memory) −

The data on these CDs are recorded by the
manufacturer. Proprietary Software, audio or
video are released on CD-ROMs.
• CD-R (Compact Disk – Recordable) − Data can be
written by the user once on the CD-R. It cannot
be deleted or modified later.
• CD-RW (Compact Disk – Rewritable) −
Data can be written and
deleted on these optical
disks again and again.
3. FLOPPY DISK
• A floppy disk or floppy diskette (sometimes
casually referred to as a floppy or diskette) is a
type of disk storage composed of a thin and
flexible disk of a magnetic storage medium in
a square or nearly square plastic enclosure
lined with a fabric that removes dust particles
from the spinning disk.
• Floppy disks are read from and written to by a
floppy disk drive (FDD).
• Floppy disks were so common in late 20th-century culture
that many electronic and software programs continue to
use save icons that look like floppy disks well into the 21st
century. While floppy disk drives still have some limited
uses, especially with legacy industrial computer equipment,
they have been superseded by data storage methods with
much greater data storage capacity and data transfer
speed, such as USB flash drives, memory cards, optical
discs, and storage available through local computer
networks and cloud storage.
4. MEMORY CARD
• A memory card or memory cartridge is an
electronic data storage device used for storing
digital information, typically using flash memory.
• These are commonly used in portable electronic
devices, such as digital cameras, mobile phones,
laptop computers, tablets etc.
• allow adding memory to such devices without
compromising ergonomy, as the card is usually
contained within the device rather than
protruding lik.e USB flash drives
• allow adding memory to such devices without
compromising ergonomy, as the card is usually
contained within the device rather than
protruding lik.e USB flash drives
5. FLASH DRIVE
• A USB flash drive is a data storage device that
includes flash memory with an integrated USB
interface.
• It is typically removable, rewritable and much
smaller than an optical disc
• weigh less than 30 g.
• USB flash drives are often used for storage,
data back-up and transferring of computer
files.
• Compared with floppy disks or CDs, they are
smaller, faster, have significantly more
capacity, and are more durable due to a lack
of moving parts.
• USB flash drives use the USB mass storage
device class standard, supported natively by
modern operating systems such as Windows,
Linux, macOS and other Unix-like systems, as
well as many BIOS boot ROMs.
 Interrupts
➔ To avoid the processor being not performing any useful computation, a hardware signal called an interrupt to the processor can solve this.
One of the bus control lines, called an interrupt-request line, is usually
Dedicated for the purpose.
➔ An interrupt-service routine usually is needed and is executed when an interrupt request is issued.On the other hand, the
processor must inform the device that its request has been recognized so that it may remove its interrupt-request signal. An interrupt-
acknowledge signal serves this function.

Example
Program Program
COMPUTE PRINT
2
1
routine routine
1
2

Interrupt i
her
occurs
e i+
1
M
Interrupts
•An interrupt is the automatic transfer of software execution in response to a Hardware/Software event that is asynchronous
with the current software execution.

• When a process or an event needs immediate attention, it triggers interrupt.

•INTERRUPT meaning to break the sequence of operations.

• While the processor is executing a program an ‘interrupt’ breaks the sequence of execution of that program and start
execution of another program.
•ISR –routine executed in response to interrupt requests.

Interrupt-Service Routine & Subroutine

Treatment of an interrupt-service routine is very similar to that of a subroutine
An important departure from the similarity should be noted
◆ A subroutine performs a function required by the program from which it is called.
◆ The interrupt-service routine may not have anything in common with the program being executed at the time the interrupt
request is received. In fact, the two programs often belong to different users.Before executing the interrupt-service
routine, any information that may be altered during the execution of the current routine must be saved. This
information must be restored before handling the interrupted programme.
Interrupt Latency

The information that needs to be saved and restored typically includes the condition code flags and the contents of any
registers used by the current program.
Saving registers also increases the delay between the time an interrupt request is received and the start of execution of the
interrupt-service routine. The delay is called interrupt latencyTypically, the processor saves the contents of the program
counter, the processor status register and some additional information that needs to be saved on STACKS.

Interrupt Hardware: An equivalent circuit for an open-drain bus used to implement a common interrupt-request
line.

Vd
Process
R
INR INT

INTR INTR INTR

 INTR=INTR1+INTR2+…+INTRn

•Most computers have several I/O devices that can request an interrupt.
• A single interrupt request line may be used to serve n devices.
•Devices connected via switches to ground.
•Request – by closing switch.
•Vdd is inactive state of line only when all the request signals(INTR1 to INTRn) are inactive.
•When any device requests by closing switch, INTR line drops to 0 causing INTR signal to CPU.
➔ All computers fundamentally should be able to enable and disable interruptions as desired. When a device
activates the interrupt-request signal, it keeps this signal activated until it learns that the processor has accepted
its request.

• When interrupts are enabled, the following is a typical scenario:

• The device raises an interrupt request.

• The processor interrupts the program currently being executed.

• Interrupts are disabled by changing the control bits in the processor status register (PS).

• The device is informed that its request has been recognized and deactivates the interrupt request
signal.
 • The action requested by the interrupt is performed by the interrupt-service routine.

• Interrupts are enabled and execution of the interrupted program is resumed.

Handling multiple devices gives rise to a number of questions:
◆ How can the processor recogniz e the device requesting an interrupt?
◆ Given that different devices are likely to require different interrupt-service routines, how can the processor obtain the
starting address of the appropriate routine in each case?
◆ Should a device be allowed to interrupt the processor while another interrupt is being serviced?
◆ How should two or more simultaneous interrupt request be handled?

Polling
Vectored Interrupts
Interrupts nesting (priority)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

Identify the Interrupting Device

When a device raises an interrupt request, it sets to 1 one of the bits in its status register , which we will call the IRQ bit.
The simplest way to identify the interrupting device is to have the interrupt-service routine poll all the I / O devices connected to
the bus. The first device encountered with IRQ bit set is serviced. Time consuming process.
 • A device requesting an interrupt may identify itself directly to the processor by sending its own special code in the
bus . Tis code include starting address of ISR for this interrupt. This address is called Interrupt vector .

Then, the processor can immediately start executing the corresponding interrupt-service routine. Then it activates Interrupt
acknowledge line
INTA. This is called vectored interrupts.

Nesting interrupts
CPU getting another Interrupts while handling one.
Eg: Tracking ‘Time of the day’ based on real time clock. This device interrupts at regular intervals to update
counters. So need to handle 2nd interrupt.

An interrupt request from a high-priority device should be accepted while the processor is servicing another request from a lower-
priority device
Interrupt Priority

The processor’s priority is usually encoded in a few bits of the processor status word. It can be changed by program instructions
that write into the program status register (PS). These are privileged instructions, which can be executed only while the processor
is running in the supervisor mode
The processor is in the su pervisor mode only when executing operating system routines. It switches to the user mode before
beginning to execute application program
An attempt to execute a privileged instruction while in the user mode leads to a special type of interrupt called a privilege
exception

Implementation of Interrupt Priority

An example of the implementation of a multiple- priority scheme

Pr INTR1 INTRp
o Device 1 Device 2 Device p
INTA
ce INTA
ss

Priority arbitration
circuit
 Simultaneous Requests
Consider the problem of simultaneous arrivals of interrupt requests on single line

➔ from two or more devices. The processor must have some means of deciding which request to
service first Interrupt priority scheme with Daisy chain.

Devices connected to a single line. Devices arranged in priority basis. More than one device
can make INTR low. The Processor response to it by sending INTA which passes in a daisy
chain fashion.
Needed device seize the INTA and puts its vector on bus.
 Pr INTR
o
ce
ss
or

Device 1 Device 2 Device n

INT
A

•At the device end, an interrupt enable bit determines whether it is allowed to generate an interrupt request.
•At the processor end, either Enable bit or Priority scheme determines whether a given interrupt request will be
accepted.
Exceptions

•The term exception is used to refer to any event that causes an interruption.
•Hence, I/O interrupts are one example of an exception.
 • Recovery from errors – These are techniques to ensure that all hardware components are operating
properly.

• Debugging – find errors in a program, trace and breakpoints (only at specific points selected by the user).

• Privilege exception – execute privileged instructions to protect OS of a computer. A user pgm will not
allowed to change the priority level
Use of interrupts in Operating Systems

•Operating system is system software which is also termed as resource manager, as it manages all variety of computer
peripheral devices efficiently.
OS uses interrupts for

• Managing i/o devices connected

• Memory protection
• Multitasking Context switching.
DMA (Direct memory access)

Program-controlled I/O:

◆ Processor polls a status flag in the device interface.

◆ Overhead associated with polling the status flag.

I/O using interrupts:

Processor waits for the device to send an interrupt request.

◆ Overhead associated with saving and restoring the Program

Counter (PC) and other state information.

In addition, if we want to transfer a group of words, the

processor needs to execute instructions which increment

the memory address and keep track of the word count.

To transfer large blocks of data at high speed, an alternative approach is used.

▪ Direct memory access

A special control unit is provided to allow transfer of a block of data directly between an
external device and the main memory, without continuous intervention by the processor. This
approach is called direct memory access, or DMA.

DMA transfers are performed by a control circuit that is part of the I/O device interface. We
refer to this circuit as a DMA controller. The DMA controller performs the functions that
would normally be carried out by the processor when accessing the main memory. For each
word transferred, it provides the memory address and all the bus signals that control data
transfer. Since it has to transfer blocks of data, the DMA controller must increment the
memory address for successive words and keep track of the number of transfers.

Although a DMA controller can transfer data without intervention by the processor, its
operation must be under the control of a program executed by the processor. To initiate the
transfer of a block of words, the processor sends the starting address, the number of words in
the block, and the direction of the transfer. On receiving this information, the DMA controller
proceeds to perform the requested operation. When the entire block has been transferred, the
controller informs the processor by raising an interrupt signal.
While a DMA transfer is taking place, the program that requested the transfer cannot
continue, and the processor can be used to execute another program. After the DMA transfer
is completed, the processor can return to the program that requested the transfer.

I/O operations are always performed by the operating system of the computer in response to a
request from an application program. The OS is also re, initiates the DMA operation, and
starts the execution of another program. When the transfer is completed, the DMA controller
informs the processor by sending an interrupt request. In response, the OS puts the suspended
program in the Runnable state so that it can be selected by the scheduler to continue
execution

Registers in a DMA interface

Two registers are used for storing the starting address and the word count. The third register
contains status and control flags. The R/W bit determines the direction of the transfer. When
this bit is set to 1 by a program instruction, the controller performs a read operation, that is, it
transfers data from the memory to the I/O device. Otherwise, it performs a write operation.
When the controller has completed transferring a block of data and is ready to receive another
command, it sets the Done flag to 1. Bit 30 is the Interrupt-enable flag, IE. When this flag is
set to 1, it causes the controller to raise an interrupt after it has completed transferring a block
of data. Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt
Use of DMA controllers in a computer system

A DMA controller connects a high-speed network to the computer bus. The disk controller,
which controls two disks, also has DMA capability and provides two DMA channels. It can
perform two independent DMA operations, as if each disk had its own DMA controller. The
registers needed to store the memory address, the word count, and so on are duplicated, so
that one set can be used with each device.

To start a DMA transfer of a block of data from the main memory to one of the disks, a
program writes the address and word count information into the registers of the
corresponding channel of the disk controller. It also provides the disk controller with
information to identify the data for future retrieval. The DMA controller proceeds
independently to implement the specified operation. When the DMA transfer is completed,
this fact is recorded in the status and control register of the DMA channel by setting the Done
bit. At the same time, if the IE bit is set, the controller sends an interrupt request to the
processor and sets the IRQ bit. The status register can also be used to record other
information, such as whether the transfer took place correctly or errors occurred.

Memory accesses by the processor and the DMA controllers are interwoven. Requests by
DMA devices for using the bus are always given higher priority than processor requests.
Among different DMA devices, top priority is given to high-speed peripherals such as a disk,
a high-speed network interface, or a graphics display device. Since the processor originates
most memory access cycles, the DMA controller can be said to “steal” memory cycles from
the processor. Hence, this interweaving technique is usually called cycle stealing.
Alternatively, the DMA controller may be given exclusive access to the main memory to
transfer a block of data without interruption. This is known as block or burst mode
Bus Arbitration

The device is that allowed to initiate data transfers on the bus at any given time is called the
bus master. When the current master relinquishes control of the bus, another device can
acquire this status. Bus arbitration is the process by which the next device to become the bus
master is selected and bus mastership is transferred to it. The selection of the bus master must
take into account the needs of various devices by establishing a priority system for gaining
access to the bus.

There are two approaches to bus arbitration: centralized and distributed. In centralized
arbitration, a single bus arbiter performs the required arbitration. In distributed arbitration, all
devices participate in the selection the next bus master.
 o Centralized Arbitration:

The bus arbiter may be the processor or a separate unit connected to the bus. A basic
arrangement in which the processor contains the bus arbitration circuitry. In this case, the
processor is normally the bus master unless it grants bus mastership to one of the DMA
controllers, A DMA controller indicates that it needs to become the bus master by activating
the Bus-Request line, R. The signal on the Bus-Request line is the logical OR of the bus
requests from all the devices connected to it. When Bus-Request is activated, the processor
activates the Bus-Grant signal, BGI, indicating to the DMA controllers that they may use the
bus when it becomes free. This signal is connected to all DMA controllers using a daisy-
chain arrangement. Thus, if DMA controller 1 is requesting the bus, it blocks the propagation
of the grant signal to other devices. Otherwise, it passes the grant downstream by asserting
BG2. The current bus master indicates to all device that it is using the bus by activating
another open-controller line called Bus-Busy, BBSY Hence, after receiving the Bus-Grant
signal, a DMA controller waits for Bus-Busy to become inactive, then assumes mastership of
the bus. At this time. it activates Bus-Busy to prevent other devices from using the bus at the
same
The timing diagram in Figure 4.21 shows the sequence of events for the devices in Figure
4.20 as DMA controller 2 requests and acquires bus mastership and later releases the bus.
During its tenure as the bus master, it may perform one or more data transfer operations,
depending on whether it is operating in the cycle stealing or block mode. After it releases the
bus, the processor resumes bus mastership. This figure shows the causal relationships among
the signals involved in the arbitration process. Details of timing, which vary significantly
from one computer bus to another, are not shown.
 o Distributed arbitration

Distributed arbitration means that all devices waiting to use the bus have equal responsibility
in carrying out the arbitration process, without using a central arbiter. A simple method for
distributed arbitration is illustrated in figure 6. Each device on the bus assigned a 4-bit
identification number. When one or more devices request the bus, they assert the Start
Arbitration signal and place their 4-bit ID numbers on four open collector lines. ARB 0
through ARB 3 A winner is selected as a result of the interaction among the signals
transmitted over those liens by all contenders. The net outcome is that the code on the four
lines represents request that the highest ID number.

▪ The drivers are of the open-collector type.

▪ Hence, if the input to one driver is equal to 1 and the input to another driver connected
to the same bus line is equal to 0 the bus will be in the low-voltage state.
 ▪ In other words, the connection performs an OR function in which logic 1 wins.
▪ Assume that two devices, A and B, having id numbers 5 and 6, respectively, are
requesting the use of the bus.
▪ Device A transmits the pattern 0101
▪ and device B transmits the pattern 0110.
▪ The code seen by both devices is 0111.
▪ Each device compares the pattern on the arbitration lines to its own ID, starting from
the most significant bit.
▪ it detects a difference at any bit position, it disables its drivers at that bit position and
for all lower-order bits.
▪ It does so by placing a 0 at the input of these drivers.
▪ In the case of our example, device A detects a difference on line ARB 1.
▪ Hence, it disables its drivers on lines ARB 1 and ARBO.
▪ This causes the pattern on the arbitration lines to change to 0110, which means that B
has won the contention.
▪ Note that, since the code on the priority lines is 0111 for a short period, device B may
temporarily disable its driver on line ARBO.
▪ However, it will enable this driver again once it sees a 0 on line ARB 1 resulting from
the action by device A.

Decentralized arbitration has the advantage of offering higher reliability, because operation of
the bus is not dependent on any single device.
FLYNNS
CLASSIFICATION:

M.J. Flynn proposed a classification for the organization of a computer system

by the number of instructions and data items that are manipulated
simultaneously.
The sequence of instructions read from memory constitutes an instruction
stream.
The operations performed on the data in the processor constitute a data
stream.

Note: The term 'Stream' refers to the flow of instructions or data.

Parallel processing may occur in the instruction stream, in the data stream, or
both.
 SISD
SISD stands for 'Single Instruction and Single Data Stream'. It represents
the organization of a single computer containing a control unit, a processor
unit, and a memory unit.
Instructions are executed sequentially, and the system may or may not have
internal parallel processing capabilities.
Most conventional computers have SISD architecture like the traditional Von-
Neumann computers.
Parallel processing, in this case, may be achieved by means of multiple
functional units or by pipeline processing.

1. Where, CU = Control Unit, PE = Processing Element, M = Memory

Instructions are decoded by the Control Unit and then the Control Unit sends
the instructions to the processing units for execution.
Data Stream flows between the processors and memory bi-directionally.
Examples:
Older generation computers, minicomputers, and workstations
SIMD
SIMD stands for 'Single Instruction and Multiple Data Stream'. It
represents an organization that includes many processing units under the
supervision of a common control unit.
All processors receive the same instruction from the control unit but operate on
different items of data.
The shared memory unit must contain multiple modules so that it can
communicate with all the processors simultaneously.

SIMD is mainly dedicated to array processing machines. However, vector

processors can also be seen as a part of this group.
 MISD
MISD stands for 'Multiple Instruction and Single Data stream'.
MISD structure is only of theoretical interest since no practical system has been
constructed using this organization.
In MISD, multiple processing units operate on one single-data stream. Each
processing unit operates on the data independently via separate instruction
stream.

1. Where, M = Memory Modules, CU = Control Unit, P = Processor Units

Example:
The experimental Carnegie-Mellon C.mmp computer (1971)
 MIMD
MIMD stands for 'Multiple Instruction and Multiple Data Stream'.
In this organization, all processors in a parallel computer can execute different
instructions and operate on various data at the same time.
In MIMD, each processor has a separate program and an instruction stream is
generated from each program.

1. Where, M = Memory Module, PE = Processing Element, and CU = Control Unit

Examples:
Cray T90, Cray T3E, IBM-SP2
Vector(Array) Processor and
its Types
Array processors are also known as multiprocessors or vector processors. They
perform computations on large arrays of data. Thus, they are used to improve
the performance of the computer.

Types of Array Processors

There are basically two types of array processors:
1.Attached Array Processors

2.SIMD Array Processors

Attached Array Processors

An attached array processor is a processor which is attached to a general

purpose computer and its purpose is to enhance and improve the performance
of that computer in numerical computational tasks. It achieves high
performance by means of parallel processing with multiple functional units.

SIMD Array Processors

SIMD is the organization of a single computer containing multiple processors

operating in parallel. The processing units are made to operate under the
control of a common control unit, thus providing a single instruction stream and
multiple data streams.
A general block diagram of an array processor is shown below. It contains a set
of identical processing elements (PE's), each of which is having a local memory
M. Each processor element includes an ALU and registers. The master control
unit controls all the operations of the processor elements. It also decodes the
instructions and determines how the instruction is to be executed.
The main memory is used for storing the program. The control unit is
responsible for fetching the instructions. Vector instructions are send to all PE's
simultaneously and results are returned to the memory.
The best known SIMD array processor is the ILLIAC IV computer developed by
the Burroughs corps. SIMD processors are highly specialized computers. They
are only suitable for numerical problems that can be expressed in vector or
matrix form and they are not suitable for other types of computations.

Why use the Array Processor

•Array processors increases the overall instruction processing speed.

•As most of the Array processors operates asynchronously from the host
CPU, hence it improves the overall capacity of the system.

•Array Processors has its own local memory, hence providing extra
memory for systems with low memory.
 Multiprocessors
These systems have multiple processors working in parallel that share
the computer clock, memory, bus, peripheral devices etc.
MIMD architecture Interconnection network :allows ‘n’ processors to
access ‘k’ memories. Any processor can access any memory. One
CPU writes some data into memory and another one reads the data
out.
Multiprocessor are classified by the way their memory is organised,
mainly its called as two types
• Tightly coupled multiprocessors (Shared Memory)
• Loosely coupled Multiprocessors (Distributed Memory)

Shared memory- UMA & NUMA :

In the UMA model, the physical memory is evenly shared among the
processors which also have equal latency for every memory word. Uniform
Memory Access.
In NUMA model, each processor is attached with individual memory modules.
Each processor can access both local and other memories but with different
speed.
Non Uniform Memory Access multiprocessors.In both model, any processor
can access any memory without intervention
Distributed memory:
Memory modules are private memories to the processor that are directly
connected to them. It Cannot access a remote processor without remote
computers cooperation. Cooperation takes place using messages – Message
passing protocol.
 Interconnection Networks
•There are several physical forms available for establishing an interconnection
network for multiprocessors.
• Time-shared common bus (single bus)
• Multiport memory
•Crossbar switch
• Multistage switching network
•Hypercube system
1. Time-shared common bus
A common-bus multiprocessor system consists of a number of processors
connected through a common path to a memory unit. Disadv.: Only one
processor can communicate with the memory or another processor at any given
time.

2. Multiport Memory

•A multiport memory system employs separate buses between each

memory module and each CPU.
•The module must have internal control logic to determine which port
will have access to memory at any given time.
• Memory access conflicts are resolved by assigning fixed priorities to
each memory port
3. Crossbar switch

•Consists of a number of crosspoints that are placed at intersections

between processor buses and memory module paths.
•The small square in each crosspoint is a switch that determines the path
from a processor to a memory module.
•Adv.: Supports simultaneous transfers from all memory modules.

4. Multistage Switching Network

The basic component of a multistage network is a two-input, two-output
interchange switch.

5. Hypercube Interconnection

•The hypercube or binary n-cube multiprocessor structure is loosely coupled

system composed of N=2n(2 raised to n) processor interconnected in an n-
dimensional binary cube.
•Each processor forms a node of the cube, in effect it contains not only a CPU
but also local memory and I/O interface.
• Hyper cube structures for n = 1,2,3.

Others…

•Tree
•Ring
• Mesh
 Memory organisation in multiprocessors
UMA architecture
• Locality of reference- Cache memory – speed
•Primary cache- inbuilt on each Processor chip.

NUMA
Parallel Processing
Parallel processing can be described as a class of techniques which enables the system to
achieve simultaneous data-processing tasks to increase the computational speed of a
computer system.

A parallel processing system can carry out simultaneous data-processing to achieve faster
execution time. For instance, while an instruction is being processed in the ALU
component of the CPU, the next instruction can be read from memory.

The primary purpose of parallel processing is to enhance the computer processing

capability and increase its throughput, i.e. the amount of processing that can be
accomplished during a given interval of time.

A parallel processing system can be achieved by having a multiplicity of functional units

that perform identical or different operations simultaneously. The data can be distributed
among various multiple functional units.

The following diagram shows one possible way of separating the execution unit into eight
functional units operating in parallel.

The operation performed in each functional unit is indicated in each block if the diagram:
 o The adder and integer multiplier performs the arithmetic operation with integer numbers.
o The floating-point operations are separated into three circuits operating in parallel.
o The logic, shift, and increment operations can be performed concurrently on different data.
All units are independent of each other, so one number can be shifted while another
number is being incremented.

Pipelining
The term Pipelining refers to a technique of decomposing a sequential process into sub-
operations, with each sub-operation being executed in a dedicated segment that operates
concurrently with all other segments.

The most important characteristic of a pipeline technique is that several computations can
be in progress in distinct segments at the same time. The overlapping of computation is
made possible by associating a register with each segment in the pipeline. The registers
provide isolation between each segment so that each can operate on distinct data
simultaneously.

The structure of a pipeline organization can be represented simply by including an input

register for each segment followed by a combinational circuit.

Let us consider an example of combined multiplication and addition operation to get a

better understanding of the pipeline organization.

The following block diagram represents the combined as well as the sub-operations
performed in each segment of the pipeline.

Registers R1, R2, R3, and R4 hold the data and the combinational circuits operate in a
particular segment.
The output generated by the combinational circuit in a given segment is applied as an
input register of the next segment. For instance, from the block diagram, we can see that
the register R3 is used as one of the input registers for the combinational adder circuit.

In general, the pipeline organization is applicable for two areas of computer design which
includes:

1. Arithmetic Pipeline

2. Instruction Pipeline

Arithmetic Pipeline
Arithmetic Pipelines are mostly used in high-speed computers. They are used to
implement floating-point operations, multiplication of fixed-point numbers, and similar
computations encountered in scientific problems.

To understand the concepts of arithmetic pipeline in a more convenient way, let us

consider an example of a pipeline unit for floating-point addition and subtraction.

The inputs to the floating-point adder pipeline are two normalized floating-point binary
numbers defined as:

X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102

Where A and B are two fractions that represent the mantissa and a and b are the
exponents.

The combined operation of floating-point addition and subtraction is divided into four
segments. Each segment contains the corresponding suboperation to be performed in
the given pipeline. The suboperations that are shown in the four segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
 4. Normalize the result.

We will discuss each suboperation in a more detailed manner later in this section.

The following block diagram represents the suboperations performed in each segment of
the pipeline.
1. Compare exponents by subtraction:
The exponents are compared by subtracting them to determine their difference. The
larger exponent is chosen as the exponent of the result.

The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa
associated with the smaller exponent must be shifted to the right.

2. Align the mantissas:

The mantissa associated with the smaller exponent is shifted according to the difference
of exponents determined in segment one.

X = 0.9504 * 103
Y = 0.08200 * 103

3. Add mantissas:
The two mantissas are added in segment three.

Z = X + Y = 1.0324 * 103

4. Normalize the result:

After normalization, the result is written as:

Z = 0.1324 * 104

Instruction Pipeline
Pipeline processing can occur not only in the data stream but in the instruction stream as
well.

Most of the digital computers with complex instructions require instruction pipeline to
carry out operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following sequence
of steps.
 1. Fetch instruction from memory.
2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

Each step is executed in a particular segment, and there are times when different
segments may take different times to operate on the incoming information. Moreover,
there are times when two or more segments may require memory access at the same
time, causing one segment to wait until another is finished with the memory.

The organization of an instruction pipeline will be more efficient if the instruction cycle is
divided into segments of equal duration. One of the most common examples of this type
of organization is a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and

makes it as a single one. For instance, the decoding of the instruction can be combined
with the calculation of the effective address into one segment.

The following block diagram shows a typical example of a four-segment instruction

pipeline. The instruction cycle is completed in four segments.

What Does Superscalar Processor Mean?

A superscalar processor is a specific type of microprocessor that uses
instruction-level parallelism to help to facilitate more than one instruction
executed during a clock cycle. This depends on analysis of the instructions to
be carried out and the use of multiple execution units to triage these
instructions.

Along with developments like the superscalar design that use microprocessor
innovation to speed up the implementation of multiple instructions, the
microprocessor industry has also seen the emergence of multicore design,
where builders simply incorporate more than one processor or core into a
multicore CPU.

Superscalar is different, because the execution units are not separate

processors. This leads to superscalar being described as “second-generation
RISC” (reduced instruction set computing) – the idea behind RISC is that
computers can operate quickly with a reduced instruction set.
Segment 1:

The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.

Segment 2:

The instruction fetched from memory is decoded in the second segment, and eventually,
the effective address is calculated in a separate arithmetic circuit.

Segment 3:

An operand from memory is fetched in the third segment.

Segment 4:

The instructions are finally executed in the last segment of the pipeline organization.
INSTRUCTION LEVEL PARALLELISM (ILP)

SUPERSCALAR PROCESSOR

SUPER PIPELINED PROCESSORS

MULTICORE SYSTEMS
INSTRUCTION LEVEL PARALLELISM (ILP)

Instruction Level Parallelism (ILP) is used to refer to the architecture in which

multiple operations can be performed parallelly in a particular process, with its own
set of resources – address space, registers, identifiers, state, program counters. It
refers to the compiler design techniques and processors designed to execute
operations, like memory load and store, integer addition, float multiplication, in
parallel to improve the performance of the processors. Examples of architectures
that exploit ILP are VLIWs, Superscalar Architecture.

ILP processors have the same execution hardware as Risc processors. The machines
without ILP have complex hardware which is hard to implement. A typical ILP
allows multiple-cycle operations to be pipelined.

Example :
Suppose, 4 operations can be carried out in single clock cycle. So there will be 4
functional units, each attached to one of the operations, branch unit, and common
register file in the ILP execution hardware. The sub-operations that can be
performed by the functional units are Integer ALU, Integer Multiplication, Floating
Point Operations, Load, Store. Let the respective latencies be 1, 2, 3, 2, 1.
Let the sequence of instructions be –

1. y1 = x1*1010
2. y2 = x2*1100
3. z1 = y1+0010
4. z2 = y2+0101
5. t1 = t1+1
6. p = q*1000
7. clr = clr+0010
8. r = r+0001
Fig. a shows sequential execution of operations.
Fig. b shows use of ILP in improving performance of the processor

The ‘nop’s in the above diagram are used to show idle time of processor. Since
latency of floating-point operations is 3, hence multiplications take 3 cycles and
processor has to remain idle for that time period. However, in Fig. b processor can
utilize those nop’s to execute other operations while previous ones are still being
executed.
While in sequential execution, each cycle has only one operation being executed, in
processor with ILP, cycle 1 has 4 operations, cycle 2 has 2 operations. In cycle 3
there is ‘nop’ as the next two operations are dependent on first two multiplication
operations. The sequential processor takes 12 cycles to execute 8 operations
whereas processor with ILP takes only 4 cycles.

TECHNIQUES THAT ARE USED TO EXPLOIT ILP

1.Loop level parallelism

2.Instruction pipelining

3.Out-of-order execution

4.Register renaming

5.Branch prediction
LOOP LEVEL PARALLELISM

Loop-level parallelism is a form paralleism in software programmining that is

concerned with extracting parallel tasks from loops. The opportunity for loop-
level parallelism often arises in computing programs where data is stored
in random access structures. Where a sequential program will iterate over the
data structure and operate on indices one at a time, a program exploiting loop-
level parallelism will use multiple threads or process which operate on some
or all of the indices at the same time. Such parallelism provides a speedup to
overall execution time of the program, typically in line with Amdahl's law.
For simple loops, where each iteration is independent of the others, loop-level
parallelism can be embarrassingly parallel, as parallelizing only requires
assigning a process to handle each iteration. However, many algorithms are
designed to run sequentially, and fail when parallel processes race due to
dependence within the code. Sequential algorithms are sometimes applicable
to parallel contexts with slight modification. Usually, though, they
require process synchronization. Synchronization can be either implicit,
via message passing, or explicit, via synchronization primitives
like semaphores.
Consider the following code operating on a list L of length n .

for (int i = 0; i < n; i++) {

S1: L[i] = L[i] + 10;
}

Each iteration of the loop takes the value from the current index of L , and
increments it by 10. If statement S1 takes T time to execute, then the loop
takes time n * T to execute sequentially, ignoring time taken by loop
constructs. Now, consider a system with p processors where p > n .
If n threads run in parallel, the time to execute all n steps is reduced to T .
Less simple cases produce inconsistent, i.e. non-serializable outcomes.
Consider the following loop operating on the same list L .

for (int i = 1; i < n; i++) {

S1: L[i] = L[i - 1] + 10;
}
Each iteration sets the current index to be the value of the previous plus ten.
When run sequentially, each iteration is guaranteed that the previous iteration
will already have the correct value. With multiple threads, process
scheduling and other considerations prevent the execution order from
guaranteeing an iteration will execute only after its dependence is met. It very
well may happen before, leading to unexpected results. Serializability can be
restored by adding synchronization to preserve the dependence on previous
iterations.

INSTRUCTION PIPELINING
Pipeline processing can occur not only in the data stream but in the instruction stream as well.

Most of the digital computers with complex instructions require instruction pipeline to carry
out operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following sequence of
steps.

1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

Each step is executed in a particular segment, and there are times when different segments
may take different times to operate on the incoming information. Moreover, there are times
when two or more segments may require memory access at the same time, causing one
segment to wait until another is finished with the memory.

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The organization of an instruction pipeline will be more efficient if the instruction cycle is
divided into segments of equal duration. One of the most common examples of this type of
organization is a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and makes it
as a single one. For instance, the decoding of the instruction can be combined with the
calculation of the effective address into one segment.
The following block diagram shows a typical example of a four-segment instruction pipeline.
The instruction cycle is completed in four segments.
Segment 1:

The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.

Segment 2:

The instruction fetched from memory is decoded in the second segment, and eventually, the
effective address is calculated in a separate arithmetic circuit.

Segment 3:

An operand from memory is fetched in the third segment.

Segment 4:

The instructions are finally executed in the last segment of the pipeline organization.

OUT-OF-ORDER EXECUTION
In computer engineering, out-of-order execution (or more formally dynamic execution) is
a paradigm used in most high-performance central processing units to make use of instruction cycles that
would otherwise be wasted. In this paradigm, a processor executes instructions in an order governed by
the availability of input data and execution units. rather than by their original order in a program. In
doing so, the processor can avoid being idle while waiting for the preceding instruction to complete and
can, in the meantime, process the next instructions that are able to run immediately and independently.

REGISTER RENAMING
Register renaming is a form of pipelining that deals with data dependences
between instructions by renaming their register operands. An assembly
language programmer or a compiler specifies these operands
using architectural registers - the registers that are explicit in the instruction
set architecture. Renaming replaces architectural register names by, in effect,
value names, with a new value name for each instruction destination operand.
This eliminates the name dependences (output dependences and
antidependences) between instructions and automatically recognizes true
dependences.
The recognition of true data dependences between instructions permits a
more flexible life cycle for instructions. By maintaining a status bit for each
value indicating whether or not it has been computed yet, it allows the
execution phase of two instruction operations to be performed out of order
when there are no true data dependences between them. This is called out-of-
order execution.

BRANCH PREDICTION
Branch prediction is a technique used in CPU design that attempts to guess the outcome of
a conditional operation and prepare for the most likely result. A digital circuit that performs
this operation is known as a branch predictor. It is an important component of modern
CPU architectures, such as the x86.

How does it work?

When a conditional operation such as an if…else statement needs to be processed,
the branch predictor "speculates" which condition most likely will be met. It
then executes the operations required by the most likely result ahead of time. This
way, they're already complete if and when the guess was correct. At runtime, if the
guess turns out not to be correct, the CPU executes the other branch of operation,
incurring a slight delay. But if the guess was correct, speed is significantly increased.

The first time a conditional operation is seen, the branch predictor does not have
much information to use as the basis of a guess. But the more frequently the same
operation is used, the more accurate its guess can become.

LIMITATIONS: DEPENDENCES AND HAZARDS

If two instructions are parallel, they can be executed simultaneously

in a pipeline without causing any stalls, assuming the pipeline has
sufficient resources.

Two dependent instructions must be executed in order, but can often

be partially overlapped.
Three types of dependences:

1.Data dependences

2.Name dependences

3.Control dependences.

DATA DEPENDENCE
A data dependency in computer science is a situation in which a program
statement (instruction) refers to the data of a preceding statement. In
compiler theory, the technique used to discover data dependencies among
statements (or instructions) is called dependence analysis

An instruction j is data dependent on instruction i if either of the following

holds:

• Instruction i produces a result that may be used by instruction j, or

• Instruction j is data dependent on instruction k, and instruction k is data
dependent on instruction i.

The second condition simply states that one instruction is dependent on

another if there exists a chain of dependences of the first type between the
two instructions. This dependence chain can be as long as the entire program.

For example, consider the following code sequence that increments a vector of
values in memory (starting at 0(R1) and with the last element at 8(R2)) by a
scalar in register F2:
Loop: L.D F0,0(R1) ; F0=array element ADD.D F4,F0,F2 ; add scalar in F2 S.D
F4,0(R1) ;store result DADDUI R1,R1,#-8 ;decrement pointer 8 bytes (/e BNE
R1,R2,LOOP ; branch R1!=zero
The dependence implies that there would be a chain of one or more data
hazards between the two instructions. Executing the instructions
simultaneously will cause a processor with pipeline interlocks to detect a
hazard and stall, thereby reducing or eliminating the overlap. Depend ences
are a property of programs.

Whether a given dependence results in an actual hazard being detected and

whether that hazard actually causes a stall are properties of the pipeline
organization. This difference is critical to understanding how instruction-level
parallelism can be exploited.

The presence of the dependence indicates the potential for a hazard, but the actual hazard
and the length of any stall is a property of the pipeline. The importance of the data
dependences is that a dependence

(1) indicates the possibility of a hazard,

(2) Determines the order in which results must be calculated, and
(3) Sets an upper bound on how much parallelism can possibly be exploited

NAME DEPENDENCES

The name dependence occurs when two instructions use the same register or
memory location, called a name, but there is no flow of data between the
instructions associated with that name.
There are two types of name dependences between an instruction i that precedes
instruction j in program order:
• An antidependence between instruction i and instruction j occurs when
instruction j writes a register or memory location that instruction i reads. The
original ordering must be preserved to ensure that i reads the correct value.

• An output dependence occurs when instruction i and instruction j write the

same register or memory location. The ordering between the instructions must be
preserved to ensure that the value finally written corresponds to instruction j.
Both anti-dependences and output dependences are name dependences, as
opposed to true data dependences, since there is no value being transmitted
between the instructions. Since a name dependence is not a true dependence,
instructions involved in a name dependence can execute simultaneously or be
reordered, if the name (register number or memory location) used in the
instructions is changed so the instructions do not conflict.
This renaming can be more easily done for register operands, where it is called
register renaming. Register renaming can be done either statically by a compiler
or dynamically by the hardware. Before describing dependences arising from
branches, let’s examine the relationship between dependences and pipeline data
hazard.

CONTROL DEPENDENCES:

A control dependence determines the ordering of an instruction, i, with respect to

a branch instruction so that the instruction i is executed in correct program order.
Every instruction, except for those in the first basic block of the program, is
control dependent on some set of branches, and, in general, these control
dependences must be preserved to preserve program order. One of the simplest
examples of a control dependence is the dependence of the statements in the
“then” part of an if statement on the branch. For example, in the co de segment:
if p1 { S1;
};
if p2 { S2;
}

S1 is control dependent on p1, and S2is control dependent on p2 but not on p1. In
general, there are two constraints imposed by control dependences:

1. An instruction that is control dependent on a branch cannot be moved before

the branch so that its execution is no longer controlled by the branch. For
example, we cannot take an instruction from the then-portion of an if-statement
and move it before the if- statement.

2. An instruction that is not control dependent on a branch cannot be moved

after the branch so that its execution is controlled by the branch. For example, we
cannot take a statement before the if-statement and move it into the then-
portion.

Control dependence is preserved by two properties in a simple pipeline, First,

instructions execute in program order. This ordering ensures that an instruction
that occurs before a branch is executed before the branch. Second, the detection
of control or branch hazards ensures that an instruction that is control dependent
on a branch is not executed until the branch direction is known.

HAZARDS
Hazard is the situation that prevent the next instruction in the instruction
stream from executing during its designated clock cycle. Hazards reduce the
performance from the ideal speedup gained by pipelining.

There are three classes of Hazards:

1. Structural Hazards: It arise from resource conflicts when the

hardware cannot support all possible combinations of
instructions simultaniously in ovelapped execution.

2. Data Hazards: It arise when an instruction depends on the

results of previous instruction in a way that is exposed by the
ovelapping of instructions in the pipeline.

3. Control Hazards: It arise from the pipelining of branches and

other instructions that change the PC

ARCHITECTURE :
Instruction Level Parallelism is achieved when multiple operations are performed in
single cycle, that is done by either executing them simultaneously or by utilizing
gaps between two successive operations that is created due to the latencies.

Now, the decision of when to execute an operation depends largely on the

compiler rather than hardware. However, extent of compiler’s control depends on
type of ILP architecture where information regarding parallelism given by compiler
to hardware via program varies. The classification of ILP architectures can be done
in the following ways –
1. Sequential Architecture :
Here, program is not expected to explicitly convey any information
regarding parallelism to hardware, like superscalar architecture.
 2. Dependence Architectures :
Here, program explicitly mentions information regarding dependencies
between operations like dataflow architecture.

3. Independence Architecture :
Here, program gives information regarding which
operationsareindependent of each other so that they can be executed in
stead of the ‘nop’s.

In order to apply ILP, compiler and hardware must determine data dependencies,
independent operations, and scheduling of these independent operations,
assignment of functional unit, and register to store data.
SUPERSCALAR PROCESSOR
A superscalar processor is a specific type of microprocessor that uses instruction-level parallelism to
help to facilitate more than one instruction executed during a clock cycle. This depends on analysis
of the instructions to be carried out and the use of multiple execution units to triage these
instructions.
SUPERSCALAR DESIGN TECHNIQUES TYPICALLY INCLUDE
1.parallel instruction decoding

2.register renaming

3.out-of-order execution

4.ILP

along with complementing design techniques such as pipelining,

caching, branch prediction, and multi-core.

A typical superscalar processor today is the Intel Core i7

processor

SUPER PIPELINED PROCESSORS

A superscalar processor is a CPU that implements a form of parallelism called instruction-

level parallelism within a single processor. In contrast to a scalar processor that can execute
at most one single instruction per clock cycle, a superscalar processor can execute more
than one instruction during a clock cycle by simultaneously dispatching multiple instructions
to different execution units on the processor. It therefore allows for more throughput (the
number of instructions that can be executed in a unit of time) than would otherwise be
possible at a given clock rate. Each execution unit is not a separate processor (or a core if
the processor is a multi-core processor), but an execution resource within a single CPU such
as an arithmetic logic unit.

• Super-pipelining attempts to increase performance by

reducing the clock cycle time because many pipeline stages
need less than half a clock time.

• It achieves that by making each pipeline stage very shallow,

resulting in a large number of pipe stages.

• Deeper pipelines

• A shorter clock cycle means a faster clock.

• A superpipelined architecture splits a pipeline phase.

SUPER PIPELINED PROCESSORS VS SUPER
SCALAR

Super-pipelining attempts to increase performance by reducing the clock cycle

time. It achieves that by making each pipeline stage very shallow, resulting in a
large number of pipe stages. A shorter clock cycle means a faster clock. As long as
your cycles per instruction (CPI) doesn’t change, a faster clock means better
performance. Super-pipelining works best with code that doesn’t branch often, or
has easily predicted branches.
Superscalar attempts to increase performance by executing multiple instructions
in parallel. If you can issue more instructions every cycle—without decreasing
clock rate—then your CPI decreases, therefore increasing performance.
Superscalar breaks into two broad flavors: In-order and out-of-order. In-order
superscalar mainly provides benefit to code with instruction-level parallelism
among a small window of consecutive instructions. Out-of-order superscalar
allows the pipeline to find parallelism across larger windows of code, and to hide
latencies associated with long-running instructions. (Example: load instructions
that miss the cache.) In-order vs. out-of-order form a continuum: Some
processors have in-order issue, but out-of-order completion, for example.
Summarizing in a few words: Super-pipelining seeks to improve the sequential
instruction rate, while superscalar seeks to improve the parallel instruction rate.
Most modern processors are both superscalar and super-pipelined. They have
deep pipelines to achieve high clock rates, and wide instruction issue to make use
of instruction level parallelism.
MULTICORE SYSTEMS

The concept of multicore technology is mainly centered on the possibility of parallel

computing, which can significantly boost computer speed and efficiency by including two or
more central processing units (CPUs) in a single chip. This reduces the system's heat and
power consumption. This means much better performance with less or the same amount of
energy.

The architecture of a multicore processor enables communication between all available

cores to ensure that the processing tasks are divided and assigned accurately. At the time of
task completion, the processed data from each core is delivered back to the motherboard
by means of a single shared gateway. This technique significantly enhances performance
compared to a single-core processor of similar speed.

APPLICATIONS
Multicore technology is very effective in challenging tasks and applications, such as
encoding, 3-D gaming and video editing
PREVIOUS YEAR QUESTIONS
1.define superscalar (3 marks) (2019)
2.define hazards (3 marks) (2020)
3.what is an instruction pipeline (3marks) (2020)