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Tutorial -5

The document is a tutorial sheet for a course in Analogue Electronics at Jaypee Institute of Information Technology, focusing on MOS differential pairs. It includes a series of problems related to the analysis and design of MOS differential amplifiers, covering topics such as bias currents, voltage gains, and the effects of mismatches in transistor parameters. Each problem requires calculations based on given parameters and conditions to determine various electrical characteristics of the circuits.

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1 views

Tutorial -5

The document is a tutorial sheet for a course in Analogue Electronics at Jaypee Institute of Information Technology, focusing on MOS differential pairs. It includes a series of problems related to the analysis and design of MOS differential amplifiers, covering topics such as bias currents, voltage gains, and the effects of mismatches in transistor parameters. Each problem requires calculations based on given parameters and conditions to determine various electrical characteristics of the circuits.

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alghorither
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY

Electronics and Communication Engineering


Analogue Electronics (15B11EC411)
Tutorial Sheet: 5

1. For the MOS differential pair with a common-mode voltage VCM applied, as shown in Fig. 1, let
VDD=VSS= 2.5 V, k'n(W/L) = 3 mA/V2. Vt = 0.7 V, I= 0.2 mA. and RD= 5 kΩ, and neglect channel-
length modulation.
(a) Find VOV and VGS for each transistor.
(b) For vCM= 0, find vS, iD1, iD2, vD1, and vD2.
(c) Repeat (b) for vCM = +1 V.
(d) Repeat (b) for vCM = -1 V.
(e) What is the highest value of vCM for which Q1 and Q2 remain in saturation?
(f) If current source I requires a minimum voltage of 0.3 V to operate properly, what is the lowest
value allowed for vs and hence for vCM ?

Fig. 1
2. A MOS differential pair is operated at a bias current I of 0.4 mA. if µnCox = 0.2 mA/V2, find the
required values of W/L and the resulting gm if the MOSFETs are operated at VOV = 0.2, 0.3, and 0.4 V.
For each value, give the maximum |vid| for which the term involving V2id , namely ((vid/2)/VOV)2 ,
limited to 0.1 .
3. Consider the differential amplifier specified in Problem 1 with G2 grounded and vG1 = vid. Let vid be
adjusted to the value that causes iD1 =0.11 mA and iD2 = 0.09 mA. Find the corresponding values of
vGS2, vS, vGS1, and hence vid. What is the difference output voltage vD2 - vD1 ?What is the voltage gain
(vD2 - vD1)/vid ?What value of vid results in iD1= 0.09 mA and iD2 = 0.11 mA?
4. An NMOS differential amplifier utilizes a bias current of 200 µA. The devices have Vt = 1 V,W=
100 µm, and L = 1.6 µm, in a technology for which µnCox = 90 mA/V2. Find VGS, gm and the value of
vid for full-current switching. To what value should the bias current be changed in order to double the
value of vid for full-current switching?
5. A MOS differential pair is operated at a total bias current of 0.8 mA. Using transistors with a W/L
ratio of 100, µnCox = 0.2 mA/V2, VA = 20 V, and RD = 5 kΩ. Find VOV , gm, ro and Ad .
6. A MOS differential pair operated at a bias current of 0.8 mA employs transistors with W/L = 100
and µnCox = 0.2 mA/V2, using RD = 5 kΩ, and RSS = 25 kΩ.
(a) Find the differential gain, the common-mode gain, and the common-mode rejection ratio (in dB) if
the output is taken singlc-endedly and the circuit is perfectly matched.
(b) Repeal (a) when ihe output is taken differentially.
(c) Repeat (a) when the output is taken differentially but the drain resistances have a 1% mismatch.
7. A design error has resulted in a gross mismatch in the circuit of Fig. 2 Specifically; Q2 has twice the
W/L ratio of Q1. If vid is a small sine-wave signal, find:
(a) ID1 and ID2.
(b) VOV for each of Q1 and Q2.
(c) The differential gain Ad in terms of Rd, I, and VOV.

Fig. 2
8. For the differential amplifier shown in Fig. 3, let Q1 and Q2 have k'p(W/L) = 3.5 mA/V2, and assume
that the bias current source has an output resistance of 30 kΩ. Find Vov, gm, |Ad|, |A|, and the CMRR
(in dB) obtained with the output taken differentially. The drain resistances are known to have a
mismatch of 2%.
Fig. 3
9. An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 kΩ ± 1%. For
the pair k'n(W/L) = 4 mA/V2. A decision is to be made concerning the bias current I to be used,
whether 200 µA or 400 µA. For differential output, contrast the differential gain and input offset
voltage for the two possibilities.
10. An NMOS differential pair operating at a bias current I of 100 µA uses transistors for which
k'n(W/L) = 100 mA/V2and W/L = 20, with Vt = 0.8 V. Find the three components of input offset
voltage under the conditions that ∆RD/RD = 5%, ∆(W/L)/(W/L) = 5%, and ∆Vt = 5 mV. In the worst
case, what might the total offset be? For the usual case of the three effects being independent, what is
the offset likely to be?

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