Name : Atif zaman

Facult Roll numbers : 779

Semester :
y of 4th
Submitted to ;
Electr Engr Khalid
Rabbani
ical Submitted by :
Atif zaman
Engin Lab NO ; 04
Season ; 2018-2022
Date : 23.04.2020
Department ; FET

EXPERIMENT NO: 4
LAB 5; TO STUDY THE COMMON SOURCE AMPLIFIERS

OBJECTIVE:
1. To about the basic common amplifiers.
 2. To learn the about the wave form of common amplifer.
3. To draw the circuit of the self , fixed bias and the voltage divider bias.

SELF BIAS

APPARATUS REQUIRED:
 Junction field effect transistor (n-channel)
 DC voltage sources
 Power supply
 Resistors
 capacitores
 Connecting Leads

THEORY:
The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage sources. The self-
bias configuration of requires only one dc supply to establish the desired operating point.
The capacitor C S across the source resistance
assumes its open-circuit equivalence for dc,
allowing R S to define the operating point.
Under ac conditions, the capacitor assumes the
short-circuit state and “short circuits” the effects
of R S . If left in the ac, gain will be reduced, as
will be shown in the paragraphs to follow. The
JFET equivalent circuit is established in Fig. and
carefully redrawn in Fig. . Since the resulting
configuration is the same as appearing in Fig. ,
the resulting equations for Z i , Z o , and A v
will be the same.

MATHEMATICALLY:
Zi Zi = RG
Zo Zo = rdRD
Zo RD
Av = -gm(rdRD)
Av = -gmRD

Z i Due to the open-circuit condition between the gate and the output network, the input remains the
following:
Zi = RG
The output impedance is defined by
Vo
Zo = Vi=0
Io

Setting Vi = 0 V in F ig. results in the gate terminal being at ground potential (0 V). The voltage
across R G is then 0 V, and R G has been effectively “shorted out” of the picture. Applying
Kirchhoff’s current law results in Io + ID = gmVgs with Vgs = -(Io + ID)RS

EXAMPLE 8.8:
The self-bias configuration of Example 7.2 has an operating point defined by VGSQ = -2.6
V and IDQ = 2.6 mA, with IDSS = 8 mA and VP = -6 V. The network is redrawn as
Fig. 8.20 with an applied signal V i . The value of g os is given as 20 mS.
a. Determine g m .
b. Find r d .
c. Find Z i .
d. Calculate Z o with and without the effects of r d .
Compare the results.
 e. Calculate A v with and without the effects of r d
. Compare the results.

Circuit Diagram
LAB 5; TO STUDY THE COMMON SOURCE AMPLIFIERS
V: 6.60 mV
V(p-p): 18.6 mV
VDD V(rms): 6.60 mV
20V V(dc): 22.6 uV
I: 0 A
I(p-p): 0 A
R1 I(rms): 0 A XSC1
Self Bias 3.3kΩ I(dc): 0 A
Freq.: 1.00 kHz
C2
Ext Trig
+
Name Atif Zaman Probe2 _

Q1 22µF A B
+ _ + _

C1

10µF 2N3821
V2

1mVrms R2
1kHz 1MΩ R3 C3
0° 1kΩ 22µF

OUTPUT;
 Voltage Divider Bias

CIRCUIT
 LAB 5; TO STUDY THE COMMON SOURCE AMPLIFIERS
V: -6.23 mV
V(p-p): 16.7 mV
VDD V(rms): 5.91 mV
20V V(dc): 35.2 uV
I: 0 A
I(p-p): 0 A
R1 I(rms): 0 A XSC1
R4
Voltage divider Bias 2.2kΩ I(dc): 0 A
2MΩ Freq.: 1.00 kHz
C2
Ext Trig
+
Name Atif Zaman Probe2 _

Q1 2.2µF A B
+ _ + _

C1

10µF 2N3821
V2

1mVrms R2
1kHz 270kΩ R3 C3
0° 1kΩ 22µF

GRAPH

FIXED BIAS
Zi = RG

Zo = RDrd

Zo = RD rdÚ10RD

Vo = -gmVgs(rdRD)

but Vgs = Vi

and Vo = -gmVi(rdRD)
Circuit Diagram
LAB 5; TO STUDY THE COMMON SOURCE AMPLIFIERS
V: 9.37 mV
V(p-p): 18.9 mV
VDD V(rms): 6.67 mV
20V V(dc): -2.01 uV
I: 0 A
I(p-p): 0 A
R1 I(rms): 0 A XSC1
Fixed Bias 3.3kΩ I(dc): 0 A
Freq.: 1.00 kHz
C2
Ext Trig
+
Name Atif Zaman Probe2 _

Q1 22µF A B
+ _ + _

C1

10µF 2N3821
V2

1mVrms R2
1kHz 1MΩ
0°
V1
2V

Graph
CONCLUSION:
I Learnt from this experiment that how the amplification work on Fixed bias, self bias and the
voltage divider bias . it amplify the input voltage. It show the amplification. Now we are able to
draw the diagram.