ELC_1101_Unit1
ELC_1101_Unit1
Electronics Paper – I
Fundamentals of Logic Circuit Design
SEM-I & II Electronics Courses
Reference Books
https://www.pdfdrive.com/digital-principles-
and-applications-d158092173.html
Course Learning Outcomes:
Sine wave is one of the commonly referred Digital signal is rectangular or pulsed wave
Analog signals. signal.
Analog signals describe the behavior of the Digital signal describes the behavior of the signal
wave with respect to amplitude, time period, with respect to the rate of a bits as well as bit
& phase of the signal. interval.
Analog signal amplitude range may not be Digital signal amplitude is fixed which is low
fixed. voltage i. e. logic 0 and high voltage i.e. logic 1.
Other labels for the true and false states are shown in
the table.
Logic states
True False
1 0
High Low
+Vs 0V
On Off
Logic gate’s ICs (Integrated Circuits) are built using different logic
families like TTL (Transistor-Transistor Logic), CMOS
(Complementary Metal Oxide semiconductor) etc. in which BJT’s
FET’s ( Field Effect Transistor) and MOSFET’s (Metal Oxide
Semiconductor FET) etc.
Truth Table:
The table used to represent the Boolean expression of a logic gate
function is commonly called a Truth Table.
A logic gate truth table shows each possible input combination to the
gate or circuit with the resultant output depending upon the
combination of these input(s).
Boolean Expression:
The relation between inputs and the output can be expressed
mathematically by means of the Boolean expression.
Classification of Logic Gates
NOT Gate- The basic logic gate having one input (A) and one
output (Y)
The output of NOT gate is high (1) if its input is low (0).
The output of NOT gate is low (0) if its input is high (1).
It is clear that NOT gate simply inverts the given input.
Since NOT gate simply inverts the given input, therefore it is also
known as Inverter Gate.
Logic Symbol- The logic symbol for NOT Gate is as shown below
Truth Table-
The truth table for NOT Timing Diagram-
Gate is as shown below-
AND Gate
The output of AND gate is high (1) if all of its inputs are high (1).
The output of AND gate is low (0) if at least one of its inputs is low
(0).
Logic Symbol
The logic symbol for AND Gate is as shown below
Truth Table
The truth table for AND Gate is Timing Diagram
as shown below-
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate-
The output of OR gate is high (1) if any one or more of its inputs
are high (1).
The output of OR gate is low (0) if all of its inputs are low (0).
Logic Symbol-
Truth Table-
The truth table for OR
Timing Diagram-
Gate is as shown below-
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1
Universal Logic Gates-
The output of NAND gate is high (1) if at least one of its inputs
is low (0).
The output of NAND gate is low (0) if all of its inputs are high
(1).
Diagram1
Logic Symbol-
The logic symbol for NAND Gate is as shown below-
Truth Table
The truth table for NAND Timing Diagram
Gate is as shown below-
NOR Gate-
• A NOR Gate is constructed by connecting a NOT Gate at the output
terminal of the OR Gate as shown in diagram1.
•The output of NOR gate is high (1) if all of its inputs are low (0).
•The output of NOR gate is low (0) if any of its inputs is high (1).
Logic Symbol
The logic symbol for Ex Gate is as shown below-
Truth Table
The truth table for XOR Gate is as
shown below-
Timing Diagram
Exclusive NOR - EXNOR Gate (XNOR)-
• The XNOR gate is derived gate.
• In two i/p XNOR gate, when both the inputs are identical (A =B),
the output is HIGH (1).
• When the inputs are not identical (A ≠ B), the output is LOW (0).
Logic Symbol
The logic symbol for Ex NOR Gate is as shown below-
Truth Table-
The truth table for XNOR Timing Diagram-
Gate is as shown below-
De-Morgan’s First Theorem
It states that complement of sum is equal to the product of their
complements.
In equation it stated as: A B A B
When A= 0 Y= 1
When A= 1 Y=0
When A= 0 and B = 0 Y= 0
When A= 0 and B = 1 Y=0
When A = 1 and B = 0 Y=0
When A = 1 and B = 1 Y=1
When A= 0 and B = 0 Y= 0
When A= 0 and B = 1 Y=1
When A = 1 and B = 0 Y=1
When A = 1 and B = 1 Y=0
When A= 0 and B = 0 Y= 1
When A= 0 and B = 1 Y=0
When A = 1 and B = 0 Y=0
When A = 1 and B = 1 Y=1
Y=
Ref: https://www.lancasterschools.org/cms/lib/NY19000266/Centricity/Domain/1055/UniversalNOR.pdf
OR Gate: Using Only NOR Gates
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
AND Gate: Using Only NOR Gates
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
NAND Gate: Using Only NOR Gates
When A= 0 and B = 0 Y= 1
When A= 0 and B = 1 Y=1
When A = 1 and B = 0 Y=1
When A = 1 and B = 1 Y=0
When A= 0 and B = 0 Y2 = 0
When A= 0 and B = 1 Y2 = 1
When A = 1 and B = 0 Y2 = 1
When A = 1 and B = 1 Y2 = 0
When A= 0 and B = 0 Y= 1
When A= 0 and B = 1 Y=0
When A = 1 and B = 0 Y=0
When A = 1 and B = 1 Y=1
Q.1 Explain with appropriate wave forms analog and digital signals.
Q.2 Explain basic logic gates.
Q.3 How are AND & OR gates are obtained using only NAND
gates?
Q.4 How are AND & OR gates are obtained using only NOR
gates?
Q.5 Explain NAND / NOR gate as universal gate.
Q. 6 How are XOR & XNOR gates designed using NAND / NOR
gates?
Q. 7 State and prove De-Morgan’s theorems.
Q. 8 Explain derived gates.
Q. 9 What is difference between analog and digital signals?
Short answer type questions (3 Marks each)