MEMORY INTERFACING PDF 15

What is Address Decoding?

Address decoding is the process of identifying which specific memory chip or I/O device should
respond to a given address sent by the CPU.

When the CPU wants to read from or write to memory or a device, it puts an address on the
address bus. But there might be many devices or memory chips connected. So we need a way
to ensure only the correct one responds — this is the job of address decoding.

How It Works

We use logic gates or decoders to check specific bits of the address. Based on those bits, the
decoder activates an enable signal for just one memory or I/O device.

There are different methods:

• Full decoding: All address lines are used to make every address unique.
• Partial decoding: Only some address lines are used, which can save hardware but may
cause conflicts if not designed carefully.

What happens after decoding?

Once the decoder recognizes the address range:

• It sends an enable signal to the correct memory chip or I/O device.

• That device is now allowed to communicate with the CPU.
• All other devices stay disabled (inactive), so there is no conflict.

Simple Flow:

1. CPU → puts address on the address bus (e.g., 0x9000).

2. Decoder circuit → checks this address.
3. Decoder → sends an enable signal to the matching chip (e.g., RAM).
4. That chip → responds and reads/writes data through the data bus.

Q: How a NAND gate can be used as a simple address decoder to

enable a 2716 EPROM chip.
Step 1: What is a 2716 EPROM?

• The 2716 EPROM is a 2 KB memory chip (2 × 1024 = 2048 bytes).

• 2716 => 27 EPROM, 16 Kb = 16/8 KB = 2 KB = 2.2^10 B = 2^11 B => 11 address lines,
8 data lines
 • It needs 11 address lines (A0–A10) to access 2048 locations.
• It has a chip enable (CE) and output enable (OE) input.
• The chip responds only when CE is low (0).

Step 2: Memory Map and Address Range

Let’s say you want to place the 2716 at address 0x0000 to 0x07FF in your system.

• This is a 2 KB block, so we only need A0 to A10 for internal addressing.

• The higher address lines (A11 to A15) should all be 0 for this block.

So:

Address Lines Value Needed

A15 to A11 11111
A10 to A0 any (used inside 2716)

Step 3: Use NAND Gate for Address Decoding

We can use a NAND gate to check if A15–A11 are all 0.

• If all those inputs are 1, the output of the NAND gate will be 0.
• we need CE = 0 to activate the EPROM.
• If there’s no 1 then we need to put the inverter on that specific address line before nand
gate.

.
Step 4: Connect Other Pins

• A0–A10 → from CPU address bus → to EPROM address inputs.

• D0–D7 → EPROM data output → to CPU data bus.
• OE → connect to RD signal from CPU (to control when data is read).
• CE → from NAND output (decoder output).

Q: now design an address decoder using NAND gates to enable a 2716 EPROM (2 KB)
placed at the top 2 KB of memory, i.e., address range 0xFF800 to 0xFFFFF.

Step 1: Understand the Address Range

The 8086 microprocessor has a 20-bit address bus, so address range is:
0x00000 to 0xFFFFF (1 MB total)

We want the EPROM to be enabled when the address is from:

0xFF800 to 0xFFFFF

This is the last 2 KB in the memory space.

Step 2: What Address Bits Are Used?

• 2 KB = 2048 bytes → needs 11 address lines (A0–A10)

• These go directly to the 2716 EPROM address inputs

The higher bits (A11 to A19) will be used for decoding.

Let’s write the binary of the start and end address:

Start: 0xFF800
= 1111 1111 1000 0000 0000
A19...A0

End: 0xFFFFF
= 1111 1111 1111 1111 1111

So:

• A19–A11 must all be 1

• A10–A0 can be anything (used inside EPROM)

Step 3: Use NAND Gate for Decoding

We want the chip to be enabled only when A19–A11 = 1

So:
 • Connect A19, A18, A17, A16, A15, A14, A13, A12, A11 (9 lines) to a 9-input NAND
gate.
• NAND of all 1s = 0

Now:

• If address is between FF800 and FFFFF → A19–A11 = 1 → NAND = 0 → CE = 0 →

EPROM responds
• Any other address → NAND = 1 → Inverter = 0 → CE = 1 → EPROM disabled

Step 4: Connect Other Pins

• A0–A10 → CPU address bus → EPROM address lines

• D0–D7 → EPROM data output → CPU data bus
• OE → connect to RD (read signal) from CPU
• CE → from the output of the decoder circuit

Q: now go through the case of placing a 2716 EPROM (2 KB) in the address range:

Address Range: 0xFF000 to 0xFF7FF

Step 1: Understand the Range

• This range is 2 KB wide → needs 11 address lines (A0–A10) for internal access in the
2716.
• So we will decode the higher address lines A11–A19 to enable the chip.
Step 2: Write Binary of Start and End Addresses

Start: 0xFF000
= 1111 1111 0000 0000 0000
End: 0xFF7FF
= 1111 1111 0111 1111 111

What is the 74138?

The 74LS138 is a 3-to-8 line decoder/demultiplexer.

It takes 3 binary input bits and activates one of 8 outputs, depending on the input combination.

Pin Configuration of 74138

Pin Name Function

1 G1 Enable (active HIGH)
Pin Name Function
2 A Input (LSB)
3 B Input
4 C Input (MSB)
5 G2A Enable (active LOW)
6 G2B Enable (active LOW)
7 Y7 Output (active LOW)
8 GND Ground
9 Y6 Output (active LOW)
10 Y5 Output (active LOW)
11 Y4 Output (active LOW)
12 Y3 Output (active LOW)
13 Y2 Output (active LOW)
14 Y1 Output (active LOW)
15 Y0 Output (active LOW)
16 Vcc +5V Power

Enable Conditions

The decoder only works when the enables are:

• G1 = 1
• G2A = 0
• G2B = 0

Otherwise, all outputs stay HIGH (inactive).

How It Works

Inputs C, B, A form a 3-bit binary number:

• 000 → Y0 is LOW (selected)

• 001 → Y1 is LOW
• 010 → Y2 is LOW
• ...
• 111 → Y7 is LOW
Only one output goes LOW at a time, depending on the input.

74138 in Address Decoding

You can use A13, A14, A15 (or any 3 address lines) as inputs C, B, A.

Each output line (Y0–Y7) can then be connected to the CE (chip enable) pin of a memory or I/O
device.

This way:

• You divide the address space into 8 blocks.

• Each block is selected when the matching 3-bit address appears.

For example:

• A15–A13 = 111 → Y7 = LOW → enables device mapped at top of memory

• A15–A13 = 000 → Y0 = LOW → enables device at bottom
Q: Let’s now explain how to use a 74138 decoder to map 8 EPROMs (e.g., 8 × 2764 = 64 KB)
into the address space F0000H to FFFFFH in an 8088 system.

GOAL
Map the EPROMs into the top 64 KB of the 8088's memory space:

• Start Address: F0000H

• End Address: FFFFFH
• Total range: 10000H = 64 KB

COMPONENTS INVOLVED
• 8088 microprocessor: 20-bit address bus (A0–A19), 1MB addressable range.
• 74138 decoder: 3-to-8 active-LOW outputs.
• 2764 EPROMs: 8KB per chip × 8 chips = 64 KB total.

MEMORY BLOCK BREAKDOWN

Each 2764 EPROM is 8 KB in size:

• 64 KB / 8 = 8 blocks.

HOW TO USE THE 74138 DECODER HERE

Inputs to 74138:

• Use A13, A14, A15 as inputs (C, B, A) to 74138 for block selection.

Enable the 74138 only when A16–A19 = 1111 (i.e., FxxxxxH):

Q: now let’s explain how to interface 8 × 2764 EPROMs (8 KB each) using a 74138
decoder into the address space 60000H to 6FFFFH in an 8088 system.

OBJECTIVE
You want to map 8 EPROMs (8 KB each, total 64 KB) into the address range:

• Start Address: 60000H

• End Address: 6FFFFH
• Size: 10000H = 64 KB

MEMORY BREAKDOWN
Each EPROM is 8 KB. So split the 64 KB range: 64/8;
DECODING STRATEGY USING 74138
Use 74138 to select 1 of the 8 EPROMs based on address lines A13, A14, A15:

• These 3 lines change per 8 KB block.

• Connect:
o A13 → A
o A14 → B
o A15 → C

Enable 74138 only when A16–A19 = 0110 (i.e., addresses between 60000H–
6FFFFH):

Signal Value for decoding

A16 0
A17 1
A18 1
A19 0
CONNECTION SUMMARY
Pin/Signal Connection
A0–A12 To all EPROMs (address within each chip)
A13–A15 To 74138 (inputs A, B, C)
A16–A19 Used to generate enables for 74138
74138 Y0–Y7 To CE̅ (Chip Enable) of each EPROM
EPROM OE̅ To RD̅ (from 8088)
Data bus Common D0–D7

Q: Let’s now explain how to interface a 74138 decoder with the 8088 microprocessor and 8
× 27128 EPROMs to map into the address space A0000H to BFFFFH, step by step.

GOAL
You want to map 8 × 27128 EPROMs (16 KB each) into the address range:

• Start Address: A0000H

• End Address: BFFFFH
• Size: 20000H = 128 KB
COMPONENTS OVERVIEW
8088 Microprocessor

• 20-bit address bus: A0–A19 → 1MB addressable space

• 8-bit data bus: D0–D7

74138 Decoder

• 3-to-8 line decoder

• 3 inputs: A, B, C (used to select 1 of 8 outputs)
• 3 enable pins: G1 (active HIGH), G2A̅, G2B̅ (both active LOW)
• Active LOW outputs: Y0–Y7

27128 EPROM

• Size: 16 KB (2¹⁴ = 16384 bytes)

• Address lines: A0–A13
• Data lines: D0–D7
• Control lines: CE̅ (chip enable), OE̅ (output enable)

MEMORY BLOCK MAPPING (16 KB EACH)

DECODING STRATEGY WITH 74138
Step 1: Use A14–A16 for selection

• Each 16 KB block requires 14 address lines (A0–A13)

• So A14, A15, A16 are used for 74138 input lines A, B, C

→ Connect:

• A14 → 74138 input A

• A15 → input B
• A16 → input C

Step 2: Enable 74138 only for A0000H–BFFFFH

Look at address bits A17–A19:

• A0000H = 1010 0000 0000 0000 0000

• BFFFFH = 1011 1111 1111 1111 1111

So A17–A19 = 101 i.e., A19 = 1, A18 = 0 , A17 = 1

Use logic:

• G1 = HIGH
• G2A̅ = A18 (must be LOW → A18 = 0)
 • G2B̅ = NOT A19 (must be LOW → A19 = 1)

CONNECTION SUMMARY
Signal Connected To
A0–A13 (8088) A0–A13 of all EPROMs
A14–A16 74138 inputs (A, B, C)
A17–A19 Used to generate enable logic for 74138
74138 Y0–Y7 Connect to CE̅ of each EPROM
OE̅ (EPROMs) Connect to RD̅ of 8088
Data bus D0–D7 Shared between EPROMs and 8088
 74139 DECODER (DUAL 2 T0 4 LINE DECODER)

The 74139 is an integrated circuit (IC) that contains two independent 2-to-4 line decoders or
demultiplexers. It is widely used in digital systems to decode binary inputs into one of several
outputs. Here's a breakdown to help you understand it clearly:

What is a Decoder?

A decoder is a digital circuit that converts binary input into a single active output line. In a 2-to-
4 line decoder, you have:

• 2 input lines (binary input)

• 4 output lines
• Only one output is active (LOW in the 74139) at any given time, depending on the input
combination.

What Does “Dual 2-to-4 Line Decoder” Mean?

• The 74139 IC has two separate 2-to-4 decoders in a single package.

• Each decoder works independently.
• Each decoder has:
o 2 inputs for selection (A and B)
o 1 enable input (G) – active LOW
o 4 outputs (Y0 to Y3) – active LOW
Pin Configuration (16-pin DIP package)

• G1, A1, B1 = Control Decoder 1

• G2, A2, B2 = Control Decoder 2

Truth Table for Each Decoder

Note: Outputs are active LOW. That means 0 = selected/active output.

Q: Let’s break down how the 74139 decoder can be used to decode address space,
specifically for the address range:

FFFFFH to F0000H (which is a 64 KB block in memory)

Q: Let’s analyze how the 74139 decoder can be used to decode the address space
from:D0000H to DFFFFH

1. Understanding the Address Range

• Start: D0000H
• End: DFFFFH

This range covers 64 KB of memory, just like your previous example but at a different segment.

2. Convert to Binary (Upper Address Bits)

Since these are 20-bit addresses (8086 addressing), let's look at the top 4 bits (A19 to A16):

Hex Binary (A19–A16)

D0000H 1101 0000 0000 0000 0000
DFFFFH 1101 1111 1111 1111 1111

So the top nibble (A19 to A16) is fixed at 1101 (that is D in hex) for the entire 64 KB block.

3. How to use 74139 for Decoding D0000H–DFFFFH

Q: WE want to decode the address range 40000H to 7FFFFH (which is 256 KB) using 8
pieces of 27256 EPROMs controlled by a 74139 decoder on an 8088 system.

1. Understand the Address Range and Memory Size

• Start address: 40000H
• End address: 7FFFFH
• This covers from 0x40000 to 0x7FFFF = 256 KB total memory.

2. About the 27256 EPROM

 • Each 27256 EPROM chip is 32 KB (32 * 1024 bytes).
• You have 8 chips, so total memory = 8 * 32 KB = 256 KB.

Perfect — your total address range (256 KB) matches the total size of all 8 EPROMs combined.

3. How to map the 8 EPROM chips to address space

You need to split the 256 KB block from 40000H to 7FFFFH into 8 blocks of 32 KB each.

Each block = 32 KB = 2^15 bytes, so the lower 15 address bits (A0–A14) will be used inside
each EPROM.

The upper bits will be used for chip select.

4. Address bits for 8088 (20 bits total):

• Total 1 MB = 2^20 bytes = addresses A0 to A19
• 32 KB = 2^15 bytes → so A0–A14 are chip internal addresses

5. Address ranges of each EPROM (32 KB each)

 8086 Memory Interface

• The 8086 CPU has a 16-bit data bus (D0-D15).

• It can access 8-bit (byte) or 16-bit (word) data.
• To support this, its 16-bit data bus is divided into two 8-bit banks:
o Low bank (D7-D0): connected to even addresses
o High bank (D15-D8): connected to odd addresses
• This way, the CPU can:
o Access both banks for 16-bit (word) read/write (when both banks are enabled)
o Access only one bank for 8-bit (byte) read/write (either low or high bank
enabled)

2. Bank Selection Signals

• BHE (Bus High Enable): Selects the high bank (odd addresses)
• A0 (Address bit 0): Selects the low bank (even addresses)

BHE A0 Meaning
0 0 Both banks enabled (16-bit access)
0 1 High bank enabled only (odd address, upper byte)
1 0 Low bank enabled only (even address, lower byte)
1 1 No bank enabled (no operation)

3. Mapping Addresses to Banks

• The low bank RAM stores all even addresses (like 00000h, 00002h, 00004h, ...)
• The high bank RAM stores all odd addresses (like 00001h, 00003h, 00005h, ...)

This means:

• Address 0x00000 → data lines D7-D0 (low bank RAM)

• Address 0x00001 → data lines D15-D8 (high bank RAM)
• Address 0x00002 → low bank RAM
• Address 0x00003 → high bank RAM
• and so on...
1. Accessing 16-bit data from an Even Address
Instruction:
MOV AX, [0000h]

• Here, DS = 0000h (Data Segment base)

• We want to load the 16-bit word starting at offset 0000h.

Physical Address Calculation:

Physical Address (PA) = DS * 16 + offset

• For offset = 0000h:

PA1=0000h∗10h+0000h=00000h

• The lower byte (AL) is at physical address 00000h.

• The higher byte (AH) is at the next address, 00001h:

PA2=0000h∗10h+0001h=00001h

Binary Address Representation:

 • 00000h in binary (20 bits):

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• 00001h in binary:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

What happens physically:

• For even address 00000h, A0 = 0 → Low bank RAM enabled.

• For next byte at 00001h (odd address), A0 = 1 → High bank RAM enabled.
• Since the AX register is 16 bits:
o AL (lower byte) is read from low bank at address 00000h
o AH (higher byte) is read from high bank at address 00001h

This is the normal and most efficient case: 16-bit word aligned at an even address, where low
and high bytes lie in two adjacent physical memory locations split between low and high banks.

2. Accessing 16-bit data from an Odd Address

Instruction:
MOV AX, [0001h]

• Here, DS = 0000h
• We want to load the 16-bit word starting at offset 0001h.

Physical Address Calculation:

• For offset = 0001h:

PA1=0000h∗10h+0001h=

• Lower byte (AL) is at physical address 00001h.

• Higher byte (AH) is at the next address, 00002h:

PA2=0000h∗10h+0002h=00002
Binary Address Representation:

• 00001h in binary (20 bits):

CopyEdit
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

• 00002h in binary:

CopyEdit
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

What happens physically:

• Lower byte at odd address 00001h, so A0=1 → High bank RAM enabled.
• Higher byte at even address 00002h, so A0=0 → Low bank RAM enabled.
• Here the 16-bit word is split across the boundary of the two banks in reverse order:
o AL (lower byte) from high bank (odd address)
o AH (higher byte) from low bank (even address)

Important Notes:

• Accessing 16-bit data at an odd address is not aligned and may cause performance
penalties.
• The 8086 must perform two memory accesses (or bus cycles):
o One to read the byte from high bank at 00001h
o One to read the byte from low bank at 00002h
• This is because the 16-bit word spans two different memory banks, and the address
crosses the boundary.

Summary Table
Lower Byte Higher Byte
Case Bank Bank Comment
Address Address
16-bit access at Low High
00000h 00001h Aligned, efficient
even addr bank bank
16-bit access at High Low Unaligned, crosses bank
00001h 00002h
odd addr bank bank boundary
Bank Selection in 8086 Memory Interface
The 8086 CPU has a 16-bit data bus, but it is internally split into two 8-bit banks:

• Low bank (even addresses, D7-D0)

• High bank (odd addresses, D15-D8)

When the CPU reads or writes data, it uses signals to select which bank(s) to activate:

• BHE (Bus High Enable): Controls the high bank (odd bytes)
• A0 (Address bit 0): Controls the low bank (even bytes)

Depending on these signals, either or both banks may be accessed.

Two Methods to Select Banks of Memory

Two Ways to Control These Banks

1. Separate Bank Decoders (Complex but Flexible)

• Uses two decoder chips (like 74LS138)—one for each bank.

• How it works:
 o Low Bank Decoder turns on when A0 = 0 (even address).
o High Bank Decoder turns on when BHE = 0 (odd address).
o Each decoder checks the address range to decide which RAM chip to
enable.
• Best for: Big systems with lots of memory (e.g., full 1MB space in 8086).

2. Separate Bank Strobes (Simple but Limited)

• Instead of decoders, the CPU generates direct control signals:

o LWR (Low Write): Writes to low bank (even addresses).

o HWR (High Write): Writes to high bank (odd addresses).
o LRD (Low Read) / HRD (High Read): Similar for reading.
• How it works:

o If writing a byte to even address → Only LWR activates.

o If writing a byte to odd address → Only HWR activates.
o If writing a 16-bit word → Both LWR & HWR activate.
• Best for: Small systems where memory is fixed (e.g., ROM or small RAM).

Q: memory interface design where the 8086 microprocessor is connected to two RAM chips
(62256) using the Separate Bank Decoders method.

8086 Memory Interface with 62256 RAM Chips

1. Basic Setup

• The 8086 has a 16-bit data bus (D0-D15) but needs to work with 8-bit RAM
chips (62256).
• Solution: Use two 62256 RAM chips (32KB each):

o Low Bank (Even addresses) → Handles D0-D7

o High Bank (Odd addresses) → Handles D8-D15
Method 1: Separate Bank Decoders

How It Works

1. Address Lines:

o A1-A15 of 8086 → Connected to A0-A14 of both RAMs (since 32KB = 2¹⁵

addresses).
o A0 and BHE control bank selection (not used for addressing RAM
directly).
2. Decoder (74LS138) Logic:

o For Low Bank (Even Addresses):

▪ Enabled when A0 = 0 (even address).

▪ Decoder checks A16-A19 to ensure the address is in F0000H-
FFFFFH.
o For High Bank (Odd Addresses):

▪ Enabled when BHE = 0 (odd address).

▪ Decoder checks A16-A19 for the same range.
3. Control Signals:

o CE (Chip Enable) → Comes from decoder.

o OE (Output Enable) → Connected to RD (Read).
o WE (Write Enable) → Connected to WR (Write).
Method 2: Separate Bank Strobes

How It Works

1. Address Lines:

o Same as above (A1-A15 → A0-A14 of RAMs).

o A0 and BHE are not used for addressing.
2. Strobe Signals:

o LWR (Low Write) = A0' AND WR → Writes to low bank (even addresses).
o HWR (High Write) = BHE' AND WR → Writes to high bank (odd
addresses).
o OE (Output Enable) → Connected to RD (Read).
3. No Decoder Needed:

o RAMs are always enabled (CE tied low).

o LWR/HWR directly control writing to each bank.
Address Space: F0000H-FFFFFH (64KB)

• Low Bank (Even): F0000H, F0002H, F0004H, ..., FFFFEH.

• High Bank (Odd): F0001H, F0003H, F0005H, ..., FFFFFH.
• Total: 32KB (low) + 32KB (high) = 64KB.

How Addressing Works

• Example: Accessing F1234H (even address):

1. A0 = 0 → Low bank selected.

2. A1-A15 → Sent to RAM (A0-A14) to select the exact byte.
3. D0-D7 → Data transferred.
• Example: Accessing F1235H (odd address):

1. BHE = 0 → High bank selected.

2. A1-A15 → Sent to RAM (A0-A14).
3. D8-D15 → Data transferred.