Design Cycle

FPGA vs. ASIC Design Flow

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‫ ﻫﺎ‬FPLD ‫ﭼﺮﺧﻪ ﻃﺮاﺣﯽ ﺑﺮاي ﺑﺮﺧﯽ‬

• Design Entry
• Schematic Netlist
• HDL
• Waveform
• State Diagram

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 ‫ﭼﺮﺧﻪ ي ﻃﺮاﺣﯽ ﺑﺮاي ﺑﺮﺧﯽ ‪ FPLD‬ﻫﺎ‬
‫• ﻣﺰاﯾﺎ‬
‫• ﮐﻮﺗﺎه ﺷﺪن ﭘﺮوﺳﻪ ﻃﺮاﺣﯽ‬
‫• ﻧﻮآوري ﺑﯿﺸﺘﺮ )ﭘﺮوﺳﻪ ﻃﺮاﺣﯽ ﺑﻪ ﻣﺮاﺣﻞ ﺑﺎﻻﺗﺮ رﻓﺘﺎري ﻣﻨﺘﻘﻞ ﻣﯽ ﺷﻮد()ﺗﺸﺎﺑﻪ ﺑﺎ زﺑﺎن ﻫﺎي ﺳﻄﺢ ﺑﺎﻻ(‬
‫• دﯾﺒﺎگ ﻃﺮح ﺑﺴﯿﺎر آﺳﺎن ﺗﺮ و ﺳﺮﯾﻊ ﺗﺮ‬
‫• ﻣﺎﻧﻨﺪ ﺳﯿﮑﻞ ﺑﺮﻧﺎﻣﻪ ﻧﻮﯾﺴﯽ‬

‫• ﺗﻐﯿﯿﺮات در ﻃﺮح ﺑﺴﯿﺎر آﺳﺎن ﺗﺮ‬

‫• ﺑﻌﻀﯽ ﺷﺮﮐﺖ ﻫﺎ ﻧﺴﺨﻪ ﺟﺪﯾﺪ ﺳﺨﺖ اﻓﺰار ﺧﻮد را روي ‪ CD‬ﯾﺎ از ﻃﺮﯾﻖ ﻧﺮم اﻓﺰار در اﺧﺘﯿﺎر ﻣﺸﺘﺮي ﺧﻮد ﻗﺮار ﻣﯽ دﻫﻨﺪ ﺗﺎ‬
‫‪ EPROM‬را ﻣﺠﺪدا ﺑﺮﻧﺎﻣﻪ رﯾﺰي ﮐﻨﺪ‪.‬‬
‫‪Zeinab Kalantari‬‬
FPGA and Embeded Design
• http://www.xilinx.com/training/free-video-cources.htm#ASIC

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Entry- HDL Coding
• HDL allows us to describe the functionality of a logic circuit in a
language that is:
• Easy to understand
• Easy to share
• Hide complicated implimentation details
• Designer more concerned about the design functionality than the detail
circuit design

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Simulation by Testbenches
• After HDL codin, the code has to be tested using “Testbenches”
(verification)

• Simulation Tools
• Modelsim (Mentor Graphics)
• Simulators of Synthesis Tools

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Synthesis
• Synthesis Tool:
• Analyzes a piece of HDL code and converts it into optimized logic gates
• This conversion is done according to the “language semantics”
→ We have to learn these language semantics, i.e., VHDL code
• It is an important tool to improve designer’s productivity to meet today’s
design complexity
• If a designer candesign 150 gates a day, it will take 6666 man’s day to design a
10-mlion gate design, or almost 20 years for 10 designer! This is assuming a
linear grow of complexity when design gets better.

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Synthesis Tool
• Input
• HDL Code
• “Technology Library” file
• Constraint file (Timing ,
area,power,loading
requirment,optimizing Alg)
• Output
• A gate-level “Netlist” of the
design
• Timing files (.sdf)

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Synthesis Example
• A 2-to-1 Multiplexer (2×1 MUX)

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Synthesis Tool
• Infer logic and state elements
• Perform technology-independent optimizations
• e.g., logic simplification , astate assignment
• Map elements to the target technology
• Perform technology-dependent optimizations
• Multi-level logic optimization
• Coose gate strengths to achieve speed goals
Vendor Name Product Name Platform
Altera Quartus II FPGA
Xilinx ISE FPGA
Mentor Graphics Modelsim, Percision FPGA/ASIC
Synopsys Design Compiler, Galaxy ASIC
Synplicity Synplify ASIC
Cadence Ambit, BG,
ZeinabRC
Kalantari ASIC
Implimentation for FPGA

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‫‪Application of HDLs‬‬

‫• ‪ VHDL‬ﺑﻪ ﻋﻨﻮان زﺑﺎن ﻣﺴﺘﻨﺪ ﺳﺎزي ) ﺗﻮﺻﯿﻒ ﻧﺮﻣﺎل و ﺑﺪون اﺑﻬﺎم(‬

‫• ﺳﻨﺘﺰ ‪ :‬ﺗﺒﺪﯾﻞ )اﺗﻮﻣﺎﺗﯿﮏ ﯾﺎ دﺳﺘﯽ( ﯾﮏ ﺗﻮﺻﯿﻒ ﺑﻪ ﺗﻮﺻﯿﻔﯽ ﺑﺎ ﺟﺰﺋﯿﺎت ﺑﯿﺸﺘﺮ‬
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 Concepts of HDL
:‫• اﺟﺮاي دﺳﺘﻮرات‬
• Execution of Statements ‫• ﺗﺮﺗﯿﺒﯽ‬
• Sequential (‫• ﻫﻤﺰﻣﺎن )ﻣﻮازي‬
• Concurrent

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‫‪Concepts of HDL‬‬
‫• ‪ : Abstraction‬ﻃﺮح را ﻣﯽ ﺗﻮان در ﺳﻄﻮح ﻣﺨﺘﻠﻔﯽ از ﺟﺰﺋﯿﺎت ﺗﻮﺻﯿﻒ ﮐﺮد‬
‫• ﺑﺮاي ﻣﺪﻟﺴﺎزي‪ ،‬ﺳﻄﻮح ﺑﺎﻻ ﮐﺎﻓﯽ اﺳﺖ‪.‬‬
‫• ﺑﺮاي ﺳﻨﺘﺰ‪ ،‬ﻣﻤﮑﻦ اﺳﺖ ﺟﺰﺋﯿﺎت ﺑﯿﺸﺘﺮي ﻻزم ﺑﺎﺷﺪ‪.‬‬
‫• ‪ : Modularity‬ﻣﯽ ﺗﻮان ﺑﻠﻮك ﭘﯿﭽﯿﺪه را ﺑﻪ ﺑﻠﻮك ﻫﺎي ﮐﻮﭼﮑﺘﺮ ﺗﻘﺴﯿﻢ ﮐﺮد و ﺑﺮاي ﻫﺮ ﺑﺨﺶ‬
‫ﯾﮏ ﻣﺪل ﻧﻮﺷﺖ‪.‬‬
‫• ‪ : Hierarchy‬ﺗﺸﮑﯿﻞ ﯾﮏ درﺧﺖ ﺳﻠﺴﻠﻪ ﻣﺮاﺗﺒﯽ‬
‫• ﻫﺮ ﮐﺪام از ﻧﻮدﻫﺎ ﻣﻤﮑﻦ اﺳﺖ در ﺳﻄﺢ ﻣﺘﻔﺎوﺗﯽ از ‪ abstraction‬ﺗﻮﺻﯿﻒ ﺷﺪه ﺑﺎﺷﺪ‪.‬‬

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Modeling Capability

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VHDL Syntax

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VHDL - Overview
• Very High Speed Integrated Circuit Hardware Description Language
• Modeling of digital systems
• Concurrent and sequential elements
• International Standards
• IEEE Std 1076-1987
• IEEE Std 1076-1993,2000, 2002
:‫ اﻧﺠﺎم ﮔﺮﻓﺘﻪ اﺳﺖ‬VHDL ‫ ﺗﻼش ﻫﺎﯾﯽ ﺑﺮاي اﺳﺘﺎﻧﺪارد ﮐﺮدن ﻋﻮاﻣﻞ ﻣﺮﺑﻮط ﺑﻪ‬،‫• ﻋﻼوه ﺑﺮ اﺳﺘﺎﻧﺪاردﻫﺎي ﺧﺎﻟﺺ‬
‫• ﭘﮑﯿﺞ ﻫﺎ‬
std_logic_1164 •
Numeric_bit •
Numeric_std •
1076.6 ‫ اﺳﺘﺎﻧﺪارد‬: ‫• زﯾﺮﻣﺠﻤﻮﻋﻪ ﻗﺎﺑﻞ ﺳﻨﺘﺰ‬
VHDL-AMS 1076.1 •

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Abstraction Level in IC Design

.‫ ﻣﻨﺎﺳﺐ ﻧﯿﺴﺖ‬layout ‫ ﺑﺮاي ﺳﻄﺢ‬VHDL •

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VHDL Structural Elements
• Entity: Interface
• Architecture: Implimentation, behavior
• Configuration: Structure , hierarchy
• Process: Seqential Execution
• Package: Components (Modular design), Utilities (data types,
constants, subprograms)
• Library: Groups of compiled units, object code

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Design Library
• Storage location for analyzed design units
• VHDL models only deal with logical library names
• Mapping too physical locations is up to VHDL tools
• Two classes of design libraries
• Working library (read-write, only one active)
• Resources library (read-only, possibly more than one active)
• Predefined logical design libraries
• WORK Current active working library
• STD. Resource library containing only three packages
(STANDARD, TEXTIO)
• IEEE Resource library containing only standard VHDL packages

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Design File
• Text file containing one or more design units
• Recommended file extension: .vhd
• Order of design units is important
• Primary units must appear before related secondary units
• Successful analysis of a design file generates binary design units in the
working library

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VHDL Key Idea
• A key idea in VHDL is to define the interface of a hardware module
while hiding its internal details.
• A VHDL entity is simply a declaration of a module’s inputs and outputs, i.e.,
its external interface signals or ports.
• A VHDL architecture is a detailed description of the module’s internal
structure or behavior.

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VHDL Interface - Ports
• You can think of the entity as a “wrapper” for the architecture.
• hiding the details of what’s inside
• providing ”ports” to other modules

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VHDL Conceptual Model
• VHDL actually allows you to entity
define multiple architecture for a
single entity. architecture 1

• It also provides a configuration

management facility that allows architecture 2
you to to specify which
architecture to use during a
configuration
particular synthesis run.

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VHDL Design Units
• Smallest model elements that can be separately analyzed
• P : Primary Units
• S : Secondary Units

• Design entity: Primary harrdware abstraction

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Entity
• Interface description
• No behavior/implimentation
defenition

A SUM

?
B CARRY

• Linking via port signals

• data types
• signal width
• signal direction
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Entity Port Modes
• in:
• signal values are resd-only
• out:
• signal values are write-only
• multiple drivers
• buffer
• similar to out
• signal values may be read, as
well
• only 1 driver
• inout
• bidirectional port
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