Chapter 8

Interrupt
 Interrupt
 Interrupt is the method of creating a temporary halt during program
execution and allows peripheral devices to access the microprocessor.
 The microprocessor responds to that interrupt with an ISR (Interrupt Service
Routine), which is a short program to instruct the microprocessor on how to
handle the interrupt.
 An interrupt is a hardware initialized procedure that interrupts whatever
program is currently executing.
 Interrupts are particularly useful when interfacing I/O devices that provide
or require data at relatively low data transfer rates.
 Interrupt is a signal which has highest priority from hardware or software
which processor should process its signal immediately.
 SOURCES OF INTERRUPTS IN 8086
 An interrupt in 8086 can come from one of the following three sources.
1) One source is from an external signal applied to NMI or INTR input pin
of the processor.
 The interrupts initiated by applying appropriate signals to these input
pins are called hardware interrupts.
2) A second source of an interrupt is execution of the interrupt instruction
"INT n", where n is the type number.
 The interrupts initiated by "INT n" instructions are called software
interrupts.
3) The third source of an interrupt is from some condition produced in the
8086 by the execution of an instruction.
 An example of this type of interrupt is divide by zero interrupt.
 Program execution will be automatically interrupted if you attempt to
divide an operand by zero. Such conditional interrupts are also known
as exceptions.
Types of Interrupt
 There are two types of interrupts which are as follows:-
1) HARDWARE INTERRUPTS
 If the signal for the processor is from external device or hardware is
called hardware interrupts.
 The interrupt signal generated from external devices and i/o devices are
made interrupt to CPU when the instructions are ready.
For example: In a keyboard if we press a key to do some action this
pressing of the keyboard generates a signal that is given to the processor to
do action, such interrupts are called hardware interrupts.
 Hardware interrupts are classified into two types which are as follows −
 Maskable Interrupt:- The hardware interrupts that can be delayed when
a highest priority interrupt has occurred to the processor.
 Non Maskable Interrupt:- The hardware that cannot be delayed and
immediately be serviced by the processor.
 Mask able interrupt (INTR)

 The INTR is a maskable interrupt because the microprocessor will be

interrupted only if interrupts are enabled using set interrupt flag
instruction.
 It should not be enabled using clear interrupt Flag instruction.
 The INTR interrupt is activated by an I/O port.
 If the interrupt is enabled and NMI is disabled, then the microprocessor
first completes the current execution and sends ‘0’ on INTA pin twice.
 The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from
the programmable interrupt controller.
Non-maskable interrupt(NMI)
 It is a single non-maskable interrupt pin (NMI) having higher priority
than the maskable interrupt request pin (INTR) and it is of type 2
interrupt.
 When this interrupt is activated, these actions take place
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer)
value of the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location
0000AH. Interrupt flag and trap flag are reset to 0.
Types of Interrupt
Software Interrupts
 Some instructions are inserted at the desired position into the program to
create interrupts.
 These interrupt instructions can be used to test the working of various
interrupt handlers

 Software interrupts can be classified into three main categories:-

1) INT- Interrupt instruction with type number
2) INT 3- Break Point Interrupt Instruction
3) INTO - Interrupt on overflow instruction
INT-Interrupt instruction with type number
 It is 2-byte instruction. First byte provides the op-code and the second
byte provides the interrupt type number.
 There are 256 interrupt types under this group.
 Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address
are pushed on to the stack.
 IP is loaded from the contents of the word location ‘type
number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
 The starting address for type0 interrupt is 000000H, for type1 interrupt
is 00004H similarly for type2 is 00008H and ……so on.
 The first five pointers are dedicated interrupt pointers. i.e.:-
TYPE 0 interrupt represents division by zero
situation.
TYPE 1 interrupt represents single-step
execution during the debugging of a program.
TYPE 2 interrupt represents non maskable NMI
interrupt.
TYPE 3 interrupt represents break-point
interrupt.
TYPE 4 interrupt represents overflow interrupt.
 The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and
 Interrupts from Type 32 to Type 255 are available for hardware and
software interrupts.
 INT 3-Break Point Interrupt Instruction
 It is a 1-byte instruction having op-code is CCH.
 These instructions are inserted into the program so that when the
processor reaches there, then it stops the normal execution of program and
follows the break-point procedure.
 Its execution includes the following steps:-
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return
address are pushed on to the stack.
 IP is loaded from the contents of the word location 3×4 =
0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
 INTO - Interrupt on overflow instruction
 It is a 1-byte instruction and their mnemonic INTO.
 The op-code for this instruction is CEH. As the name suggests it is a
conditional interrupt instruction, i.e. it is active only when the overflow flag
is set to 1 and branches to the interrupt handler whose interrupt type number
is 4.
 If the overflow flag is reset then, the execution continues to the next
instruction.
 Its execution includes the following steps −
Flag register values are pushed on to the stack.
CS value of the return address and IP value of
the return address are pushed on to the stack.
IP is loaded from the contents of word location
4×4 = 00010H
CS is loaded from the contents of the next word
location.
Interrupt flag and Trap flag are reset to 0
 Operation of a Real Mode Interrupt
 When the microprocessor completes executing the current instruction, it
determines whether an interrupt is active by checking (1) instruction
executions, (2) single-step, (3) NMI, (4) coprocessor segment overrun, (5)
INTR, and (6) INT instructions in the order presented.
 If one or more of these interrupt conditions are present, the following
sequence of events occurs:-
1. The contents of the flag register are pushed onto the stack.
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the
INTR pin and the trap or single-step feature.
3. The contents of the code segment register (CS) are pushed onto the stack.
4. The contents of the instruction pointer (IP) are pushed onto the stack.
5. The interrupt vector contents are fetched, and then placed into both IP
and CS so that the next instruction executes at the interrupt service
procedure addressed by the vector.
 Operation of a Protected Mode Interrupt
 In the protected mode, interrupts have exactly the same assignments as in the
real mode, but the interrupt vector table is different.
 In place of interrupt vectors, protected mode uses a set of 256 interrupt
descriptors that are stored in an interrupt descriptor table (IDT).
 The interrupt descriptor table is 256 × 8 (2K) bytes long, with each
descriptor containing eight bytes.
 The interrupt descriptor table is located at any memory location in the
system by the interrupt descriptor table address register (IDTR).
 Each entry in the IDT contains the address of the interrupt service procedure
in the form of a segment selector and a 32-bit offset address.
 It also contains the P bit (present) and DPL bits to describe the privilege
level of the interrupt.
 Real mode interrupt vectors can be converted into protected mode
interrupts by copying the interrupt procedure addresses from the
interrupt vector table and converting them to 32-bit offset addresses
that are stored in the interrupt descriptors.
 A single selector and segment descriptor can be placed in the global
descriptor table that identifies the first 1M byte of memory as the
interrupt segment.
Interrupt Flag Bits
 The interrupt flag (IF) and the trap flag (TF) are both cleared after the
contents of the flag register are stacked during an interrupt.
 When the IF bit is set, it allows the INTR pin to cause an interrupt;
 When the IF bit is cleared, it prevents the INTR pin from causing an
interrupt.
 When TF = 1, it causes a trap interrupt (type number 1) to occur after
each instruction executes. This is why we often call trap a single-step.
 When TF = 0, normal program execution occurs.
 The interrupt flag is set and cleared by the STI and CLI instructions,
respectively. There are no special instructions that set or clear the trap
flag.