CMOS Current Mode Analog Multiplier

Ankita Tijare Pravin Dakhole

Ph.D. Scholar Professor
YCCE, Nagpur, India YCCE, Nagpur, India
[email protected] [email protected]

Abstract—This paper presents two different multiplier. Low-power CMOS four quadrant analog multiplier
implementations of four Quadrant CMOS Analog Multiplier based on a squarer topology is presented in [12] which are
Circuits. The Multipliers are designed in current mode. suitable in deep submicron technology . Four-quadrant analog
Current squarer and translinear loops are the basic blocks for multiplier circuit can also be implemented using strong
both the structures in realization of mathematical equations. inversion saturated MOSFETs characteristics [13]. The circuit
The structures have simplicity in implementation. The is construced by connecting simple combiner and subtractor
proposed multiplier structures are designed in implementing in cells in a novel topology.
180 nm CMOS technology with a supply of 1.8 V & 1.2 V In this paper, two different architectures of the current mode
resp. The structures have frequency bandwidth of 493 MHz & multipliers are implemented. Using the squarer topology first
75 MHz with a power consumption of 146.78µW & 36.08µW multipier is implemented. The squarer function is designed &
respectively. implemented using transistor characteristics when biased in
saturation region. The design works on the supply voltage of
Keywords— Four Quadrant Multiplier,current mode, low VDD=1.8V. The MOS transistors use square law characteristics
power, high bandwidth,low voltage. biased in saturation region. The second architecture makes use
of translinear loop for the implementation with a supply
I. INTRODUCTION voltage of 1.2V.
Analog multipliers is an important block in analog signal
II. CIRCUIT DESCRIPTION
processing and have very useful applications such as
communication system, frequency doublers, neural networks,, Two implementation of current mode analog multiplier
modulators, fuzzy controllers, etc. Considering the application structures are presented. The main goal of proposed current
of input variables, multipliers are classified as-voltage mode multiplier is related to the determination of
multipliers: accept two inputs in the form of voltages and functionality level. The frequency response & the accuracy of
output generated is in the form of voltage only. Current the multiplier can be increased by using current mode
Multipliers: accept two current quantities as input and current
approach.
mode output is generated. Using the transistor characteristics
when MOS is biased in saturation region the multiplying
function can be implemented. Some of the mathematical
principles are derived from linear relation between squaring A. FIRST MULTIPLIER CIRCUIT
items. Therefore several architectures have been presented in
Squaring technique is used for the first proposed multiplier
the literature.
structure. Fig.1 shows the block diagram for the multiplier
Barrie Gilbert designed four-quadrant multiplier in 1968 using architecture where as the transistorized structure of squarer
the characteristics of bipolar transistor. From Gilbert BJT block is shown in Fig. 2.
multiplier recently designed MOS transconductance based
multipliers different topologies of multipliers are proposed [4].
Multipliers are classified based on its MOS region of operation.
Accuracy can be improved when multiplier is designed using
square law characteristics in saturation region, which again
have the advantage of improving frequency response [5-8] and
the other type is subthreshold operated MOS transistor [9]
which are used for low power applications. For low power low
voltage application multiplier using MOS operated in weak
inversion region is presented in [10-11] Most of these
transconductance multipliers are further categorized based on
type of non linearity cancellation methods used in each
Fig1: Block Diagram of first proposed multiplier structure
 The drain-to-source current (IDS) of a MOS transistor
Current Mode squarer Circuit operated in the saturation region is given by:
The internal structure of squarer cell is shown in Fig.2.
I DS = K (VGS − Vt ) 2
(8)
ID
VGS = Vt +
K (9)
Where K is transconductance parameter of transistor.
Consider a MOS transistor loop of M1 to M4 of Fig.4, &
after summing the gate-source voltages in a loop gives:
VGS 1 + VGS 2 = VGS 3 + VGS 4 (10)

Fig.2 Squarer cell

Assuming the MOS transistors operating in saturation
region, the equation for the drain to source current of
transistor M2 is given by,
I0 = k2 (VB –VT2)2 (1)
Where k2 =µn CoxW/2L.
Similarly the voltages at node A & B are given by,
VA= R(Iin + Ibias)
VB = VA +VGS1
On simplification the output current of squarer cell is given
by

Io= k2 (RIin + VE)2 (2)

FIRST CURRENT MODE MULTIPLIER

The proposed four quadrant multiplier is designed using
four squarer cells. If Ix & IY are applied as input currents to
the squarer cell then the output currents of respective
squarer cells based on equation (2) are given as:
Fig.3 Schematic of First Multiplier
I01 = k(R(Ix +IY) + VE) 2 (3)
I02 = k(R(Ix +IY) + VE)2 (4) Assuming the MOS transistors M1 to M4 of Fig. 4 are
I03 = k(R(Ix +IY) + VE) 2
(5) biased in the saturation region and all transistors are
matched and having the identical value of the
I04 = k(R(Ix +IY) + VE)2 (6)
transconductance parameter, that is KN=KP, then using
equation (8), (9) & (10) gives relationship of the currents
On simplification these currents are the given to subtractor in the loop can be described as:
so as to get the final output equation as:

IOUT = (I01 + I02) – ( I03 + I04) = 8kR2IXIY (7)

The schematic for four quadrant multiplier is shown in

Fig.3.

B. SECOND MULTIPLIER CIRCUIT

Translinear loop: A translinear circuit is a circuit that
works on translinear principle. When a closed loop
containing an even number of translinear elements with
an equal number of transistors are arranged in clockwise
and counterclockwise, then the product of the currents Fig. 4 Translinear loop
through the clockwise elements to that of counter
clockwise elements are same. 2 I 0 = I D + I D + I IN (11)
Squaring the terms and solving, it results Table1: Sizes of the transistor used in the first proposed CM
4 I 0 − 2 I D − I IN = 2 I D ( I D + I IN ) (12) Multiplier
Transistors Aspect Ratio(W/L)
On simplifying, M2,M3,M6,M7 0.25/0.18
16 I 02 + I IN
2
− 16 I D I 0 − 8 I 0 I IN = 0 (13) M1,M4,M5,M8 0.18/0.18
So M9,M10,M11,M12 2,16/0.18
I IN I IN2
I D = I0 − + (14)
2 16 I 0

MULTIPLIER CIRCUIT:

The proposed “Multiplier” circuit is being designed using two

current mode squaring circuits, (M1–M4 and M6–M7,
respectively), which is based on the translinear loop shown in
Fig.4 [2]. The CMOS implementation of the “Multiplier”
circuit is shown in Fig.5. By reusing M1–M2 transistors for
both squaring circuits the complexity of the “Multiplier”
circuit is minimized. The output current is given as,
I OUT = I D 2 − I D1 + 2 I 0 (15)
where expressions of ID1 and ID2 currents are:
( I1 − I 0 )2
I D1 = I 2 − ( I1 − I 0 ) + (16)
4I 2
Fig 5. Current Mode Multiplier
and
( I1 + I 0 )2 For second Multiplier power supply voltage is 1.2V. Fig.11
I D 2 = I 2 − ( I1 + I 0 ) + (17) shows the waveform for amplitude modulation. The
4I 2 modulation is performed when the input currents I0 & I1 are
giving an output current of the circuit as 1GHz & 12 GHz with the peak amplitude of 200uA & 300uA.
I1
I OUT = I 0 (18) The AC characteristics of the multiplier are shown in fig 12
I2
multiplier exhibits 3dB bandwidth of 75MHz.Fig.13 shows the
So, from equation (18) circuit implements the DC characteristics for the multiplier, where I0 is set to 40µA,
multiplying/dividing function. while I2 is continuously swept from 10 µA to 40 µA with 10
III. SIMULATION RESULTS: µA step size. Fig.14 shows the Comparison between
theoretical results and simulated results.

The current mode multiplier circuit shown in Fig .3 & Fig 5 Table2: Sizes of the transistor used in the second proposed
has been simulated with TSPICE using 0.18micron. The first C-M Multiplier
multiplier is simulated with a power supply of VDD=1.8V. The
aspect ratios for the MOS are specified in table 1. In squarer Transistors Aspect Ratio(W/L)
cell IBIAS and R are 4.6µA & 12KΩ, while RL is 1KΩ. Fig 6 M1-M8 0.9/0.18
shows the use of multiplier as amplitude modulator where Ix is M9,M14,M16,M17 1.08/0.18
sinusoidal modulating signal with magnitude 10µA and M10-M13,M15 2.16/0.18
frequency 100KHz where as IY is sinusoidal signal with
magnitude 10µA and frequency 2 MHz. Fig 7 shows the use
of multiplier as frequency doublers where Ix and IY both are
sinusoidal signals with magnitude 10µA and frequency 1MHz.
The frequency characteristic of the multiplier is shown in fig 8
where IY is set to 10µA DC and IX is 10µA AC. The multiplier
exhibits 3dB bandwidth of 569MHz.After performing four
corner analysis it is been observed that multiplier works in
slow-slow corner efficiently. Fig9 shows the result for the
same.Fig10 shows the multiplier performance with respect to
noise. The Noise output Voltage 6.76491n V/Rt(Hz).
Fig6: Multiplier 1 as an Amplitude Modulator
 Fig11: Multiplier 2 as an Amplitude Modulator
Fig7: Multiplier 1 as Frequency Doublers

Fig8: AC Characteristics of Multiplier 1 Fig12: AC Characteristics of Multiplier 2

Fig9: Four Corner Analysis of Multiplier 1

Fig13: DC Characteristics of Multiplier 2

Fig10: Noise Analysis Of Multiplier 1 Fig14: Comparison of theoretical results with simulated
results.
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technology respectively. Current mode multipliers have
advantage of simple circuitry, improved frequency response
and low power consumption. Table 3 gives the comparative
result summary of proposed implemented multipliers.