5th International Conference on Smart Electronics and Communication (ICOSEC 2024)

IEEE Xplore Part Number: CFP24V90-ART; ISBN: 979-8-3315-0440-3

Digital CMOS VLSI Implementation and

Assessment of Power Efficient Delay Flip-Flop
Using Dynamic CMOS Logic for Low Power VLSI
2024 5th International Conference on Smart Electronics and Communication (ICOSEC) | 979-8-3315-0440-3/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICOSEC61587.2024.10722648

Systems
P.Nagarajan1
Department of ECE N.Ashokkumar3
I.Chandra2 Professor, Department of ECE
SRM Institute of Science and
Professor, Department of ECE Mohan Babu University (Erstwhile Sree
Technology, Vadapalani,
Rajalakshmi Institute of Technology, Vidyanikethan Engineering College)
Chennai-600026
Kuthambakkam, Tirupati- 517102
Tamilnadu, India.
Chennai- 600124 AndraPradesh , India
[email protected]
Tamilnadu, India. [email protected]
[email protected]

Dr.M.Thiruveni4 R.Bhairavi6
Associate Professor, Department of Anita Christaline Johnvictor5
Department of ECE
ECE Associate Professor
School of Computer Science and SRM Institute of Science and
PSNA College of Engineering and Technology, Vadapalani,
Technology, Engineering
Chennai – 600026
Dindigul - 624622 Vellore Institute of Technology
Tamilnadu , India
Tamilnadu, India. Chennai - 600127
Tamilnadu, India. [email protected]
[email protected]
[email protected]

Keywords— flip flops, low power, CMOS technology, dual

Abstract— Generally, the flip-flops are vital circuit and edge triggering
foremost power in considering various digital VLSI circuits. I. INTRODUCTION
In this work, a unique power effective flip-flop, named 5-
Device count duple edge triggering delay flipflop (5DC- In current scenario, the power utilization is a foremost concern
DETFF) is introduced by using the power effective techniques in the framing of power efficient circuits and systems
such as reduction of entire quantity of devices usage, implicit modeling. Generally, the flip-flops are vital circuit and
triggering clock, duple edge triggering, dynamic CMOS and foremost power consuming component in various digital
pass transistor logic schema. By following the dynamic and VLSI organizations [1, 2]. The flip-flops intakes maximum
pass transistor logic design styles, the branch-1 and branch-2 power of upto 60% which is extreme value in the global power
of Flip-flop is realized respectively, with entirely 5 devices consuming of digital system organizations [3, 4]. To minimize
count. Another most power proficient techniques called duple the global power intake of digital VLSI organization, the
edge triggering is used in this projected flip-flop and samples power consumption by the key flip-flop circuit must be
the data input D at an arrival of both up and down edges of the condensed. The lessening of power utilization of flip-flop
Triggering clock. Instead separate external trigger clock circuits will outcomes the whole power usage of digital VLSI
generation network, the triggering clock is directly applied to systems [5].
the branch-1 input terminal as implicit fashion. It lessens the The flip-flop circuits for an excellent power efficacy are
extra transistors usage for clock generation network and also realized by following less power designing procedures.
diminishes the power wastage. The presented flip flop is According to the topological development schemes, the flip-
simulated using CMOS 6-metal 0.12µm technology and flop construction is majorly categorized into two sets such as
assessed in point of Complete device usage count, count of master-slave structure and pulse edge triggering structure.
Count of clock triggered device, Circuit layout area, Input The duple edge triggering and master slave flip-flops,
Data D –Q output delay, global power intake and also in view designed by following parallel paradigm strategy are cast-off
of product of power delay, Energy delay and power energy in various embedded and digital signal processors due to its
products. The anticipated topology intakes the entire power of power effectiveness. In the parallel paradigm strategy, one
5.181µW and accomplishes the power efficacy from 12.85% single latching branch is replicated to numerous times as per
to 37.92%, which states this foreseen flipflop will be pertinent the design requirements. While one latching branch is
for low power digital VLSI organisations. sampling and transferring the input data, the rest of the
latching section will be in standby mode and vice versa [6,7].

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The multiple stages in the flip-flop constructions are branches branch-1 and branch-2, totally with 5 counts of
condensed into single stage by clock edge triggering flipflops transistors shown in Fig.1. By following the dynamic CMOS
through ensuing both the negative and positive edges set up logic the branch-1 is created with single P-type device P1 and
time. The clock pulse triggering flip flops are categorized into two counts of N-type devices N1 & N2, totally 3 transistor
implicit pulsed clocking and explicit pulsed clocking fashion. counts. The branch-2 is framed by using one P-type device P2
The Global Power utilization (PGlobal) of any digital VLSI and one N-type device N3, totally two transistor counts. The
Systems can be expressed as [8] devices P2 and N3 will acts as pass transistors and passes the
PGlobal = Static power utilization (Psp) + Dynamic power logical high value and logical low value respectively, while
their gate terminal is driven by corresponding transistor from
utilization (Pdyp) + Short circuit power utilization (Pscp)
branch-1.
Psp- entitles static power intake which occurs because
unwanted current leakage even the circuit in standby mode. In the branch -1, an actual data input D drives the devices
Pdyp - specifies dynamic power utilization which happens due P1 and N2. By following the dynamic CMOS logic, the clock
to unlikable switching activities of circuit elements like ON triggering signal TCLK is applied as implicit fashion to gate
and OFF. Pscp- labels short circuit power dissipation which of device N1. The common power supply VDD and ground
arises because a direct current flow path presents between VSS are given to both branches. Through the Midpoint node-
High power supply voltage (Vdd) and low potential ground X and Midpoint node-Y, the devices P2 &N3 will be enabled
(Vss) while both pull up and pull down networks conducts and results the output Q as logical high and low respectively
simultaneously. which are highlighted in Fig.2.
By following several power saving practices, the overall
B. Functionality of the proposed 5DC-DETFF Design
Power intake of the flipflops can be lessened and named as
follows. [9-11]

• Duple edge triggering

• Usage of minimum devices
• Multiple threshold and supply voltage scheme
• Diminishing the count of clock triggering devices
• Implicit clock triggering scheme
• Operating Path splitting technique

Various flipflop topologies are realized in recent years by

ensuing diverse power effective approaches and recorded as
RTSPC-FF [12], CTS-DETFF [13], DDNET-FF [14], DCS-
FF [15], STCR-DETFF [16] and MS-PTDETFF [17] in
assessment table-1 which are taken into attention to evaluate
the prominence of proposed flip-flop organization.
II. PROPOSED PASS TRANSISTOR LOGIC BASED IMPLICIT
PULSED – DUAL EDGE TRIGGERED FLIPFLOP (PTIP-DETFF)
Fig. 2. schematic of 5DC-DETFF with its logical branches 1 and 2
DESIGN

A. Construction of Proposed 5DC-DETFF Design The functionality of proposed flip-flop is elucidated with
all possible combination of datainput D and clock triggering
signal TCLK as follows.
Functionality-1: while the trigger clock TCLK = logic
high (1), datainput D = logic high (1), the logical high data
input switch OFFs the device P1 and switch ON the device
N2. An implicitly asserted logical high TCLK, switch ON the
device N1. Due the ON state N1 and N2 devices, the ground
Vss is directly connected to the devices p2 and N3 via the
midpoint nodes X and Y.
The device N3 gets switched OFF due to low grounded
signal in its gate terminal. Currently the gate of the P2 is
grounded via ON state devices N1 and N2. Due to this, the
device P2 temporarily becomes Pseudo NMOS device (i.e)
always ON device. The power supply VDD is passing to the
output terminal through the ON state Pseudo NMOS P2
device and the output Q becomes logical high (i.e) Q=1.
Fig. 1. Realization of Proposed 5 Device Count – Dual Edge Triggered Functionality-2: while Trigger clock TCLK= logic high
Flipflop (5DC-DETFF), Entire 5 counts of MOS device loads includes (1), datainput D = logic low (0), the device N2 becomes
single clock trggered device
switched OFF and device P1 becomes switched ON. The high
The proposed 5-Device Count Duple Edge Triggering value of TCLK makes the device N1 gets ON. Due to OFF
Delay Flip-Flop (5DC-DETFF) is constructed by Couple of state N2, the branch -1 is momentarily cut off from the VSS

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 5th International Conference on Smart Electronics and Communication (ICOSEC 2024)
IEEE Xplore Part Number: CFP24V90-ART; ISBN: 979-8-3315-0440-3

ground. At this moment, the power supply VDD is passing III. RESULTS AND DISCUSSION
through the ON state P1 & N1 and energies the midpoint The proposed 5DC-DETFF design is realized in Dsch -
nodes X &Y. due to the logical high signal in both the schematic EDA Microwind platform and simulated by 0.12
midpoints X & Y , the device P2 becomes OFF and N3 µm CMOS-6 metal technology. The prominence of the
becomes ON state. Through an ON state N3 in the branch- anticipated flipflop topology is inspected by the performance
2, the output terminal is directly connected to the ground VSS features such as complete device usage count, count of clock
and pull downs the output to low value (i.e) Q=0. triggered devices, triggering style, input terminal D to output
Functionality-3: while the trigger clock TCLK = logic low delay, Layout Area utilisation and global power intake. The
(0), datainput D = logic high (1), the logical high data input performance of the offered 5DC-DETFF scheme is assessed
switch OFFs the device P1 and switch ON the device N2. The also by the optimization features like product of Power delay,
device N1 becomes switch OFF by an implicitly given logical product of Energy delay and product of power energy.
high TCLK. Due the ON state N1 and N2 devices, the ground The presented scheme samples the input data D at both
Vss is connected to the devices P2 and N3 via the midnodes edges of the triggering clock signal and Concise as follows.
X and Y.
Functionality-1: Input Data D=1, TCLK=1, Output Q =1
The device N3 gets switched OFF due to low grounded
signal in its gate terminal. Presently the gate of the P2 is Functionality-2: Input Data D=0, TCLK=1, Output Q =0
grounded and momentarily becomes always ON Pseudo
Functionality-3: Input Data D=1, TCLK=0, Output Q =1
NMOS device. Through the ON state Pseudo NMOS P2
device, the supply VDD is passing to the output terminal and Functionality-4: Input Data D=0, TCLK=0, Output Q =0
an output Q becomes high.
By asserting, the complete probable combinations of input
Functionality-4: while Trigger clock TCLK= logic low data D (D=logic HIGH & D=logic LOW) and Triggering
(0), datainput D = logic low (0), the device P1 becomes Clock (TCLK= 1 & TCLK=0) the functionalities of offered
switched ON and N2 gets switched OFF. The low value of 5DC-DETFF strategy are assessed as specified above
TCLK makes the device N1 gets OFF. Due to OFF state N1 Functionalities -1, 2, 3 and 4. The simulation outcomes
and N2 devices, the branch -1 is momentarily cut off from the validates the correct functioning of offered structure for
VSS. At this moment, the power supply VDD is passing respective Input Data D & TCLK and shown in Fig. 3, 4, 5
through the ON state P1 and energies the midpoint nodes X and 6.The timing diagram demonstrates the right variation of
&Y. Due to the logical high signal in both the midpoints X & output data Q with respect to the corresponding input data D
Y , the device P2 becomes OFF and N3 becomes ON and shown in Fig.7.
state. An ON state N3 in the output branch, pulls down the
Fig.3.Functionality-1: Input Data D=1, TCLK=1, Output Q =1
output Q to low value (i.e. Q = 0) by connecting the output
terminal to the ground VSS straightly.
In this proposed design, no separate clock generation
network with certain numbers of devices is used. Instead by
following the implicit pulsed clocking scheme, the triggering
clock signal is directly applied to the input terminal of the
flipflop as implicit style. It lessens the extra transistors usage
for clock generation network and also diminishes the power
wastage. By following one of the low power VLSI techniques
named reduction of entire quantity of transistors usage, the
branch-1 is formulated by only 3 devices and branch-2 by only
2 devices, totally 5 devices count. One of the most power
efficient techniques called double edge triggering is used in
this proposed flip-flop and samples the data input D at an
arrival of both up and down edges of the Triggering clock. Fig.4.Functionality-2: Input Data D=0, TCLK=1, Output Q =0
The branch-2 transistor devices permanently connected with
branch-1 through continuously active midpoint nodes X & Y
and will not become a floating devices. Due to this the floating
node problem is evaded in an anticipated flip-flop
construction. So all these methodologies makes the proposed
5DC-DETFF design as power effective.

Fig.5.Functionality-3: Input Data D=1, TCLK=0, Output Q =1

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 5th International Conference on Smart Electronics and Communication (ICOSEC 2024)
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respectively. In account of complete device usage count,

the offered flip-flop construction consists of very less 5
devices count. By ensuing the low power approaches of
less count device usage technique, the projected 5DC-
DETFF is framed with very fewer usage of devices and
makes the projected design to take very less power.

TABLE I. ASSESSMENT OF PERFORMANCE FEATURES

Performance features

Complete device

output delay (ps)

Input Data D –Q
triggered device

Triggering style
Count of clock
usage count

Global Power
Layout area

Intake (μw)
utilization
Flipflop Designs

(μ m2)
Fig.6.Functionality-4: Input Data D=0, TCLK=0, Output Q =0

RTSPC-FF [12] 26 5 Single 616 77.31 8.598

CTS-DETFF [13] 23 8 Dual 424 179 8.347

DDNET-FF [14] 14 2 Dual 176 91 7.610

DCS-FF [15] 24 7 Single 180 112.7 7.40

STCR-DETFF Dual
16 12 201 86.31 7.310
[16]

MS-PTDETFF
Fig.7. Timing Diagram: Input and output response variation 16 6 Dual 252 206 5.945
[17]
Proposed
5DC-DETFF 5 1 Single 132 130 5.181

TABLE II. ASSESSMENT OF OPTIMIZATION FEATURES

Optimization Features
Flipflop Design EDP PEP
PDP (fj)
(*10-24) (*10-20)

RTSPC-FF 0.664 0.0513 0.571

CTS-DETFF 1.503 0.2690 1.263

DDNET-FF 0.692 0.0630 0.527

Fig.8.Swichlevel code proposed design

DCS-FF 0.833 0.093 0.617

STCR-DETFF 0.630 0.0545 0.461

MS-PTDETFF 1.224 0.252 0.728

Proposed
5DC-DETFF 0.673 0.0875 0.348

Commonly, due to dynamic switching nature, the

clock triggered devices intakes extra power compared
with non-clock triggering devices. In point of the count of
clock triggered devices, the offered 5DC-DETFF uses
only one clock triggering device named as N1, which
leads to less dynamic power utilization.
The switch level Verilog code equivalent to an anticipated An offered 5DC-DETFF, results the response Q later the
5DC-DETFF model developed by EDA tool which is delay of 130 ps, which is considerably less rate compared
used for simulation is shown in Fig.8.The performance with prior art of flip-flops labelled in Table-1 excluding
and an optimization features for prior and proposed flip- the fewer flip-flops. This substantial less delay marks the
flop schema are tabulated in the Table-I and Table –II

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5DC-DETFF is also right for high performance Fig.12.Circuit Layout Area Utilization assessment
applications.
Fig.9. Global power intake of offered 5DC-DETFF (Power = 5.181 µW)

Fig.10. Circuit Layout area of offered 5DC-DETFF (Area = 132 µm2)

Fig.13.Complete transistor device usage assessment

Fig.14.PDP, EDP and PEP Assessment

Fig.11.Complete transistor device usage assessment

In point of complete transistor devices usage the proposed Asper, the product of power delay feature, the 5DC-
flip-flop topology needs totally 5 devices including one DETFF structure reports the value of 0.673 fj, which is
clock enabled transistor. Both total device count & clock fewer related to prior schemes excluding RTSPCFF and
enabled transistor count of proposed design is S-TCRFF designs. With respect to the feature called
significantly low compared with prior flip-flops structure Product of Energy Delay, the 5DC-DETFF results the
and reported in the Fig.11. value of 0.0875*10-24 which is slightly good compared
with prior schemes. Typically, the feature called Product
In view of circuit Layout area occupying, the foreseen
of Power Energy (Power * Delay* Power) offers more
5DC-DETFF uses the Layout area of 132µm2. This value
preference to power utilization compared with
is lowest one compared to the prior flip-flop schemes
propagation delay [18]. In view of Power Energy Product,
listed in table-1 and also reported in Fig.12.
the 5DC-DETFF scheme attains outstanding minimum
In account of global power intake, an offered 5DC- value of 0.348*10-20 and demonstrated in Fig.14. The
DETFF intakes the power of 5.181µW, which is very least Product of Power Energy (PEP) is enriched in the range
compared to prior flipflop structures and the same of 24.51% to 72.46 % for the anticipated 5DC-DETFF
reported in Fig.9 & Fig.13.An offered 5DC-DETFF which enunciates the anticipated flip-flop scheme is
accomplishes the power efficacy from 12.85% to 37.92% noteworthy and apposite for low power VLSI
compared to the prior flip-flop schemes ordered in Table- applications.
1. This very condensed global power usage makes the
5DC-DETFF as more appropriate for power effective
VLSI clocking organizations.

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IV. CONCLUSION operation”, IEEE Transactions on VLSI Syatems, Vol.29, No.5,

pp.1022-1032, 2021.
In this work, the overall less device count Duple edge [13] P.Nagarajan, R.Saravanan, and P.Thirumurugan, “Design of Register
triggering flip-flop 5DC-DETFF is offered by using the Element for Low Power Clocking System”, Information an
power efficient techniques of reduction of entire quantity interdisciplinary research, ISSN 1343-4500, vol.17, pp.2903-2913,
of devices usage, implicit clock pulse triggering, duple 2014.
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schema. By following the dynamic and pass transistor design featuring low power VLSI applications”, International Journal
of Engineering and Technology , vol. 8,pp. 1696-1705, 2016.
logic design styles an anticipated Flip-flop design is
[15] Jun-Young Park, Minhyun Jin, Soo-Youn Kim and Minkyu Song
realized with entirely 5 devices count. Another most 2022,” Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm
power proficient techniques called duple edge triggering CMOS Technology for Ultra Low-Power System Chips”, Electronics,
is used in this projected flip-flop and samples the data pp 01-10.
input D at an arrival of both up and down edges of the [16] Neethu Anna Sabu and K. Batri, “ Design and Analysis of Power
Triggering clock. The triggering clock is directly applied Efficient TG based Dual Edge Triggered Flip-Flops with Stacking
to an input port as implicit style, instead separate external Technique”, Journal of Circuits, Systems and Computers,
Vol..29,No.8, ,2020.
trigger clock generation network. It lowers the additional
[17] Pandian Nagarajan, Thandabani Kavitha et al “Power energy and
transistors usage for clock generation setup and also power area product simulation analysis of master-slave flip-flop.
diminishes the power excess. All these mechanisms (2023). Revue roumaine des sciences techniques — série
makes an anticipated topology, to intake an entire global électrotechnique et énergétique, ISSN (online): 00354066, December
power of 5.181µW and achieves the power efficacy from 2023.
12.85% to 37.92%. This significant power efficacy and [18] Dipanjan Sengupta and Resve saleh, “Power – Delay metrics Revisited
considerable speed performance tells that an offered 5DC- for 90nm CMOS Technology”, Proc. of the sixth international symp.
on ISQED, 2005.
DETFF will be adequate for low power digital VLSI
organisations.
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