Low Power Multistage

Amplifiers
For Large Capacitive Loads
By

Xiaohua Fan
Chinmaya Mishra
Edgar Sánchez-Sinencio

A M S C

See March 2005 issue in the IEEE JSSC

 Outline
• Introduction
• Design Considerations
• Existing approaches
• Proposed Approach (1)
• Proposed Approach (2)
• Experimental Results
• Discussion
• Conclusion
 Introduction
• Need for Low voltage Low power amplifier.
• High gain + low voltage multistage architecture
• High capacitive loads are required in error amplifiers
in a linear regulator which is a part of low power
portable devices.
• Large capacitive loads degrade the frequency
response.
• Robust Phase compensation technique required.
 Design Considerations
• Large Capacitive Load
• Low Power
• Less Area
• High Gain
• Moderate GBW and PM

Existing solutions in the

literature?
 Nested Miller Compensation
Cm1

Cm2

Vin gmL Vo
- + -
gm1 gm2 CL

AV 
g m1 g m 2 g mL 1  g mL 
GBW   
g p1 g p 2 g L 4  CL 

[4] R. G. H. Eschauzier etal. “A 100-MHz 100-dB operational amplifier with multipath nested miller compensation structure,”
IEEE Journal of Solid State Circuits, Vol. 27, pp. 1709-1717, Dec. 1992.
 NMC (contd..)
Stability analysis:
1 1
GBW  p2  p3
2 4
g m1 1 g m 2 1 g mL
 
Cm1 2 Cm 2 4 C L

Stability condition:
g mL  g m1 , g m 2
Cm1 and Cm2 very
 g m1 
C m1  4
g
C L
 large for large load!!
 mL 
 g m2 
Cm2  2
g
C L

 mL 
 Damping Factor-Control Frequency
Compensation (DFCFC)

Cm1

Vin gmL Vo
- + -
gm2
gm1 Cm2
CL

-
gm4
-
gmf2

[2] K. N. Leung et al., “Three Stage Large Capacitive Load Amplifier with Damping-Factor Control Frequency Compensation,”
IEEE Journal of Solid State Circuits, Vol.35, No.2, February 2000.
 DFCFC (contd.)

Stability condition:
g mf 2  g mL
4  g m1 
C m1   C L

  g mL 
C m1  Cm2  C p 2
 C p2 
g m4     g mL

 CL 
 CL  g m2
where  1  1  2 
 C p2  g mL
 
 Active Feedback Frequency
Compensation(AFFC)
Cm

gmL Vo
Vin
- + -
gm1 gm2 CL
g mf

-
Ca
Va
+
gma

[1] H. Lee, P. K .T Mok. , “Active-feedback frequency compensation technique for low-power multistage amplifiers, “
IEEE Journal of Solid State Circuits, Vol. 38, pp- 511-520, March, 2003.
 AFFC (contd.)

Stability condition:

g ma  4 g m1
g mf  g m 2
1
Ca  Cm  C m1( NMC)
N
 CL
whereN  8  

  g m1 g mf  g m 2 
2 
 C1   g mL 
 Proposed Solution 1
Single Miller Capacitor (SMC)

Cm

g mf
-
gmL
Vin Vo
- + -
gm2
gm1
Rp1 Cp1 Cp2 RL CL
Rp2
 SMC (contd.)
Transfer function analysis

ggmm2V
  g V2 sC
1V1in  gpp21V1
 0m (Vout  V1 )  0
sCp1pV21V2 sC
 g m3V2  g LVout  sCLVout  sCm (V1  Vout )  0


g m1 g m 2 g mL Cm 2 CmC P 2

1  s s 

g p1 g p 2 g L G meff g m 2 mL 
g 
H (s) 
 g g C  C C p 2C L 
1  s m 2 mL m  1  s L
s 2

 g p1 p 2 L  
g g  G g m 2 mL 
g
  meff 
g m2
G meff  g mL
g p2
 SMC (contd.)
Poles and Zeros:
g p1 g p 2 g L Gmeff
Poles: p1  z1  RHP
g m 2 g mL C m Zeros: Cm
g p2 Gmeff
p2 
g p2

Gmeff z2   LHP
C p2 CL C p2 Cm

p3 
Gmeff
z 2  z1  p1,2,3
CL

P1: Dominant Pole P2: Non-dominant Pole P3: Non-Dominant Pole

g m1 g m 2 g mL
AV 
g p1 g p 2 g L
GBW GBW GBW
PM  180 o  tan 1 ( )  tan 1 ( )  tan 1 ( )
p1 p2 p3
1 1 1 1 1 1
GBW  p2  p3 PM  180  90  tan ( )  tan ( )  49.40
0 0
2 4 2 4
 SMC (contd.)
Stability analysis:

1 1
GBW  p2  p3
2 4
g m1 1  g p 2 Gmeff  1 Gmeff
  

Cm 2  C p 2 
CL  4 CL

Stability condition:
4 g m1C L
Cm  Cm is small even for
Gmeff
CL large load!!
g mL  4 g m1  Cm 
Av 2
g p2 Gmeff

C p2 CL
 Cm

SMC (contd.) -
g mf

gmL
Vin Vo
- + -
gm2
gm1
Rp1 Cp1 Cp2 RL CL
Rp2

M b1 M b2 M 7,8
M9 Vb3
M12

Vb 2 M14
I bias M1,2 g mf
Vin  Vin  gm2 Cm
M 5,6
g m1 Vout

M13
Vb1

M 3,4 g mL
M10,11

gmf and gmL form a push-pull output stage

for better slew rate and settling time.
 Proposed Solution 2
Single Miller Capacitor Feedforward
Compensation (SMFFC)
Cm

gmf2

gmL
Vin Vo
- + -
gm2
gm1
Rp1 Cp1 Cp2 RL CL
Rp2

-
gmf1
 SMFFC (contd.)
Transfer function analysis

ggmmf1V1inVin
  gp1gVm
1 1
2VsC p1V1p 2 m(V
g 2VsC sC 2V
outp V12) 
00
ggmf V11  ggmL
mf 22V m3V22  g LVout  sCLVout  sCm (V1  Vout )  0

g m1 g m 2 g mL  g mf 1C m 2 Cm C P 2 
1  s s 
g p1 g p 2 g L  g g
m1 m 2 g m 2 mL 
g
H (s) 
  C g 
1  s g m 2 g mL Cm  1  s L p 2  s 2 C P 2C L 
 
 g p1 g p 2 g L  g m 2 g mL g m 2 g mL 
 SMFFC (contd.)
Poles and Zeros: Zeros:
g p1 g p 2 g L g m1 g m 2
p1  z1  LHP
Poles: g m 2 g mL C m g mf 1C m

g p2 Gmeff g mf 1 g mL g m1 g m 2
p2   z2   RHP
C p2 CL g m1C p 2 g mf 1Cm

p3 
Gmeff
z 2  z1
CL

P1: Dominant Pole P2: Non-dominant Pole P3: Non-Dominant Pole

g m1 g m 2 g mL 1 1
AV  GBW  p2  p3
g p1 g p 2 g L 2 4
GBW GBW GBW GBW
PM  180o  tan 1 ( )  tan 1 ( )  tan 1 ( )  tan 1 ( )
p1 p2 p3 z1
1 1 1
PM  1800  900  tan 1 ( )  tan 1 ( )  tan 1 ( )  750
2 4 2
 SMFFC (contd.)
Stability analysis:
1 1
GBW  p2  p3
2 4
g m1 1  g p 2 Gmeff  1 Gmeff
  
Cm 
2  C p2 
CL  4 CL

Stability condition:
4 g m1C L
Cm 
Gmeff
g mL  4 g m1  Cm 
CL Cm is much smaller
Av 2 even for large load!!
g p2 Gmeff

C p2 CL
g m1 g m2 g 02C p 2C L
g mf 1  2
( g 02C L  g m 2 g m3C p 2 )Cm
 Cm

gmf2

SMFFC (contd.) Vin

- + -
gmL
Vo

gm2
gm1
Rp1 Cp1 Cp2 RL CL
Rp2
Schematic
-
gmf1

M b1 M b2 M 7,8
M9 Vb3
M12
Vb
Vb 2 M14
I bias M1,2 g mf 2
Vin  Vin  g m2 Cm
M 5,6
g m1 Vout

M13
Vb1

Vb M b3 M 3,4
g m3
M10,11

M f 1,2
Vin  Vin 
g mf 1
Chip Micrograph

SMC

SMFFC
AC Response (SMC)
AC Response (SMFFC)
Transient Response (SMC)

Input

Output
Transient Response (SMFFC)

Input

Output
 Comparison Table
NMC DFCFC AFFC SMC SMFFC
This Work This Work
Load pF/KΩ 1 2 0 / 2 5 1 0 0 / 2 5 1 2 0 / 2 5 1 2 0 / 2 5 1 2 0 / 2 5

P o w e r S u p p l y
1V
DC gain (dB) >100 >100 >100 >100 >100
GBW (MHz) 0.4 2.6 4.5 4.6 9
Phase margin 61 o 43 o 65o 57o 57o
Power (mW@Vdd) 0.38 @2 0.42 @2 0.4 @2 0.38@2 0.41@2
Capacitor Value Cm1=88 Cm1=18 Cm=3 Cm=7 Cm=4
(pF) Cm2=11 Cm2=3 Ca=7
Slew Rate 0.15/0.13 1.36/1.27 2.20/0.78 3.28/1.31 4.8/2
SR+/ SR- (V/S)
Settling Time 4.9/4.7 0.96/1.37 0.42/0.85 0.53/0.4 0.58/0.43
TS+/TS- (s) (to 1%)
FOMS(MHz.pF/mW) 127 619 1350 1453 2634
FOML(V/s.pF/mW) 45 314 447 726 996
Area (mm2) 0.14 0.11 0.06 0.02 0.015
Normalized Area 9.33 7.33 4 1.33 1
Technology 0.8m 0.5m
CMOS CMOS
Note: Average value of the slew rate is used in the calculation of FOML parameter
GBW * C L SR * C L
FOM S  and FOM L  , where CTotal = Total value of compensation
Power Power
capacitors
 Conclusions
 Two low power multistage amplifier topologies are
introduced for large capacitive loads.
 Pole splitting and feedforward approaches are
combined for better performance.
 Performance parameters such as GBW and Area
are improved without sacrificing same power
consumption.
 The proposed approaches have better small-
signal and large-signal performances than other
reported compensation topologies .
A Robust Feedforward
Compensation Scheme for Multi-
Stage OTA’s with no Miller
capacitors

Thanks to Bharath Kumar Thandri and

Dr José-Silva Martínez for the material provided

ELEN 607 (ESS)

 Outline
• Need for high performance amplifiers
• Conventional approaches and problems
• Proposed NCFF compensation scheme
• Pole-zero mismatch effects
• OTA design
• Simulation and Experimental results
• Conclusion
 Need for high performance amplifiers

• Performance of integrator
degrades because of the Vi -
-Vo/A
amplifier characteristics Vo

• Output deviates from ideal +

value due to finite gain
• Settling time increases with
decreasing GBW
• Amplifiers with high gain and   Vi 
GBW are required in high  
precision ADC’s (pipelined, Vo   sRC 
sigma-delta etc) and switched 1 1  
 1    1
capacitor filters.  A  sRC  
 -vo

DC-gain
V in limitation
GBW & PM
limitation

Slew rate Step response of an amplifier with

limitation sufficient phase margin.
 Vo (t )  Vo (t0 ) 
Vi
1
1  e  GBW t

1
Av
g m
 GBW 
C2 C1  C3 
C4 
C1  C2  C3

 (=C1/C2) is the ideal amplifier gain,  (=C2/ (C1+C2+C3))

is the feedback factor and Av (=gm/g0)

C
2

C
1

v v v
in x o

C g v g C
3 0
m x 4
 Step response of an amplifier (continues)

 gbw t
Vo (t )  Vin (1  k1e )
k1  1

 is gainband width
gbw

of amplifier
• Two phases - slewing phase and quasi-linear phase
• Slew rate is limited by current available to charge/discharge the load capacitor.
Response is usually dominated by second phase
• High GBW => fast settling time ; High gain => accuracy ; sufficient phase
margin => no ringing or overshoot
• Best settling performance requires high performance amplifier
Contradicting requirements for Gain vs Bandwidth ?

• High gain amplifiers => multistage architectures,

low bias currents, large channel lengths
• High bandwidth amplifiers => single stage, high
bias currents, minimum channel lengths
• Difficult to obtain high gain and bandwidth
simultaneously
• Previous architectures settle for an optimal tradeoff
between speed and accuracy requirements
 Cascaded amplifiers

vi
Av01 Av02 vo
DC Gain  Av 01 * Av 02
• Cascade of individual gain stages gives high gain
• Poles created by each stage degrade phase response by -90°
• Stable closed loop operation => phase margin > 45°
• Robust phase compensation scheme is required for multi-
stage amplifiers
• Miller compensation (pole splitting/lead compensation) used
for two stage amplifiers has been extended for multi-stage
amplifiers
 Miller compensation for 2-stage amplifier

Disadvantages
• Miller effect of Cc pushes dominant pole to
1 gm2
lower frequencies => low GBW wp, d  wz , rhp 
• Non-dominant pole is pushed to higher rds1 Av 02Cc Cc
frequencies => more power consumption
• RHP zero is created by addition of Cc which
1
creates negative phase shift wz 
 1 
• Rz is used to cancel RHP zero Cc  Rz - 
 gm2 
Reported compensation schemes(cont)

• Damping factor frequency controlled

compensation (DFCFC) and embedded frequency
compensation schemes have also been reported.
• All reported schemes are often a variant of the
two-stage miller compensation and have similar
disadvantages
• A multistage feedforward compensated amplifier
has been reported by Cirrus Logic for low-noise
application, but it also uses compensation
capacitor
 EQUIVALENT BLOCK DIAGRAMS
A1 A2 Vo
Vin +
Vo   A1 A2  A2 Vin

A1 A2 Vo
Vin +
Vo   A1 A2  A2 Vin

A2
Vo   A1 A2  A3 Vin
A1 A2 Vo
Vin +
A2 and A3 must have only one pole.
Different gains are okay.
A3 The number of poles of A1 determines
the number of poles of the system.
 No-Capacitor FeedForward (NCFF)
compensation scheme
A1
H 1( s ) 
s
1
w p1

A2
H 2( s ) 
s
1
wp 2

• Main concept : Feedforward path with same phase  s 

A2  A1  1  

shift as compared to the normal path produces LHP V w
zeros. o
  p 1 
Vi  s  s 
• LHP zeros create positive phase shift and cancels 1   1  
 w   w 
the negative phase shift of poles  p 1  p 2 
• No pole splitting => improvement in BW
• Combines high gain, high GBW and good phase Avo  A1 A2  A2
margin
z1  ( A1  1) wp1
Miller vs NCFF compensation:Why the difference?
 Effect of non-dominant pole
A1
H 1( s) 
s s
(1  )(1  )
w p1,d w p1,nd

A2
H 2( s) 
s
1
wp 2

• Number of LHP zeros created is equal to

 s s 
the order of the first stage 
A2 A1  (1  )(1  )
 w w 
• Main constraint - No non-dominant pole o  V p1, d p1, nd 
of second stage before the overall GBW Vi  s  s  s 
1 1 1
• For N poles in the system, (N-1) LHP    
 w p1,d  w p1,nd  w p 2 
zeros are created => overall amplifier’s
response is effectively a single pole phase  s s 
response A2  A1  (1  )(1  )  0
 w p1,d w p1,nd 
 C
2

C
1

v v v
in x o

C g v g C
3 0
m x 4

Typical OTA based capacitor amplifier

-gm1 +gm2 vo

g01 C01 g02 C02

vin

-gm3

Block diagram of basic NCFF compensation scheme for 2-stage amplifier.

  s   

Av1 Av 2  Av 3 1 
  
 Av1 Av 2  Av 3  1 
 Av 3 s
  A A  A  

H ( s)    p1 
  v1 v 2 v3 p1 

     
1  s 1  s  1  s 1  s 
         
 p1  p2   p1  p2 

 A A  g g 
z1   p1 1  v1 v 2    m1  m 2 
 Av 3  C01  g m3 
 Optimization of Loop Equations
 C1   s 
   1 
v0 s   Z 
  
C2
vi s   1     
 s s
 1  1   
 1
AV        
   1  2 

 g m3  g 0  4CL ' g m1g m 2 

1  1  1   (7)
2CL '  C01 g m3  g 0 2 

g m3  g 0  4CL ' g m1g m 2 

2  1  1  
2CL '  C01 g m3  g 0 2 

g m3  4C2 g m1 g m 2 
z   1 2
 1
2C2  C01g m3 
  C1   1 2 
 Vi   1   1 
 
v0 (t )  v0 (t0 )   2  1  e  2t 
C Z
e 1t  Z
 1   1 2 
 1    1   1 
 AV    2  1 

4bCL'gm1gm2/(C01(bgm3+g0)2) < 0.5,

g   g m1 
 z   m 2    (10)
 g m3   C 01 

g m1g m 2
1  (11)
C01 g m3  g 0 

g m3  g 0
2 
CL '
Extending the scheme to multi-stage amplifiers:
Conceptual Representation

• Constraint - Last stage should not have non-

dominant pole before overall GBW
• Number of LHP zeros is one less than the total
number of poles in the system
 NCFF compensation scheme for
N-Stage Amplifier Implementation

gm1 gm2 gm3 gm4 gmn vo

gm2'
vin
gm3'

gm4'

gmn'
 Main features of NCFF compensation
scheme
• Combines high gain and GBW, resulting in a good
settling time and accurate final value
• Good phase margin - when zero exactly cancels the
pole, phase margin is 90°
• No compensation capacitors => lot of reduction in
area, esp for multi-stage amplifiers with 2 or more
compensation capacitors
• Disadvantage - pole-zero mismatch due to process
variations. Pole-zero doublet affects settling time
and phase margin
 Effect of pole-zero doublet

• Pole zero doublet causes minor change in

frequency response, but may degrade the settling
time based on their spacing and the zero frequency
• For more accuracy (0.01%), lower frequency
doublet causes more degradation in settling time
because of higher time constant
• For lesser accuracy(0.1%) higher frequency
doublet will cause more degradation because of its
larger amplitude, though it decays faster
 Effect of pole-zero mismatch

 t 
 
A) Settling time  wg t  2 
Vo (t )  Vin (1  k1e  k2 e )
• Settling time depends on pole-zero
mismatch and zero frequency
• When pole-zero cancellation is at wz  w p 1
k2  ; 2 
high frequencies , effect is very wg wz
minimal
w g  GBW
w z  zero ; w p  p ole
Effect of pole-zero mismatch(cont)
z1  ( A1  1) wp1 z1  p2
Overall GBW  A2 ( A1  1)wp1

B) Phase margin and stability

Two scenarios
• When zero occurs before the pole, it improves the phase
margin
• When pole occurs before zero : It is always stable when the
gain of the second stage > 1. It can be unstable when the
second stage is an attenuator
• Since cancellation is done at high frequencies, percentage
change due to process variations is relatively small
 Gain distribution

• First stage - High gain and low bandwidth

• Feedforward and second stage - low gain and high
bandwidth
 Closed- loop
Open-loop

AV1 AV2 AV1 AV2

pole-zero pair pole-zero pair

AV3 AV3
C1/C2 C1/C2
 
Z Z
(a) (b)

Amplifier frequency response and pole-zero locations in open and closed loop.
a) Perfect pole-zero cancellation b) Pole-zero mismatch .
 Parasitic capacitance in feedforward path

• Parasitic Cgd capacitance in the feedforward path

exists from input to output node
• When used in closed loop, it is in parallel to
feedback capacitor and attenuates the signal
• Possible solution - use cascode amplifier in the
feedforward stage
Single-ended amplifier (first try)
 VDD

M6 M6 M7 M7

V BP •
M5 M5
• v0
• •
V BN
M4 M4

M2 M2
M1 M1
I B1 I B2
VSS
VSS

• • vi
M3 M3
I B3

VSS
 Fully Differential Amplifier

Second and
First stage - High gain feedforward stage
telescopic cascode Differential amplifier
Fully differential amplifier (cont.)

Common-mode feedback for first stage

 Fully differential amplifier (cont)

gm4
 z1 

C gs19  Av 2C gd19 

1
 p2 
rds22 || rds20 || rds14 || rds16 CL
1
 p1 

g m6 rds6 rds4  || g m8 rds8rds10  Cgs19  Av 2Cgd19 
 Modified fully differential amplifier

gm4
 z1 

C gs19  Av2C gd19 

1
 p2 
rds22 || rds20 || g m16rds16rds143CL
1
 p1 

g m6 rds6 rds4  || g m8 rds8rds10  Cgs19  Av2Cgd19 
Chip microphotograph (AMI 0.5µm technology)
 1.2

0.8
Voltage (Volts)

0.4

vinput voutput

0.0

-0.4
0E+0 1E-8 2E-8 3E-8 4E-8 5E-8
Time (Secs)

Post-layout simulation results for the capacitive amplifier. Pulse

response with a real input signal, including all parasitic capacitors. 1 %
settling time is around 14 ns.
 Post-layout simulations for OTA’s
designed in AMI 0.5µm technology
Parameter Single-ended Fully
OTA differential
OTA
DC gain (dB) 94 97

Gainbandwidth (MHz) 300 350

Phase Margin (deg) 74 90

1% settling time (ns) * 6.3 5.1

Current consumption (mA) 5.36 7.16

Power supply  1.25  1.25

Load capacitor = 12 pF
* PCB and probe parasitics not included; ideal step input
 10 pF
0.4
7 pF
3 pF
0.3 1 pF
Voltage (Volts)

0.5 pF
0.2
0.25 pF

0.1

0.0

-0.1

0.0E+0 5.0E-9 1.0E-8 1.5E-8 2.0E-8

Time (Secs)

Pulse response post-layout simulation – parametric

sweep of feedback and load capacitors.
Simulation plots for single-ended amplifier
Simulation plots for differential amplifier
Experimental results :Step response of amplifier
(Falling step input)
. Measured pulse response for large input signal.
 Remarks

• NCFF compensation scheme for multi-stage amplifiers

was presented.
• Compensation scheme uses positive phase shift of LHP
zeros to cancel negative phase shift of poles. It combines
high gain, GBW and good phase margin
• Other potential optimal NCFF implementations are
possible by meeting the poles and number of poles of
individual blocks conditions.
• How much saving in power and area versus other schemes
such as DFCFC need to be explored
 A 92 MHz 80 dB peak SNR SC
Bandpass ΣΔ ADC based on NCFF
OTA’s in 0.35µm CMOS technology

Bharath Kumar Thandri and Jose Silva Martinez

AMSC, Texas A&M University
College Station, Texas
Presented at CICC 2003

Reference: A 92MHz, 80dB peak SNR SC bandpass Sigma Delta modulator based on a high GBW OTA with no Miller
capacitors in 0.35 um CMOS technology
Thandri, B.K.; Martinez, J.S.; Rocha-Perez, J.M.; Wang, J.; Custom Integrated Circuits Conference, 2003. Proceedings
of the IEEE 2003 , 21-24 Sept. 2003 Pages:123 - 126
 Modulator architecture
V in

FI R ST R E SON A T O R SE C O N D R E SO N A T OR
b3
b1 b2
g2
g1

1 z -1
V dig_out
1 z -1 c3
1 - z -1 1 - z -1
c1 c2
1 - z -1 1 - z -1

a4
a2 a3
a1

• 4th order cascade of resonators in feedback

• Resonator – inverting and non-inverting
integrator with local feedback
• For stability, out-of-band gain of NTF =1.5
• Simulations in Matlab/Simulink
• Signal swing, capacitance spread and SNR
 Amplifier requirements
Ca Cf
Vi- Vo+ 1
Error 
Vi+ Vo- Avo
Ca
Cf Avo  DC gain

  Feedback factor Slew Limited by

limit GBW and PM

GBW
 5 f clock ωGBW  Gain bandwidth
2
10 f clock
f GBW 
2
• Amplifier non-idealities : Finite DC gain and GBW
• Gain > 70 dB and GBW > 1 GHz for fs =100 MHz and SNR > 85 dB
 Amplifier design
• Two stage amplifier with NCFF compensation
scheme
• First stage : High gain stage
• Second and Feedforward stage : Medium gain
and high BW
• Pole-zero cancellation at high frequencies
 Amplifier (final version)
VDD VDD
Vcmfb2
Vcmfb1 M4 M4 Vcmfb1 M8 M8 Vcmfb2
Vo- Vo+
Vbp M3 M3 Vbp • Use cascode in FF stage
Vbn1
M7 M7
• Conventional CMFB for both
M2 M2 Vbn1
stages
Vi+ M1 M1 Vi- • CMFB capacitors increase
VSS loading at output
• Bias network to fix Vg of
VSS
M2,M3 and M6
Vbn2 M6 M6 Vbn2 • Currents
First stage = 100 μA
Vi+ M5 M5 Vi-
Second stage = 1.25 mA
FF stage = 3.25 mA

VSS
 Amplifier performance
Parameter CICC 2002 [*] This design
DC gain 61 dB 80 dB
GBW 430 MHz 1.4 GHz
Phase margin 61° 62°

Current 9 mA 4.6 mA
Settling time N/A 2 ns
(CLOAD) ( 2pF)
Architecture Single-stage folded Two-stage with
cascode NCFF scheme
Technology 0.35µm CMOS 0.35µm CMOS

[*] T. Salo et al, “An 80 MHz 8th-order bandpass ΔΣ modulator with a 75 dB

SNDR for IS-95 “, CICC, May 2002
 1
4th order Modulator
Ca 1
1
V da c - Ca 3
V da c -
2 V re f+
2
Ca 4 1

V da c - V da c +
Cg 1 1
Vi +
1 Cb 2 2
2 2 V re f-
Cg 2

1 Cb 3
2 2 1
V i- 1

Cf 1 Cf 2 2
Cf 3 Cf 4

2
1 Cb 1 1 Cc 1 1
1 COM PARAT OR
V i+ 1 Cc 2 1 Cc 3 2

2 2 1 2 V d ig _ o u t+
2 2 2 1

1 1 2 1
Cb 1 Cc 1
1 V d ig _ o u t-
V i- 1 Cc 2 1 Cc 3 2

2 2 1 2
Cf 2 2
2 2 1
Cf 4
Cf 1
1 Cf 3
Cg 1
1 2 2
Cb 2 Cg 2

2
Vi -
1 Ca 4 1 V da c - V re f-
Cb 3
2 1 V i+ 1 V da c +
1 2
Ca 1 2
V da c + Ca 3 1

2
V da c + V re f+
2

• Two-stage latched comparator

• Single-bit DAC – inherently linear
• NMOS switches with boosted clock voltage (2.5V)
• RC time constant of switches limit the speed of operation
 Measurement setup
Signal generator Spectrum analyzer

• Output bit stream is directly injected into spectrum analyzer

• SNR measurement is a conservative estimate as it includes noise
in the bit stream
• Modulator works properly @110 MHz clock
• SNR degrades for fs > 92 MHz
 Measurement results

-127 dBV / Hz

0 Hz 23 MHz 46 MHz
• Noise floor is measured by grounding inputs
• Includes quantization and circuit (kT/C) noise
• Fs = 92 MHz
 Output spectrum
5 MHz span 100 Hz span
-7.1
dBm

23 MHz 23 MHz

Signal power
SNR  SNR = 80 dB (270 kHz)


BW
Noise power SNR = 54 dB (3.84 MHz)
Fs = 92 MHz
 Two tone IMD test
-12 dBm

-70 dBm

22.9 MHz 23.1 MHz

• Two tone input @ -11 dBr, 23.1 and 22.9 MHz
• Measured IMD3 = -58 dB
 Plot of SNR vs input amplitude
90

80 dB 80

70

60
SNR [dB]

50

40

30

20

10
-80 -70 -60 -50 -40 -30 -20 -10 0
Input amplitude [dB]

-12 dB
Performance summary of the modulator
Technology TSMC 0.35μm
CMOS
Peak SNR for 270 KHz BW 80 dB

Peak SNR for 3.84 MHz BW 54 dB

IMD3 @ -11dBr input -58 dB

Supply voltage ±1.25V
Power consumption 47.5 mW
Sampling frequency 92 MHz
Core area 1.248 mm2
 References
S. Pernici, “A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested
Miller Compensation,” IEEE J. Solid-State Circuits, Vol. 28, No. 7, pp. 758-763, July 1993.

F. You, S.H.K. Embabi and E. Sánchez-Sinencio, “Multistage Amplifier Topologies with

Nested Gm-C Compensation,” IEEE J. of Solid-State Circuits, Vol. 32, No. 12, pp. 2000-2011,
December 1997.

X. Xie, M.C. Schneider, E. Sánchez-Sinencio and S.H.K. Embabi, “ Sound Design of low power nested
transconconductance-capacitance compensation amplifiers” Electronics Letters, Vol. 35, No. 12, pp956-
958, June 1999

K.N. Leung, P.K. T. Mok, W.-H. Ki, and J. K. O. Sin, “ Three-Stage Large Capacitive Load
Amplifier with Damping Factor-Control Frequency Compensation, “IEEE J. of Solid-State
Circuits, Vol. 35, No. 2, pp. 221-230, February 2000

B.K. Thandri, , and J. Silva-Martinez, “ A Feedforward Compensation Scheme for Multi-Stage Amplifiers
with No-Miller Capacitors”, IEEE J. Solid State Circuits, Vol. 38, pp. 237-243, Feb. 2003.

X. Fan, C. Mishra and E. Sánchez-Sinencio, “Single Miller Capacitor Frequency

Compensation Technique for Low Power Multistage Amplifiers,” IEEE Journal of Solid-State
Circuits, Vol. 40, No. 3, March 2005.

Analog & Mixed-Signal Center (AMSC)