CHAPTER 4

i8086 SYSTEM MODE AND COPROCESSORS

3/31/2025 By Eng A4K 1

Pin Description of i8086

The is as follows:
• AD0-AD15 (Address Data Bus): Bidirectional
address/data lines. These are low order address
bus. They are multiplexed with data. When these
lines are used to transmit memory address, the
symbol A is used instead of AD, for example, A0-
A15.
• A16 - A19 (Output): High order address lines.
These are multiplexed with status signals.
• A16/S3, A17/S4: A16 and A17 are multiplexed
with segment identifier signals S3 and S4.
• A18/S5: A18 is multiplexed with interrupt status
S5.
• A19/S6: A19 is multiplexed with status signal S6.

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 • BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data
onto the most significant half of data bus, D8-D15. 8-bit device connected to
upper half of the data bus use BHE signal. It is multiplexed with status signal S7.
S7 signal is available during T3 and T4.
• RD (Read): For read operation. It is an output signal. It is active when LOW.
• Ready (Input): The addressed memory or I/O sends acknowledgment through
this pin. When HIGH, it denotes that the peripheral is ready to transfer data.

• RESET (Input): System reset. The signal is active HIGH.

• CLK (input): Clock 5, 8 or 10 MHz.
• INTR: Interrupt Request.
• NMI (Input): Non-maskable interrupt request.
• TEST (Input): Wait for test control. When LOW the microprocessor continues
execution otherwise waits.
• VCC: Power supply +5V dc.
• GND: Ground.

3/31/2025 by eng A4k 3

I8086 system mode:

Minimum Mode 8086 System

• The Microprocessor 8086 is operated in minimum mode by strapping its MN/MX
pin to logic 1.
• In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
• The remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices.
• Some type of chip selection logic may be required for selecting memory or I/O
devices, depending upon the address map of the system.
• The clock generator generates the clock from the crystal oscillator and then
shapes it and divides to make it more precise so that it can be used as an accurate
timing reference for the system.
• The clock generator also synchronizes some external signal with the system clock.
• The working of the minimum mode configuration system can be better described
in terms of the timing diagrams rather than qualitatively describing the
operations.

3/31/2025 by eng A4k 4

 • The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the
second is the timing diagram for write cycle
• The read cycle begins in T1 with the assertion of address latch enable (ALE) signal
and also M / IO signal. During the negative going edge of this signal, the valid
address is latched on the local bus.
• The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M/IO
signal indicates a memory or I/O operation.
• At T2, the address is removed from the local bus and is sent to the output. The bus
is then tri-stated. The read (RD) control signal is also activated in T2
• The read (RD) signal causes the address device to enable its data bus drivers. After
RD goes low, the valid data is available on the data bus.
• A write cycle also begins with the assertion of ALE and the emission of the
address. The M/IO signal is again asserted to indicate a memory or I/O operation.
In T2, after sending the address in T1 the processor sends the data to be written to
the addressed location.

3/31/2025 by eng A4k 5

 Maximum Mode i8086 System
• In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
• In this mode, the processor derives the status signal S2, S1,S0. Another chip called
bus controller derives the control signal using this status information .
• In the maximum mode, there may be more than one microprocessor in the system
configuration.
• The components in the system are same as in the minimum mode system.
• Here the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the available control and advanced
command signals.
• S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse
as on the ALE and apply a required signal to its DT / R pin during T1.
• In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4.
• For an output, the AMWC or AIOWC is activated from T2to T4 and MWTC or IOWC is
activated from T3to T4.
• The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
• If reader input is not activated before T3, wait state will be inserted between T3 and
T4.

3/31/2025 by eng A4k 6

i8086 Coprocessor
• A coprocessor is a computer processor used to supplement the functions of the primary
processor (the CPU).
• Operations performed by the coprocessor may be floating point arithmetic, graphics, signal
processing, string processing, cryptography or I/O interfacing with peripheral devices.
Way co-processor?
• A microprocessor designed at specified architecture is not good at all kinds tasks but good and
efficient at some kind. Categorizing a microprocessor at their decantation came for this reason.
They perform efficiently at their dedicated task. In order to get accelerated performance
cooperating kinds of processor for proposed system is required.
But How?
• By offloading processor-intensive tasks from the main processor.
• Main processor is a processor around which all other processors are gathered.
• The processor Governs all other processors by dispatching tasks that they are dedicated to.
• Thus it is called central processor unit.

3/31/2025 by eng A4k 7

Functional Features:

• Coprocessors vary in their degree of autonomy.

• Some (such as FPUs) rely on direct control via coprocessor instructions, embedded in the CPU's
instruction stream.
• Others are independent processors in their own right, capable of working asynchronously; they are
still not optimized for general-purpose code, or they are incapable of it due to a limited instruction
set focused on accelerating specific tasks.
• It is common for these to be driven by direct memory access (DMA), with the host processor(CPU)
building a command list.
• Direct memory access (DMA) is a feature of computer systems that allows certain hardware
subsystems to access main system memory (random-access memory) independent of the central
processing unit (CPU)
• The PlayStation 2's Emotion engine contained an unusual DSP-like SIMD vector unit capable of
both modes of operation.

3/31/2025 by eng A4k 8

Principles:
✓ Third-party:
Standard DMA, also called third-party DMA, uses a DMA controller. A DMA controller can generate
memory addresses and initiate memory read or write cycles.
✓ Bus mastering:
Also known as a first-party DMA system, the CPU and peripherals can each be granted control of
the memory bus. Where a peripheral can become a bus master, it can directly write to system
memory without the involvement of the CPU, providing memory address and control signals as
required. Some measures must be provided to put the processor into a hold condition so that bus
contention does not occur.
Modes of operation:
✓ Burst mode:
An entire block of data is transferred in one contiguous sequence
✓ Transparent mode:
In transparent mode, the DMA controller transfers data only when the CPU is performing
operations that do not use the system buses. The primary advantage of transparent mode is
that the CPU never stops executing its programs and the DMA transfer is free in terms of time,
while the disadvantage is that the hardware needs to determine when the CPU is not using the
system buses, which can be complex. This is also called as "Hidden DMA data transfer mode".

3/31/2025 by eng A4k 9

✓ Cycle stealing mode:
• used in systems in which the CPU should not be disabled for the length of time needed
for burst transfer modes.
• In the cycle stealing mode, the DMA controller obtains access to the system bus the
same way as in burst mode, using BR (Bus Request) and BG (Bus Grant) signals, which
are the two signals controlling the interface between the CPU and the DMA controller.
• However, in cycle stealing mode, after one byte of data transfer, the control of the
system bus is reasserted to the CPU via BG. It is then continually requested again via
BR, transferring one byte of data per request, until the entire block of data has been
transferred.
• By continually obtaining and releasing the control of the system bus, the DMA
controller essentially interleaves instruction and data transfers.
• The CPU processes an instruction, then the DMA controller transfers one data value,
and so on. On the one hand, the data block is not transferred as quickly in cycle
stealing mode as in burst mode, but on the other hand the CPU is not idled for as long
as in burst mode.
• Cycle stealing mode is useful for controllers that monitor data in real time.

3/31/2025 by eng A4k 10

 Intel 8087 floating-point coprocessor

• In that architecture, the coprocessor speeds up floating-point arithmetic on the order of fiftyfold.
Users that only used the PC for word processing, for example, saved the high cost of the coprocessor,
which would not have accelerated performance of text manipulation operations.
• The 8087 was tightly integrated with the 8086/8088 and responded to floating-point machine code
operation codes inserted in the 8088 instruction stream.
• An 8088 processor without an 8087 could not interpret these instructions, requiring separate versions
of programs for FPU and non-FPU systems, or at least a test at run time to detect the FPU and select
appropriate mathematical library functions.
• Intel 80386DX CPU with 80387DX math coprocessor
• Another coprocessor for the 8086/8088 central processor was the 8089 input/output coprocessor. It
used the same programming technique as 8087 for input/output operations, such as transfer of data
from memory to a peripheral device, and so reducing the load on the CPU. But IBM didn't use it in
IBM PC design and Intel stopped development of this type of coprocessor.
• The Intel 80386 microprocessor used an optional "math" coprocessor (the 80387) to perform floating
point operations directly in hardware.

3/31/2025 by eng A4k 11

 The block diagram of 8087

Control Numeric control unit

unit

3/31/2025 by eng A4k 12

 Pin Diagram of 8087

• INT:- Interrupt output used to indicate unmasked exception

has been received during execution
• BUSY:-o/p signal ,When high ,indicates instruction.
• READY:- i/p signal used to inform the coprocessor that the
addressed device will complete the data transfer from its
side & the bus is likely to be free for the next cycle
• RESET:- i/p Signal used to abandon the internal activities of
coprocessor & prepare it for further execution
• CLK:-Provide CLK input
• VCC:-Supply +5 V
• GND :-Power supply
• S2 ,S1 & S0 :- 8087 driven or externally driven by CPU.

3/31/2025 by eng A4k 13

 SIGNAL DESCRIPTIONS OF 8087
• AD0 –AD5 :- Time multiplexed address/data lines. These lines carry address during
T1 & data during T 2 , T3, TW& T4 states. A0 used when transfer is an lower
byte(D0-D7) of data bus, to derive chip select. These act as input lines for CPU
driven bus cycle.
• A19/S6-A16/S3 :- Time multiplexed address/status lines.
1. These functions are similar to the pins of 8086
2. S6,S4 & S3 are permanently high , S5 permanently low.
• BHE/S7 :-During T1 BHE/S7 pin used to enable data on the higher byte of 8086
data bus .During T 2 , T3, TW& T4 status line S7
• QS1-QS0 :- Queue status i/p signal, enable 8087 to keep track of prefetch status of
the CPU.
Status of these lines is decoded as:-
QS1 QS0 Queue status
0 0 No Operation
0 1 First byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue

3/31/2025 by eng A4k 14

 If these are driven by 8087
S2 S1 S0 Queue status
0 X X Unused
1 0 0 Unused
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive

• RG/GT6:-Request/Grant pin used to gain control of bus from host 8086/8088 for
operand transfer.
• An active low pulse of one clock duration generated for the host to inform it that it
wants to gain control of the local bus either for itself or for other Co processor
connected to RQ/GT Pin.
• RQ/GT1:- Bidirectional pin used by other bus masters to convey their need of local
bus access to 8087.

3/31/2025 by eng A4k 15

 REGISTER SET OF 8087
• Set of 8 bit registers
• Used either as a stack or a set of general registers
• When operating as a stack, it operates from the top on one or two registers
• While operating as a register set used only with the instruction designed for them.
• ·Divided into three
1. Sign(1 bit)
2. Exponent(15 bits)
3. Significant(64 bits)
• Two bit tag field to indicate the status of contents
• Instruction may address data registers either implicitly or explicitly
• An internal status register field Top is used to address any one of the eight
registers implicitly. While explicitly addressing the registers, They may be
addressed relative to Top.

3/31/2025 by eng A4k 16

 STATUS WORD OF 8087

15 0
TAG (7) TAG(6) TAG (5) TAG (4) TAG (3) TAG (2) TAG (1) TAG (0)

TAG VALUES
00=VALID 01ZERO
10=SPECIAL 11=EMPTY

✓ B0- B5 :- Indicate that an exception has been deleted

✓ B7 :- bit set if any unmasked exception has been detected otherwise cleared
✓ B12 – B14:-3 bits are used as the current top of the stack pointer to any of these eight
registers.
✓ B6 – B10& B14:- 4 condition code bits reflects as status of the results calculated by
8087
✓ B15 :- Busy bit shows the status NEU B14 =1, NEU is busy with execution otherwise
free.

3/31/2025 by eng A4k 17

 CONDITION CODE TABLE
Instruction type C3 C2 C1 C0 Interpretation
compare test 0 0 X 0 ST>Source or 0(FTST)
0 0 X 1 ST>Source or 0(FTST)

0 0 X 0 ST>Source or 0(FTST)
Remainder 1 0 X 1 Complete reduction with three low bits of
quotient
Q1 0 Q0 Q2
incomplete reduction
U 1 U U Valid, positive un normalized
0 0 0 0 Invalid,positive, exponent=0
0 0 0 1 Valid, negative, un normalized
0 0 1 0 Valid, negative , exponent=0
0 0 1 1 Invalid, positive, normalized
0 1 0 0 Valid, positive, normalized
0 1 0 1 Infinity, positive
0 1 1 0 Valid, negative, normalized
Examine 0 1 1 1 Infinity, negative
1 0 0 0 Zero, positive
1 0 0 1 Empty
1 0 1 0 Zero, negative
1 0 1 1 Empty
1 1 0 0 Invalid, positive, exponent=0
1 1 0 1 Empty
1 1 1 0 Invalid, Negative, exponent=0
1 1 1 1
3/31/2025 by eng A4k 18
 Instruction & Data pointer: - Used to enable the programmers to write their own
exception handling subroutines. Before executing a mathematical instruction, the
8087 forms a table in memory containing the instruction address in the field of
instruction, operand address in the field of data pointer TAG word Status word
Control word in their respective fields table

CONTROL WORD REGISTER

Allows the programmer to select the required processing options out of available
once
16 – bit control word register is used to control the operation of 8087
B0- B5 used for masking the different

3/31/2025 by eng A4k 19

 Interfacing of 8087 Math Co Processor

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 • 8087 can be connected with CPU only in max.mode, i.e wen MN/MX pin is grounded.
• In max. mode, all control signals are derived using a bus controller.
• Multiplexed address-data bus lines are connected directly from the 8086 to 8087.
• The status lines and the queue status lines connected directly from 8086 to 8087.
• The QS0 and QS1 lines may be directly connected to corresponding pins in case of
8086/88 based systems.
• The Request/Grant signal RQ/GT0 of 8087 is connected to 𝑅𝑄/𝐺𝑇1of 8086.
• The clock pin of 8087 connected with CPU 8086/88 clock i/p.
• The interrupt o/p of 8087 is routed to 8086/88 via a programmable interrupt
controller.
• The pins AD0-AD15,𝐵𝐻𝐸/𝑆7,RESET,A19/S6-A16/S3 r connected to corresponding
pins of 8086
• 𝐵𝑈𝑆𝑌 signal 8087 is connected to TEST pin of 8086.
• Interrupt o/p INT of the 8087 to NMI input of 8086. This intimates an error
• condition.
• A 𝑊𝐴𝐼𝑇 instruction is passed to keep looking at its TEST pin, until it finds pin Low to
indicates that the 8087 has completed the computation

3/31/2025 by eng A4k 21

 • SYNCHRONIZATION must be established between the processor and coprocessor
in two situations.
a) The execution of an ESC instruction that require the participation of the
NUE must not be initiated if the NUE has not completed the execution of
the previous instruction.
b) When a processor instruction accesses a memory location that is an
operand of a previous co processor instruction .In this case CPU must
synchronize with NPX to ensure that it has completed its instruction.
Processor WAIT instruction is provided.

Other Arithmetic coprocessor

• The numeric or arithmetic coprocessor is a special purpose microprocessor that
is especially designed to efficiently execute arithmetic and transcendental
operations.
• The Intel family of arithmetic coprocessor includes the 8087, 80287, 80387SX,
80387DX, and the 80487SX.
• The 80486DX to Pentium_4 microprocessors contain their own built-in
arithmetic coprocessors (a fully –compatible versions of 80387).

3/31/2025 by eng A4k 22

 • The Intel family of coprocessors, which is labeled the 80x87 is able to multiply, divide,
add, subtract, find the square root, calculate the partial tangent, logarithms,
etc………..
• Data types include 16-, 32-, 64- bit signed integers; and 32-, 64-, 80-bit floating point
numbers.

80x87 coprocessor
• The operations performed by 80x87 generally execute faster than equivalent
operations written with the programs that use microprocessor’s normal
instruction set.
• With the improved Pentium coprocessors, operations are at about 5 times faster
than those performed by the 80486 microprocessor.
• The 80x87 executes 68 different instructions.
• The host microprocessor executes all normal instructions and 80x87 executes
arithmetic coprocessor instructions only.
• Both the host microprocessor and coprocessor can execute their respective
instruction concurrently.

3/31/2025 by eng A4k 23

 Microprocessor Co-processor .
8086 8087
8088 8087
80186 80187
80188 80187
80286 80287
80386SX 80387SX
80386DX 80387DX
804868X 80487SX
8048SDX Built into microprocessor
Pentium Built into microprocessor
Pentium Pro Built into microprocessor
Pentium II Built into microprocessor
Pentium III Built into microprocessor
Pentium 4 Built into microprocessor

3/31/2025 by eng A4k 24

8087 Math Coprocessor:

1. Intel 8087 is a processor with architecture and instruction set optimized for performing complicated
arithmetic operations.
2. An 8087 is along with the host microprocessor 8086 rather than serving as the main processor itself.
Therefore, it is referred to as the coprocessor.
3. An 8087 instruction may perform a given mathematical computation 100 times faster than the
equivalent sequence of 8086 instructions.
4. 8087 is an actual processor with its own specialized instruction set. Instructions for 8087 are written
in the program as needed, interspersed with 8086 instructions.
5. As the 8086 fetches instruction bytes from the memory and puts them in its queue, the 8087 also
reads these instruction bytes and puts them in its queue. The 8087 decodes each instruction that
comes into its queue.
6. When 8087 decodes an instruction from its queue and finds that it is an 8086 instruction, the 8087
simply treats the instruction as NOP.
7. Likewise, when the 8086 decodes an instruction from its queue and finds that it is an 8087
instruction, the 8086 simply treats the instruction as NOP or in some cases reads a data word from
the memory for the 8087.
8. Each processor decodes all instructions in the fetched instruction byte stream but executes only its
own instructions.
 I8087 instruction sets
The Intel 8087 is a floating-point coprocessor designed to work with the 8086/8088 CPUs. It accelerates
complex mathematical operations, including trigonometry, logarithms, and arithmetic. Below is a
breakdown of its instruction set and a coding example.
Key Instruction Categories:
Data Transfer instruction:
FLD: Push a floating-point value onto the register stack.
FST: Store the top of the stack (ST(0)) into memory (without popping).
FSTP: Store and pop the stack.
FILD: Load an integer from memory into the stack.
Arithmetic instruction:
FADD/FADDP: Add values. Control instructions:
FSUB/FSUBP: Subtract values. FINIT: Initialize the 8087.
FMUL/FMULP: Multiply values. FSTSW: Store the status word (e.g., for conditional
FDIV/FDIVP: Divide values. jumps
FSQRT: Compute square root of ST(0).
Comparison instructions:
FCOM: Compare ST(0) with a value (sets status flags).
FTST: Compare ST(0) with 0.0.
Transcendental Functions
FSIN/FCOS: Compute sine/cosine of ST(0) (in radians).
FPTAN: Compute tangent of ST(0).
).
Key Components of the 8087 Instruction Sets
1. Data Transfer Instruction format
FLD src: Push a floating-point value (from memory or register) onto the stack.
FST dest: Store the top of the stack (ST(0)) into memory.
FSTP dest: Store ST(0) into memory and pop the stack.
FILD src: Load an integer from memory into ST(0).
FIST dest: Store ST(0) as an integer to memory (without popping).
FISTP dest: Store ST(0) as an integer and pop the stack.
2. Arithmetic Instructions format since it is operation on stack(zero address instruction), the operation is
done the top elements whether the operator is unary or binary
FADD: Add two values (e.g., FADD ST(0), ST(1) or FADD [mem]).
FSUB: Subtract (e.g., FSUB ST(0), ST(1) subtracts ST(1) from ST(0)).
FMUL: Multiply.
FDIV: Divide.
FSUBR: Reverse subtract (computes src - ST(0)).
FDIVR: Reverse divide (computes src / ST(0)).
FSQRT: Compute square root of ST(0).
3. Comparison Instructions and operational description
FCOM src: Compare ST(0) with src (memory or register).
FCOMP: Compare and pop the stack.
FCOMPP: Compare ST(0) with ST(1) and pop twice.
FTST: Compare ST(0) with 0.0.
4. Transcendental Functions and computational description
FPTAN: Compute partial tangent of ST(0) (result in ST(0) and ST(1)).
FPATAN: Compute arctangent of ST(1)/ST(0) and pop twice.
F2XM1: Compute 2𝑆𝑇(0) −1.
(𝑆𝑇 0 )
FYL2X: Compute ST(1)⋅𝑙𝑜𝑔2
5. Instructions work with Constants
FLD1: Push 1.0 onto the stack.
(𝑒)
FLDL2E: Push 𝑙𝑜𝑔2 natural logarithm
FLDPI: Push π. The constant pi
FLDZ: Push 0.0.
6. Control Instructions
FINIT: Initialize the coprocessor (reset registers and control word).
FSTSW dest: Store the status word (e.g., to check comparison results).
FLDCW src: Load the control word (set rounding modes, precision).
Coding Example: Calculate the Area of a Circle
Formula:
Area=π×r2

ASSUME DS:DATA, CS: CODE, SS:STACK

DATA SEGMENT
radius dd 5.0 ; 32-bit float for radius
pi dd 3.14159265 ; 32-bit float for π
result dd ? ; Store the result
ENDS
CODE SEGMENT
MAIN PROC
FINIT ; Initialize 8087
FLD radius ; Load radius into ST(0)
FMUL st(0), st(0) ; ST(0) = radius^2
FLD pi ; Push π into ST(0), radius² now in ST(1)
FMULP st(1), st(0) ; ST(1) = π * radius², then pop (result in ST(0))
FST result ; Store result into memory
; Exit to DOS
HLT
MAIN ENDP
Code Explanation
• FINIT: Initializes the coprocessor (resets registers and control word).
• FLD radius: Pushes the radius value onto the 8087 stack (ST(0)).
• FMUL st(0), st(0): Squares the value in ST(0) (radius * radius).
• FLD pi: Pushes π onto the stack; squared radius moves to ST(1).
• FMULP st(1), st(0): Multiplies ST(0) (π) with ST(1) (radius²), stores the result in ST(1), and pops the
stack. The final result is in ST(0).
• FST result: Saves the result from ST(0) into memory.

Usage Notes
• The 8087 uses an 80bit-register stack (ST(0) to ST(7)).
• Floating-point values are stored in IEEE 754 format (real4 = 32-bit, real8 = 64-bit).
• Use FSTSW + SAHF to transfer 8087 status flags to the CPU for conditional branching.
• This example demonstrates basic 8087 usage for floating-point computation. For advanced operations
(e.g., trigonometry), use instructions like FSIN or FPTAN.
Emu8086 is primarily an emulator for the Intel 8086/8088 CPU and does not natively support the i8087
math coprocessor instructions. Here's a breakdown:

Hardware Emulation Limitation:

The i8087 is a separate floating-point coprocessor that works alongside the 8086. Emu8086 focuses on
the CPU core and does not emulate the i8087 hardware. Attempting to execute i8087 instructions (e.g.,
FADD, FMUL, FSQRT) will result in invalid opcode exceptions because the emulator does not recognize
these commands.

Assembler Support:
While Emu8086’s assembler may parse some i8087 instructions (depending on syntax), they cannot
execute properly. The emulator lacks the necessary logic to simulate floating-point operations or the
i8087’s internal stack/registers.

Workarounds:
Software-Based Floating-Point: Use software libraries (e.g., integer-based or custom routines) to handle
floating-point calculations.
Alternative Emulators: Tools like DOSBox, Bochs, or NASM with QEMU (configured to emulate an FPU)
support i8087 instructions.
Modern x86 Environments: Modern CPUs and emulators (e.g., VirtualBox, VMware) typically include FPU
emulation, but these are outside Emu8086’s scope.
Conclusion: Emu8086 cannot execute i8087 instructions. For FPU functionality, use alternative methods
or emulators that explicitly support the i8087.
 Thank you

3/31/2025 By Eng A4K 32