Chapter 6

6.1 IO interface

• Introduction
• I/O ports and devices
• Programmable peripheral Interfaces (PPI)
 Introduction
I/O Problems
✓ Wide variety of peripherals
✓ Delivering different amounts of data
• At different speeds
• In different formats
✓ All slower than CPU and RAM
✓ Need I/O modules
I/O Modules
✓ Interface to CPU and Memory
✓ Interface to one or more peripherals
External Devices
Human readable
Screen, printer, keyboard
Machine readable
Monitoring and control
Communication
Modem
Network Interface Card (NIC)

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I/O module functions
• Control & Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection

I/O steps
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
I/O Techniques
• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

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 I/O ports
Two types

• Memory mapped I/O

• Isolated I/O

Memory mapped I/O

• Uses instructions that transfers data between microprocessor & memory
• Treated as memory location in the memory map
• Portion of memory is used as I/O map
• 8086 uses M/ (𝑰𝑶) ̅control signal to select b/n memory and I/O devices
• I/O locations are isolated from memory system in a separate address space.
• User can expand the memory to its full size
• Data transferred between I/O and microprocessor must be access by IN/OUT
instructions
• In PC, isolated I/O ports are used for controlling peripheral device
• 8-bit port address access devices located on system board.
• 16-bit port access serial, parallel ports, video & disk drive

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 I/O ports
I/O Addressing
Two addressing modes
1) Immediate port address
- Can only be 1 byte immediate address
- Can only address ports 00h through ffh
2) Port address present in DX
- Can address all ports 0000h through ffffh
- Can only use DX for port addresses
- Can only use AL,AX for port data
I/O Instructions
Two I/O instructions:
• Transfers information to an I/O device (OUT)
• Read information from an I/O device (IN)
o When data are transferred using IN/OUT instruction, I/O address (port number) appears on the
address bus
o 8-bit fixed port appears on address bus A7-A0 with A15-A8 bits equal to 00000000b
o 16-bit variable port appears on address connection A15-A0

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I/O Instructions…e.g.

IN AL, p8 ;Read from port p8 to AL

IN AX, p8 ;Read from port p8 to AX
IN AL, DX ;Read from port addressed by DX to AL
IN AX, DX ;Read from port addressed by DX to AX
OUT p8 , AL ;Output from AL into port p8
OUT p8 , AX ;Output from AX into port p8
OUT DX, AL ;Output from AL into port addressed by DX
I/O Port

Parallel I/O Serial I/O

A simple shift register can be used to change a serial Port to parallel or vice versa

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Parallel I/O Input
Basic input device has a set of tri-state buffers.
When microprocessors executes an IN instruction, I/O port is decoded to generate logic 0 on
SEL

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Parallel I/O Output
Basic output interface receives data from microprocessor and must hold it.
Flip-flop latches (buffers) are built into these devices

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e.g. Blinking an LED at an O/P port with a delay loop

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 MOV DX, 8000h ;initialize address of port 0
MOV AL, 00h ;load data with bit 7 as logic 0
ON_OFF:
OUT DX,AL ;turned on

MOV CX,FFFFh ;load delay count of FFFFh

HERE:
LOOP HERE
XOR AL,80h ;complement bit 7
JMP ON_OFF

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PPI (Programmable peripheral interfaces)
Several developed by Intel to ease design burden provide a complete I/O interface on a
single chip
Examples of common I/O interface chips:
• 8255A Programmable Peripheral Interface (PPI)
• 8259 Programmable Interrupt Controller (PIC)
• 8253/4 Programmable Interval Timer (PIT)
• 8237 Programmable DMA Controller
• IBM PC/XT had these chips on system board
• Modern PCs have functionality included in system chipset

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 i8255A-ic
Download the datasheet for 8255 and refer to
- The internal structure
- How to interface with the microprocessor
- how to control data transfer between the ports and the microprocessor
- Details are available with examples on the 3rd manual
• It can be programmed to transfer data under various conditions.
• It has 24 I/O pins.
• The function of 8255A classified acc to two modes.
1. BSR mode
2. I/O mode
Control word
BSR mode
Mode 0
Mode 1
Mode 2

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Pin diagram of
8255A

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 BLOCK
DIAGRAM
OF 8255A

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 CONTROL WPRD FORMAT
• Control word is some times called command word
• It is stored in control register
• It is 8 bit length
• It configure the interface IC to suitable setting

• To know in which mode the interface is working we need to know the value of Control
word. Control word is a part of control register in 8255 which specify an I/O function for
each port. This is format of control word 8255.
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If the most significant bit of control word or D7 is 1 then 8255 works in I/O mode else, if it’s
value is 0 it works in BSR mode.
1) IO mode -D7=1
I/O Mode – When MSB of the control register is one(1), 8255 works in Input-Output mode.it
is further divided into three categories.
• Mode 0 –D6D5 =00 Simple or basic I/O mode:
Port A, B and C can work either as input function or as output function. The outputs are latched
but the inputs are not latched. It has interrupt handling capability.
Mode 1 –D6D5=01
Handshake or strobbed I/O:
In this either port A or B can work and port C bits are used to provide handshaking. The outputs
as well as inputs are latched. It has interrupt handling capability. Before actual data transfer
there is transmission of signal to match speed of CPU and printer.
Example: When CPU wants to send data to slow peripheral device like printer, it will send
handshaking signal to printer to tell whether it is ready or not to transfer the data. When printer
will be ready it will send one acknowledgement to CPU then there will be transfer of data
through data bus.

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Strobe pulse:
A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to
occur.
Handshaking pulse:
A control signal is accompanied with each data being transmitted to indicate the presence
of data in the bus.
The receiving unit responds with another control signal to acknowledge receipt of the data.
This type of agreement b/n two independent unit called handshaking.
Busy pulse:
If previous task of data transfer is not accomplished this signal remains active to notify the
other device it is busy

Other
Device

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Mode 2 – Bidirectional I/O:
In this mode only port A will work, port B can either is in mode 0 or 1 and port C bits are used
as handshake signal. The outputs as well as inputs are latched. It has interrupt handling
capability. The remaining are port group definition
✓ D4 defines i/0 of protA
✓ D3 defines prot C(upper)
✓ D2 defines mode 0/1 of protB
✓ D1 defines i/o of portB
✓ D0 defines portC(lower)
Control Register is as follows:

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Example:

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2) Bit set reset (BSR) mode –
This mode is used to set or reset the bits of port C only, and selected when the most significant
bit (D7) in the control register is 0. Control Register is as follows:

This mode affects only one bit of port C at a time because, as user set the bit, it remains set
until and unless user changes it. User needs to load the bit pattern in control register to
change the bit.

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 Interfacing i8086
▪ Types of interfacing:
▪ IO mapped IO configuration
▪ Memory mapped IO configuration

▪ Interfacing with i8255

▪ 8255 Internal Architecture
▪ Working Modes Of 8255
▪ Control Word Of 8255 PPI
▪ BSR Mode Control Word
▪ Operation Of Different 8255 Modes
▪ Interfacing Examples Using 8255 PPI
8255 Interfacing with 8086 in I/O Mapped I/O Mode:

• The 8086 has four special instructions IN, INS, OUT, and OUTS to transfer data through
the input/output ports in I/O mapped I/O system.
• M/IO signal is always low when 8086 is executing these instructions. So M/IO signal is
used to generate separate addresses for, memory and input/output.
• Only 256 (28 ) I/O addresses can be generated when direct addressing method is used.
• By using indirect address method this range can be extended upto 65536 (216 ) addresses.

• Fig. on next slide shows the 8255 Interfacing with 8086 in I/O mapped I/O technique.
Here, RD and WR signals are activated when M/IO signal is low, indicating I/O bus cycle.
• Only lower data bus (D0 — D7) is used as 8255 is 8-bit device. Reset out signal from clock
generator is connected to the Reset signal of the 8255.
• In case of interrupt driven I/O INTR signal (PC3 or PC0) from 8255 is connected to INTR
input of 8088.

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IO mapped IO configuration

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24
8255 Interfacing with 8086 in Memory Mapped I/O:

• In this type of I/O interfacing, the 8086 uses 20 address lines to identify an I/O device; an
I/O device is connected as if it is a memory register.
• The 8086 uses same control signals and instructions to access I/O as those of memory.
• Fig. on thee next slide shows the 8255 Interfacing with 8086 in memory mapped I/O
technique.
• Here RD and WR signals are activated when M/IO signal is high, indicating memory bus
cycle. Address lines A0 – A2 are used by 8255 for internal decoding.
• To get absolute address, all remaining address lines (A3 – A19) are used to decode the
address for 8255. Other signal connections are same as in I/O mapped I/O.

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Memory mapped IO configuration

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27
EXERCISE

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Summery of control word definition

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Summery of control word definition

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Example:-
Interface an 8255 chip with 8086 to work as an I/O port. Initialize port A as output port, Port
B as I/P port and Port C as O/P port. Port A address should be 0740H. Write an ALP to sense
switch positions SW0–SW7 connected at port B. The sensed pattern is to be displayed on
port A, to which 8 LED's are connected, while port C lower displays number of on switches
out of the total eight switches .

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 PROGRAMMING FOR INTERFACING
8255
• Port address definition
• Control word address definition
• Defining control word(input-output port definition and mode
• Loading control word to control register
• Statements to receive input
• Statement to casting output
To communicate with peripherals through 8255 three steps are necessary:
• Determine the addresses of Port A, B, C and Control register according to Chip Select
Logic and the Address lines A0 and A1.
• Write a control word in control register.
• Write I/O instructions to communicate with peripherals through port A, B, C.

Programming steps
1. Define the address of each port and control register
2. Write a statement to load the control word
3. Then the body of your program will follow accordingly you will use the port
connection statement with DX then the statement with instruction IN or OUT to get
to the input-output register AL

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DATA SEGMENT
PORTA EQU 0740H
PORTB EQU 0742H
PORTC EQU 0744H ;PORT ADDRESS
COMD EQU 0746H ;COMMAND WORD
ENDS

CODE SEGMENT
MOV DX, COMD ;connecting to the control register
MOV AL, 82H ;loading the control word AL
OUT DX, AL ;loading AL value to the control register through DX

MOV AL, 11000000B ; loading to the io-register

MOV DX, PORTA ;connecting the port
OUT DX,AL ;oupting the value in AL to portA

START:
MOV DX, PORTB
IN AL, DX ;receiving the input from portB
;so you can put any logic any where but according to the steps
CODE ENDS
END
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37
38
Exercise 1
a) Determine control words when the ports of Intel 8255 are defined as follows:
Port A as an input port. Mode of the Port A is Mode 0.
Port B as an input port. Mode of the Port B is Mode 0.
Port C upper and C lower are input ports.
b) Determine the control word for the following configuration of the ports of Intel 8255 for
Mode 1 operation:
Port A is used as input and operation mode of Port A is Mode 1.
Port B can be used as output and operates in Mode 1.
PC6 and PC7 act as input.
c) Write down the port addresses of the three counters and the control word register. The
Chip Select signal is derived on the basis of A7 - A4 =1111 and A3 – A2 = 00. Also, draw the
interfacing diagram of Programmable Interval Timer 8254 with 8086. Assume suitable
address mapping.

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EXERCISE 2
Interface an 8255 chip with 8086 microprocessor to work as an IO ports which is shown below in. Initialize
port B as input port connected to the push buttons, port A as output port connected to 7 seg display. So
that the ASM code should make a process to display decimal number when a corresponding pushbutton is
pressed. Control word register address should be 00FEH,PPI A0 is connected to 8086 microprocessor A1,
PPI A1 is connected to 8086 microprocessor A2

7-seg DISPLAY
U3
AD[0..15] AD0 34 4
D0 PA0
AD1 33 3
U2 AD2 32
D1 PA1
2
AD0 D2 PA2
3 2 AD3 31 1
D0 Q0 D3 PA3
AD1 4 5 AD4 30 40
D1 Q1 D4 PA4
AD2 7 6 AD5 29 39
D2 Q2 D5 PA5
AD3 8 9 AD6 28 38
D3 Q3 D6 PA6
AD4 13 12 AD7
27 37
D4 Q4 D7 PA7
AD5 14 15
D5 Q5
AD6 17 16 5 18
D6 Q6 RD PB0
AD[0..15]

AD7 18 19 36 19
D7 Q7 WR PB1
9 20
A0 PB2
1 8 21
OE A1 PB3
11 35 22
LE RESET PB4
23
PB5
74HC373 6 24
U1 CS PB6
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21 PB7
RESET AD[0..15]
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READY A[16..19] 14
24 PC0
INTA/QS1 15
18 25 PC1
INTR ALE/QS0 16
31 34 PC2
HOLD/GT1 BHE 17
30 27 PC3
HLDA/GT0 DT/R/S1 13
23 26 PC4
TEST DEN/S2 12
17 32 PC5
NMI RD 11
33 29 PC6
MN/MX WR/LOCK 10
19 28 PC7
CLK M/IO/S0
8086
8255A
PUSH BUTTONS
i8086 microporcessor 8255A PPI
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 8237 DMA Controller
• DMA is an input output technique used for high speed data transfer
• Data transfer between system memory and floppy disk
• The direct memory access DMA interface of the 8086 minimum mode
consist of the HOLD and HLDA signals.
• When an external device wants to take control of the system bus, it signals
to the 8086 by switching HOLD to the logic 1 level. At the completion of the
current bus cycle, the 8086 enters the hold state.
• The 8237 works in two modes i.e., master and slave modes.
• In slave mode, the 8237 functions as an input/output device. In this mode the system
buses arc controlled by microprocessor and hence the microprocessor is connected to
the system bus.
• In master mode 8237 becomes the bus master and hence the microprocessor is isolated
from the system bus. This isolation is done by AEN signal.
• In minimum configuration, 8237 DMA controller is used to transfer the data. The
peripheral chips are interface as normal 10 ports. Figure shows the interfacing of DMA
controller with 8086.
• In minimum mode the HOLD and HLDA signals are used to bus arbitration and in
maximum mode configuration RQ_0/GT_0; and RQ_1/GT_1.
• The 8237 outputs only 16-bit memory address but not the complete 20-bit address of
8086. To store the remaining four address hits A_16—A_19 a separate page latch is
required.
• The 8237 is not compatible with 8086 in its maximum mode configuration. This is
because RQ/GT is not compatible with HRQ and HLDA of 8237.
• So if 8086 is to be interfaced with DMA controller, then 8089 10 processor is required.
• The 8089 interfaces to the 8086's local multiplexed buses. It shares the bus buffers and
system controller of the host system. It is compatible with the RQ/GT signals of 8086
and outputs the complete 20-bit address.
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DMA interfacing Block diagram

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Different data transfer modes of 8237 DMA controller:

The 8237 is in the idle cycle if there is no pending request or the 8237 is waiting for a request
from one of the DMA channels. Once a channel requests a DMA service, the 8237 sends the
HOLD request to the CPU using its HRQ pin. If the CPU acknowledges the hold request on
HLDA, the 8237 enters an active cycle. In the active cycle, the actual data transfer takes place in
one of the following transfer modes as is programmed.

1. Single Transfer Mode: In this mode, the device transfers only one byte per request. The
word count is decremented and the address is decremented or incremented (depending on
programming) after each such transfer. The Terminal Count (TC) state is reached when the
count becomes zero. For each transfer the DREQ must be active until the DACK is activated,
in order to get recognized. After TC the bus will be relinquished for the CPU. For a new DREQ
to 8237 it will again activate the HRQ signal to the CPU and the HLDA signal from the CPU
will push the 8237 again into the single transfer mode. This mode is also called as 'cycle
stealing'.
2. Block Transfer Mode: In this mode, the 8237 is activated by DREQ to continue the transfer
until a TC is reached, i.e. a block of data is transferred. The transfer cycle may be terminated
due to EOP (either internal or external) which forces Terminal Count (TC). The DREO needs
to be activated only till the DACK signal is activated by the DMA controller. Auto-
initialization may be programmed in this mode.
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3. Demand Transfer Mode: In this mode, the device continues transfers until a TC is reached
or an external EOP is detected or the DREQ signal goes inactive. Thus a transfer may
exhaust the capacity of data transfer of an I/O device. After the I/O device is able to catch
up the service may be re-established activating the DREQ signal again. Only the EOP
generated by TC or external EOP can cause the auto-initialization, and only if it is
programmed for.
4. Cascade Mode: In this mode, more than one 8237 can be connected together to provide
more than four DMA channels. The HRQ and HLDA signals from additional 8237s are
connected with DREQ and DACK pins of a channel of the host 8237 respectively. The
priorities of the DMA requests may be preserved at each level. The first device is only used
for prioritizing the additional devices (slave 8237s), and it does not generate any address
or control signal of its own. The host 8237 responds to DREQ generated by slaves and
generates the DACK and the HRQ signals to coordinate all the slaves. All other outputs of
the host 8237 are disabled.
5. Memory to memory Transfer: To perform the transfer of a block of data from one set of
memory address to another one, this transfer mode is used. Programming the
corresponding mode bit in the command word, sets the channel 0 and I to operate as
source and destination channels, respectively. The transfer is initialized by setting the
DREQ0 using software commands. The 8237 sends HRQ (Hold Request) signal to the CPU
as usual and when the HLDA signal is activated by the CPU. the device starts operating in
block transfer mode to read the data from memory. 51
• The channel 0 current address register acts as a source pointer.
• The byte read from the memory is stored in an internal temporary register of 8237.
• The channel 1 current address register acts as a destination pointer to write the data from
the temporary register to the destination memory location.
• The pointers are automatically incremented or decremented, depending upon the
programming.
• The channel 1 word count register is used as a counter and is decremented after each
transfer.
• When it reaches zero, a TC is generated, causing EOP to terminate the service.
• The 8237 also responds to external EOP signals to terminate the service.
• This feature may be used to scan a block of data for a byte. When a match is found the
process may be terminated using the external EOP.
• Under all these transfer modes, the 8237 carries out three basic transfers namely, write
transfer, read transfer and verify transfer.
• In write transfer, the 8237 reads from an I/O device and writes to memory under the control
of IOR and MEMW signals.
• In read transfer, the 8237 reads from memory and writes to an I/O device by activating the
MEMR and IOW signals.
• In verify transfers, the 8237 works in the same way as the read or write transfer but does
not generate any control signal.
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