Digital Design

Chapter 2:
Combinational Logic Design

Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and
Verilog, 2nd Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2010.
http://www.ddvahid.com

Copyright © 2010 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
Digital
with animations) may Design 2e
not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
Copyright © 2010 1
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Frank Vahid
may obtain PowerPoint source or obtain special use permissions from Wiley – see http://www.ddvahid.com for information.
 2.1

Introduction
• Let’s learn to design digital circuits, starting with a
simple form of circuit:
– Combinational circuit
• Outputs depend solely on the present combination of the circuit
inputs’ values
• Vs. sequential circuit: Has “memory” that impacts outputs too
b=0 Digital F=0
System
b=0 Digital F=0
System
b=1 Digital F=1
System
b=1 Digital F=1
System b=0 Digital F=1
System
if b=0, then F=0
if b=1, then F=1 Cannot determine value of
(a) a (b) F solely from present
a
input value
Digital Design 2e
Copyright © 2010 2
Frank Vahid
 Switches
• Electronic switches are the basis of control
input
binary digital circuits “off”
• A switch has three parts
– Source input, and output source output
a
input
• Current tries to flow from source control
input to output input
“on”
– Control input
• Voltage controls whether that source output
input
current can flow
(b)
• The amazing shrinking switch
– 1930s: Relays
– 1940s: Vacuum tubes
– 1950s: Discrete transistor
discrete
– 1960s: Integrated circuits (ICs) transistor
IC
relay
• Initially just a few transistors on IC vacuum tube

• Then tens, hundreds, thousands... quarter

Digital Design 2e (to see the relative size)
Copyright © 2010 3
Frank Vahid
 2.3

The CMOS Transistor

• CMOS transistor
– Basic switch in modern ICs
a
A positive ...attracts electrons here,
voltage here... turning the channel between
the source and drain into nMOS
a conductor 1 0
gate
gate
oxide
IC package
source drain conducts does not
conduct

pMOS
1 0
IC gate
(a )

Silicon -- not quite a conductor or insulator: does not conducts

conduct
Semiconductor
Digital Design 2e
Copyright © 2010 4
Frank Vahid
 Planar MOS

Digital Design 2e
Copyright © 2010 5
Frank Vahid
 FinFET (Tri-Gate) transistors

Digital Design 2e
Copyright © 2010 6
Frank Vahid
 Moore’s Law
• IC capacity doubling about every 18 months for
several decades
– Known as “Moore’s Law” after Gordon Moore, co-
founder of Intel
• Predicted in 1965 predicted that components per IC
would double roughly every year or so
– Scaling offers many advantages An Intel Pentium processor IC
having millions of transistors
• More transistors per unit area.
• Less chip area used
• Lower power*
– Today’s ICs hold billions of transistors
• The first Pentium processor (early 1990s) needed
only 3 million
– Manufacturing classified by “Process Technology
Node”
• Refers to the the “recipe” used.
An Intel “Coffee Lake” Core i7 IC
• Traditionally uses minimum half pitch as the process
having billions of transistors
name, e.g., 22nm, 14nm, etc. (no longer accurate)

Digital Design 2e
Copyright © 2010 7
Frank Vahid
 Semiconductor Foundry

Intel Ronler Acres Campus at Hillsboro, OR

Digital Design 2e
Copyright © 2010 8
Frank Vahid
 Semiconductor Foundry

TSMC Fab15, Taiwan

Digital Design 2e
Copyright © 2010 9
Frank Vahid
 Boolean Logic Gates 2.4

Building Blocks for Digital Circuits

(Because Switches are Hard to Work With)

• “Logic gates” are better digital circuit building blocks than switches (transistors)
– Why?...
Abstraction reduces complexity!
Digital Design 2e
Copyright © 2010 10
Frank Vahid
 NOT gate

1
1

x F
0 1 0 1 1
x F x F
1 0 0

1
0 a a

x 0
0
(a)
(b)
1 When the input is 0 When the input is 1
F
0

time
Digital Design 2e
Copyright © 2010 11
Frank Vahid
 OR gate

0 0
x y F
0 0 0 1 0
y y
0 1 1
1 0 1 0 0
x 1 x 0
1 1 1
F F
1 0 1 y 0 0 y
x x x
a
0 a

1
y
0 1 1
1 (a) (b)
F
0 When an input is 1 When both inputs are 0
time
Digital Design 2e
Copyright © 2010 12
Frank Vahid
 AND gate

0 0
x y F
0 0 0
1 1 0 1
0 1 0 x y x y
1 0 0
F F
1 1 1
y 1 1 y 1 0
1
x 0
0 1 x
x a a
1
y
1
0 1
(b)
1 (a)
F
0
When both inputs are 1 When an input is 0
time
Digital Design 2e
Copyright © 2010 13
Frank Vahid
 IC Design Process

Design
Description

k Belt Warn

p w

1 BeltWarn

0
s

Digital Design 2e 1
Copyright © 2010 14
Frank Vahid
Boolean Algebra and its Relation to Digital Circuits
• To understand the benefits of “logic gates” vs. switches,
we should first understand Boolean algebra
• “Traditional” algebra
– Variables represent real numbers (x, y)
– Operators operate on variables, return real numbers (2.5*x + y - 3)
• Boolean Algebra
– Variables represent 0 or 1 only
a b AND
– Operators return 0 or 1 only 0 0 0 a

0 1 0
– Basic operators 1 0 0
1 1 1 a b OR
• AND: a AND b returns 1 only when both a=1 and b=1 0 0 0
0 1 1
• OR: a OR b returns 1 if either (or both) a=1 or b=1 1 0 1

• NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1) a

0
NOT
1
1 1 1

1 0

Digital Design 2e
Copyright © 2010 15
Frank Vahid
Boolean Algebra and its Relation to Digital Circuits
• Developed mid-1800’s by George Boole to formalize human thought
– Ex: “I’ll go to lunch if Mary goes OR John goes, AND Sally does not go.”
• Let F represent my going to lunch (1 means I go, 0 I don’t go)
• Likewise, m for Mary going, j for John, and s for Sally a b AND
0 0 0
• Then F = (m OR j) AND NOT(s) 0 1 0
1 0 0
– Nice features 1 1 1
• Formally evaluate
a b OR
– m=1, j=0, s=1 --> F = (1 OR 0) AND NOT(1) = 1 AND 0 = 0
0 0 0
• Formally transform 0 1 1
1 0 1
– F = (m and NOT(s)) OR (j and NOT(s))
1 1 1
» Looks different, but same function
» We’ll show transformation techniques soon a NOT
0 1
• Formally prove 1 0
– Prove that if Sally goes to lunch (s=1), then I don’t go (F=0)
– F = (m OR j) AND NOT(1) = (m OR j) AND 0 = 0

Digital Design 2e
Copyright © 2010 16
Frank Vahid
 Evaluating Boolean Equations
a
• Evaluate the Boolean equation F = (a AND b) OR (c
AND d) for the given values of variables a, b, c, and d:
– Q1: a=1, b=1, c=1, d=0.
a b AND
• Answer: F = (1 AND 1) OR (1 AND 0) = 1 OR 0 = 1. 0 0 0
0 1 0
– Q2: a=0, b=1, c=0, d=1. 1 0 0
1 1 1
• Answer: F = (0 AND 1) OR (0 AND 1) = 0 OR 0 = 0.
– Q3: a=1, b=1, c=1, d=1. a
0
b
0
OR
0
• Answer: F = (1 AND 1) OR (1 AND 1) = 1 OR 1 = 1. 0
1
1
0
1
1
1 1 1

a NOT
0 1
1 0

Digital Design 2e
Copyright © 2010 17
Frank Vahid
 Converting to Boolean Equations
a
• Q1. A fire sprinkler system should spray water if high heat
is sensed and the system is set to enabled.
– Answer: Let Boolean variable h represent “high heat is sensed,” e
represent “enabled,” and F represent “spraying water.” Then an
equation is: F = h AND e.
• Q2. A car alarm should sound if the alarm is enabled, and
either the car is shaken or the door is opened.
– Answer: Let a represent “alarm is enabled,” s represent “car is
shaken,” d represent “door is opened,” and F represent “alarm
sounds.” Then an equation is: F = a AND (s OR d).
– (a) Alternatively, assuming that our door sensor d represents “door
is closed” instead of open (meaning d=1 when the door is closed, 0
when open), we obtain the following equation: F = a AND (s OR
NOT(d)).
Digital Design 2e
Copyright © 2010 18
Frank Vahid
 Relating Boolean Algebra to Digital Design
NOT OR AND
Boolean Boole’s intent: formalize x x
algebra human thought Symbol x F F F
y y
(mid-1800s)
x F x y F x y F
Switches For telephone Truth table 0 1 0 0 0 0 0 0
1 0 0 1 1 0 1 0
(1930s) switching and other
electronic uses 1 0 1 1 0 0
1 1 1 1 1 1

Showed application 1 0 0

Shannon (1938) of Boolean algebra y

x y
to design of switch-
based circuits Transistor
x F
x F
circuit F y

x y
Digital design x
0
1 1
• Implement Boolean operators using
transistors 1.8 V Next slides show how
“1”
these circuits work.
– Call those implementations logic gates. 1.2 V Note: The above OR/AND
– Lets us build circuits by doing math - 0.6 V implementations are
inefficient; we’ll show
“0”
- powerful concept 0V why, and show better
Digital Design 2e
ones, later.
1 and 0 each actually corresponds to
Copyright © 2010
a voltage range 19
Frank Vahid
 Building Circuits Using Gates

• Recall the motion-in-dark example

– Turn on lamp (F=1) when motion sensed (a=1) and no light (b=0)
– F = a AND NOT(b)
– Build using logic gates, AND and NOT, as shown
– We just built our first digital circuit!

Digital Design 2e
Copyright © 2010 20
Frank Vahid
 Example: Converting a Boolean Equation to a
Circuit of Logic Gates
Start from the output, work back towards the inputs

• Q: Convert the following equation to logic gates:

F = a AND NOT( b OR NOT(c) )

a
b F
c

Digital Design 2e
Copyright © 2010 21
Frank Vahid
 More examples

F = (a AND NOT(b)) OR (b AND NOT(c))

2 1 3
F = a AND (s OR d)
1 2 a
a b
s F F
d
c
a
(a) a

(b)

Start from the output, work back towards the inputs

Digital Design 2e
Copyright © 2010 22
Frank Vahid
 Using gates with more than 2 inputs

F = a AND b AND c

a
a
b b F
F c
c
(a) (b)

Can think of as AND(a,b,c)

Digital Design 2e
Copyright © 2010 23
Frank Vahid
Example: Seat Belt Warning Light
System
• Design circuit for warning light
• Sensors
– s=1: seat belt fastened
– k=1: key inserted
w = NOT(s) AND k
BeltWarn
• Capture Boolean equation
k w
– seat belt not fastened, and key
inserted
a

• Convert equation to circuit s

Seatbelt
• Timing diagram illustrates circuit Inputs
behavior k
1
– We set inputs to any values 0
1
– Output set according to circuit s a
0
Outputs
1
w
0
Digital Design 2e
Copyright © 2010 time 24
Frank Vahid
More examples: Seat belt warning light extensions
• Only illuminate warning light if
k Belt W a rn

person is in the seat (p=1), p w

and seat belt not fastened a

and key inserted

s
• w = p AND NOT(s) AND k

• Given t=1 for 5 seconds after k BeltWarn

key inserted. Turn on warning p

w
light when t=1 (to check that s
a

warning lights are working)

t
• w = (p AND NOT(s) AND k) OR t
Digital Design 2e
Copyright © 2010 26
Frank Vahid
Some Gate-Based Circuit Drawing Conventions
no yes
x
F
y

no yes
a

ok
a

not ok

Digital Design 2e
Copyright © 2010 27
Frank Vahid
 2.5

Boolean Algebra
• By defining logic gates based on Boolean algebra, we can
use algebraic methods to manipulate circuits
• Notation: Writing a AND b, a OR b, NOT(a) is cumbersome
– Use symbols: a * b (or just ab), a + b, and a’
• Original: w = (p AND NOT(s) AND k) OR t
• New: w = ps’k + t
– Spoken as “w equals p and s prime and k, or t”
– Or just “w equals p s prime k, or t”
– s’ known as “complement of s”
• While symbols come from regular algebra, don’t say “times” or “plus”
– "product" and "sum" are OK and commonly used

Boolean algebra precedence, highest precedence first.

Symbol Name Description
() Parentheses Evaluate expressions nested in parentheses first
’ NOT Evaluate from left to right
Digital Design 2e * AND Evaluate from left to right
Copyright © 2010 28
Frank Vahid + OR Evaluate from left to right
 Boolean Algebra Terminology
• Example equation: F(a,b,c) = a’bc + abc’ + ab + c
• Variable
– Represents a value (0 or 1)
– Three variables: a, b, and c
• Literal
– Appearance of a variable, in true or complemented form
– Nine literals: a’, b, c, a, b, c’, a, b, and c
• Product term
– Product of literals
– Four product terms: a’bc, abc’, ab, c
• Sum-of-products
– Equation written as OR of product terms only
– Above equation is in sum-of-products form. “F = (a+b)c + d” is not.
Digital Design 2e
Copyright © 2010 29
Frank Vahid
 Boolean Algebra Properties
• Commutative Example uses of the properties
– a+b=b+a
– a*b=b*a • Show abc’ equivalent to c’ba.
• Distributive – Use commutative property:
– a * (b + c) = a * b + a * c • a*b*c’ = a*c’*b = c’*a*b = c’*b*a
• Can write as: a(b+c) = ab + ac • Show abc + abc’ = ab.
– a + (b * c) = (a + b) * (a + c) – Use first distributive property
• (This second one is tricky!)
a

• abc + abc’ = ab(c+c’).

• Can write as: a+(bc) = (a+b)(a+c)
• Associative – Complement property
• Replace c+c’ by 1: ab(c+c’) = ab(1).
– (a + b) + c = a + (b + c)
– (a * b) * c = a * (b * c) – Identity property
• ab(1) = ab*1 = ab.
• Identity
– 0+a=a+0=a • Show x + x’z equivalent to x + z.
– 1*a=a*1=a – Second distributive property
• Complement • Replace x+x’z by (x+x’)*(x+z).
– a + a’ = 1 – Complement property
– a * a’ = 0 • Replace (x+x’) by 1,
• To prove, just evaluate all possibilities – Identity property
• replace 1*(x+z) by x+z.
Digital Design 2e
Copyright © 2010 30
Frank Vahid
 Example that Applies Boolean Algebra Properties
• Want automatic door opener
• Can the circuit be simplified?
circuit (e.g., for grocery store)
– Output: f=1 opens door f = hc' + h'pc‘ a

f = c'h + c'h'p (by the commutative property)

– Inputs:
f = c'(h + h'p) (by the first distrib. property)
• p=1: person detected
f = c'((h+h')*(h+p)) (2nd distrib. prop.; tricky one)
• h=1: switch forcing hold open
f = c'((1)*(h + p)) (by the complement property)
• c=1: key forcing closed
f = c'(h+p) (by the identity property)
– Want open door when
• h=1 and c=0, or
• h=0 and p=1 and c=0 a

– Equation: f = hc’ + h’pc’

DoorOpener
DoorOpener c
h Simplified
c f
h f circuit
p p

Digital Design 2e
Copyright © 2010
Simplification of circuits is covered 31
Frank Vahid in Sec. 2.11 / Sec 6.2.
 Boolean Algebra: Additional Properties
• Null elements
– a+1=1
– a*0=0
• Idempotent Law
– a+a=a
– a*a=a
• Involution Law
– (a’)’ = a
• DeMorgan’s Law
– (a + b)’ = a’b’
– (ab)’ = a’ + b’
– Very useful!
• To prove, just evaluate all possibilities
Digital Design 2e
Copyright © 2010 32
Frank Vahid
 Complement of a Function
• Commonly want to find complement (inverse) of function F
– 0 when F is 1; 1 when F is 0
• Use DeMorgan’s Law repeatedly
– Note: DeMorgan’s Law defined for more than two variables, e.g.:
• (a + b + c)' = a'b'c'
• (abc)' = (a' + b' + c')
• Complement of f = w'xy + wx'y'z'
– f ' = (w'xy + wx'y'z')'
– f ' = (w'xy)'(wx'y'z')' (by DeMorgan’s Law)
– f ' = (w+x'+y')(w'+x+y+z) (by DeMorgan’s Law)
• Can then expand into sum-of-products form

Digital Design 2e
Copyright © 2010 33
Frank Vahid
Truth Table Representation of Boolean Functions
• Define value of F for
a b F a b c F a b c d F
0 0 0 0 0 0 0 0 0
each possible 0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
combination of input 1 1 0 1 1 0 0 1 1
1 0 0 0 1 0 0
values (a)
1 0 1 0 1 0 1
– 2-input function: 4 rows 1
1
1
1
0
1
0
0
1
1
1
1
0
1
– 3-input function: 8 rows (b) 1 0 0 0
1 0 0 1
– 4-input function: 16 rows a b c F 1 0 1 0
1 0 1 1
• Q: Use truth table to 0
0
0
0
0
1
0
0 1 1 0 0
define function F(a,b,c) a 0 1 0 0 1
1
1
1
0
1
1
0
0 1 1 0
that is 1 when abc is 5 or 1 0 0 0 1 1 1 1
1 0 1 1 (c)
greater in binary 1 1 0 1
1 1 1 1

Digital Design 2e
Copyright © 2010 34
Frank Vahid
 2.6

Representations of Boolean Functions

English 1: F outputs 1 when a is 0 and b is 0, or when a is 0 and b is 1.
English 2: F outputs 1 when a is 0, regardless of b’s value
(a)
a
a b F
b
0 0 1
Equation 1: F(a,b) = a’b’ + a’b F
0 1 1
Equation 2: F(a,b) = a’
1 0 0
(b) (c)
1 1 0
Circuit 1 a

Truth table
a F (d)
Circuit 2

The function F

• A function can be represented in different ways

– Above shows seven representations of the same functions F(a,b), using
four different methods: English, Equation, Circuit, and Truth Table
Digital Design 2e
Copyright © 2010 36
Frank Vahid
 Converting among Representations
1
• Can convert from any representation
to another Equations Circuits
2
• Common conversions
4 6
– Equation to circuit (we did this earlier)
3 5
– Circuit to equation
• Start at inputs, write expression of Truth tables
each gate output

c c'

h F = c'(h+p)
p
h+p

Digital Design 2e
Copyright © 2010 37
Frank Vahid
 Converting among
1

Equations Circuits

Representations
2
4 6
3 5
• More common conversions Truth tables
– Truth table to equation (which we can
then convert to circuit) Inputs Outputs Term
• Easy–just OR each input term that a b F F = sum of
should output 1 0 0 1 a’b’
– Equation to truth table 0 1 1 a’b
1 0 0
• Easy—just evaluate equation for each
1 1 0
input combination (row)
• Creating intermediate columns helps F = a’b’ + a’b

Q: Convert to equation
a b c F
0 0 0 0
0 0 1 0
Q: Convert to truth table: F = a’b’ + a’b 0 1 0 0
Inputs Output 0 1 1 0
a b a' b' a' b F 1 0 0 0
a
0 0 1 0 1 1 0 1 1 ab’c
0 1 0 1 1 1 1 0 1 abc’
1 0 0 0 0 1 1 1 1 abc a
Digital Design 2e 1 1 0 0 0
Copyright © 2010
Frank Vahid
F = ab’c + abc’ + abc 38
 Example: Converting from Circuit to Truth Table
• First convert to circuit to equation, then equation to table

a ab (ab)'
b

c' F
c (ab)'c'

Inputs Outputs
a b c ab (ab)' c' F
0 0 0 0 1 1 1
0 0 1 0 1 0 0
0 1 0 0 1 1 1
0 1 1 0 1 0 0
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 1 0 1 0
Digital Design 2e 1 1 1 1 0 0 0
Copyright © 2010 40
Frank Vahid
 Comparing functions: Truth Table
• How can we determine if two f = c’hp + c’hp’ + c’h’
functions are the same? f = c’h(p + p’) + c’h’p
– Recall automatic door example
f = c’h(1) + c’h’p
• Same as f = hc’ + h’pc’?
• Used algebraic methods f = c’h + c’h’p
• But if we failed, does that prove (what if we stopped here?)
not equal? No.
f = hc’ + h’pc’
• Solution: Convert to truth tables
– Only ONE truth table
Q: Determine if F=ab+a’ is same
representation of a given
function as F=a’b’+a’b+ab, by converting
function
each to truth table first
• Standard representation—for
given function, only one version F = ab + a' F = a’b’ +
a’b + ab
in standard form exists
a b F a b F
0 0 1 0 0 1 a

0 1 1 0 1 1
1 0 0 1 0 0
Digital Design 2e 1 1 1 1 1 1
Copyright © 2010 41
Frank Vahid
 Canonical Form – Sum of Minterms
• Truth tables too big for numerous inputs
• Use standard form of equation instead
– Known as canonical form
– Regular algebra: group terms of polynomial by power
• ax2 + bx + c (3x2 + 4x + 2x2 + 3 + 1 --> 5x2 + 4x + 4)
– Boolean algebra: create sum of minterms
• Minterm: product term with every function literal appearing exactly
once, in true or complemented form
• Just multiply-out equation until sum of product terms
• Then expand each term until all terms are minterms
Q: Determine if F(a,b)=ab+a’ is equivalent to F(a,b)=a’b’+a’b+ab, by
converting first equation to canonical form (second already is)

F = ab+a’ (already sum of products)

a F = ab + a’(b+b’) (expanding term)
F = ab + a’b + a’b’ (Equivalent – same three terms as other equation)
Digital Design 2e
Copyright © 2010 42
Frank Vahid
 Compact Sum of Minterms Representation
• List each minterm as a number
• Number determined from the binary representation of its
variables’ values
– a'bcde corresponds to 01111, or 15
– abcde' corresponds to 11110, or 30
– abcde corresponds to 11111, or 31
• Thus, H = a'bcde + abcde' + abcde can be written as:
– H = ∑m(15,30,31)
– "H is the sum of minterms 15, 30, and 31"

Digital Design 2e
Copyright © 2010 43
Frank Vahid
 Sum of Minterms Example
Convert into Sum of Minterms compact form
F(a,b,c) = (ab + a’)c + b

Step 1: Convert into Sum of Products form (distribute c)

F = abc + a’c + b

Step 2: Convert into Sum of Minterms form (a’c, b are not minterms)
F = abc + a’c (b + b’) + b
F = abc + a’bc + a’b’c + b
F = abc + a’bc + a’b’c + b (a + a’) (c + c’)
F = abc + a’bc + a’b’c + abc + abc’ + a’bc + a’bc’

Step 3: Encode each minterm in binary (we removed repeated instances abc, a’bc)
F = abc + a’bc + a’b’c + abc’ + a’bc’
Binary: 111 011 001 110 010
Decimal: 7 3 1 6 2
Digital Design 2e
Copyright © 2010
Frank Vahid
F = ∑m(7,3,1,6,2) 44
 2.7

Combinational Logic Design Process

Step Description
Step 1: Create a truth table or equations, whichever is
Capture the
Capture most natural for the given problem, to describe
function
behavior the desired behavior of each output of the
combinational logic.

This substep is only necessary if you captured the

2A: Create function using a truth table instead of equations. Create
Step 2: equations an equation for each output by ORing all the minterms
Convert for that output. Simplify the equations if desired.
to circuit 2B: Implement For each output, create a circuit corresponding
as a gate- to the output’s equation. (Sharing gates among
based circuit multiple outputs is OK optionally.)

Digital Design 2e
Copyright © 2010 45
Frank Vahid
 Example: Number of 1s Counter
• Problem: Output in binary on two
outputs yz the # of 1s on three inputs
• 010  01
• 101  10
• 000  00
a
– Step 1: Capture the function
• Truth table or equation?
– Truth table is straightforward
– Step 2a: Create equations
• y = a’bc + ab’c + abc’ + abc
• z = a’b’c + a’bc’ + ab’c’ + abc a
• Optional: Let's simplify y: b
c
– y = a'bc + ab'c + ab(c' + c) = a'bc + ab'c + ab a
a
– Step 2b: Implement as a gate-based a
b
c
circuit b
c
z
a
b
a y c
b
c
a
b
Digital Design 2e
a c
Copyright © 2010
b 47
Frank Vahid
 Simplifying Notations
• Used in previous circuit

a a a a
b b b b
c c c c

a a
b'
b c
(a) (b) a

List inputs multiple times Draw inversion bubble

 Less wiring in drawing rather than inverter. Or list
input as complemented.

Digital Design 2e
Copyright © 2010 48
Frank Vahid
 Multiple-Output Circuits
• Many circuits have more than one output
• Can give each a separate circuit, or can share gates
• Ex: F = ab + c’, G = ab + bc

a
a
b
b
F
F
c
c
a
a

G
G

(b)
(a)

Option 1: Separate circuits Option 2: Shared gates

Digital Design 2e
Copyright © 2010 51
Frank Vahid
 2.9

Decoders
• Decoder: Popular combinational
logic building block, in addition to
logic gates d0 1 d0 0 d0 0 d0 0
0 i0 d1 0 1 i0 d1 1 0 i0 d1 0 1 i0 d1 0
– Converts input binary number to
0 i1 d2 0 0 i1 d2 0 1 i1 d2 1 1 i1 d2 0
one high output
d3 0 d3 0 d3 0 d3 1
• 2-input decoder: four possible
input binary numbers
– So has four outputs, one for each d0 0
i1’i0’ d0
possible input binary number 1 i0 d1 0
• Internal design i1’i0 d1 1 i1 d2 0
– AND gate for each output to e d3 1
detect input combination i1i0’ d2
1
• Decoder with enable e i1i0 d3 d0 0
– Outputs all 0 if e=0 1 i0 d1 0
– Regular behavior if e=1 1 i1 d2 0

• n-input decoder: 2n outputs i1 i0

e d3 0
a
a
0
Digital Design 2e
Copyright © 2010 54
Frank Vahid
 Example: Sprinkler Controller
• Microprocessor outputs which zone to water (e.g., cba=110
means zone 6) and enables watering (e=1)
• Decoder should set appropriate valve to 1

zone 0
Step 1: Capture
zone 1
a
d0 behavior
d1
b d2 2
Micro- d3 3
4
d0 = a'b'c'e a

processor c
d4
d5
d1 = a'b'ce
decoder d6 5
e d7
6 d2 = a'bc'e
7
d3 = a'bce
d4 = ab'c'e
d5 = ab'ce
Digital Design 2e
Equations seem like d6 = abc'e
a natural fit 55
Copyright © 2010
Frank Vahid d7 = abce
 Example: Sprinkler Controller
• Step 2b: Implement as circuit a
b
c d0
zone 0 zone 1
d0
a
d1

Micro-
b d2
d3 3
2 d1
c 4
processor d4
d5
decoder d6 5
e 6
d7 7 d2

d3
d0 = a'b'c'e
d1 = a'b'ce d4
d2 = a'bc'e
d3 = a'bce d5

d4 = ab'c'e
d6
d5 = ab'ce
d6 = abc'e d7
e
Digital Design 2e
Copyright © 2010
d7 = abce 56
Frank Vahid
 Multiplexer (Mux)
• Mux: Another popular combinational building block
– Routes one of its N data inputs to its one output, based on binary
value of select inputs
• 4 input mux  needs 2 select inputs to indicate which input to route
through
• 8 input mux  3 select inputs
• N inputs  log2(N) selects
– Like a rail yard switch

Digital Design 2e
Copyright © 2010 58
Frank Vahid
 Mux Internal Design
i0 i0 (1*i0=i0)
2×1 2×1 2×1 d
1 i0 (0+i0=i0)
i0 i0 i0 i1
d d d 0
i1 i1 i1
0
s0 s0 s0
a
0 1

2x1 mux 0 s0

i0
4×1
i0 i1
i1 d
d
i2 i2
i3
s1 s0 i3

4x1 mux
s1 s0
Digital Design 2e
Copyright © 2010 59
Frank Vahid
 Muxes Commonly Together – N-bit Mux
2x1
a3 i0 Simplifying
d
b3 i1 notation:
s0
4-bit 4
2x1 4 C
a2 i0 2x1
d A I0 4
b2 i1 D C is short
s0 4
B I1 for
2x1
a1 i0 s0
d
b1 i1 c3
s0
s0 c2
2x1
a0 i0
d c1
b0 i1
s0
s0 c0

• Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0)

– 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select
between A or B

Digital Design 2e
Copyright © 2010 60
Frank Vahid
 N-bit Mux Example
From the car's 8-bit a
T 8
central computer I0 4x1
A 8 To the
I1 8 D
I 8 D above-
I2 mirror
M 8 display
I3
s1 s0
x y
We'll design
this later (encoder)

button

• Four possible display items

– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and
Miles remaining (M) – each is 8-bits wide
– Choose which to display on D using two inputs x and y
• Pushing button sequences to the next item
– Use 8-bit 4x1 mux
Digital Design 2e
Copyright © 2010 61
Frank Vahid
 Encoder and DeMux
• Encoder: n inputs with exactly one of them being set to 1,
log2(n) outputs for encoding.
4x2

4x2 encoder

• DeMux: one data input being passed through one of the

outputs. 1×2

1x2 demux
s0

Digital Design 2e
Copyright © 2010 62
Frank Vahid
 2.8

More Gates
1 1
NAND NOR XOR XNOR NAND NOR
x x x
F F x y
y y
F y a
x y F x y F x y F x y F x F
0 0 1 0 0 1 0 0 0 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0 x y
y
1 0 1 1 0 0 1 0 1 1 0 0
1 1 0 1 1 0 1 1 0 1 1 1 0 0

• NAND: Opposite of AND (“NOT AND”) • NAND same as AND with power &
• NOR: Opposite of OR (“NOT OR”) ground switched
• XOR: Exactly 1 input is 1, for 2-input • nMOS conducts 0s well, but not 1s
XOR. (For more inputs -- odd number (reasons beyond our scope) – so
of 1s) NAND is more efficient
• XNOR: Opposite of XOR (“NOT • Likewise, NOR same as OR with
XOR”) power/ground switched
• NAND/NOR more common
• AND in CMOS: NAND with NOT
Digital Design 2e • OR in CMOS: NOR with NOT
Copyright © 2010 64
Frank Vahid
 Completeness of NAND
• Any Boolean function can be implemented using just NAND
gates. Why?
– Need AND, OR, and NOT
– NOT: 1-input NAND (or 2-input NAND with inputs tied together)
– AND: NAND followed by NOT
– OR: NAND preceded by NOTs
– Thus, NAND is a universal gate
• Can implement any circuit using just NAND gates
• Likewise for NOR

Digital Design 2e
Copyright © 2010 66
Frank Vahid
 Additional Considerations
2.10

Non-Ideal Gate Behavior -- Delay

1 1 1
x x x x
F
y 0 0 0

1 1 1
y y y
0 0 0

(1.8 V) 1 1 1
F F F
(0 V) 0 0 0
time time time
(a ) (b ) a
(c )
a a
ideal more with delay but
realistic otherwise ideal
• Real gates have some delay
– Outputs don’t change immediately after inputs change

Digital Design 2e
Copyright © 2010 67
Frank Vahid
 Circuit Delay and Critical Path
k BeltWarn

p 1 ns
1 ns
1 ns 1 ns a
w
s 1 ns 1+1+1+1+1 = 5 ns
1 ns
1 ns 1 ns 1+0.5+1+1+1+1+1 = 6.5 ns
0.5 ns
t 1 ns 1+1+1 = 3 ns
Critical path delay = 6.5 ns
Hence, circuit’s delay is 6.5 ns
• Wires also have delay
• Assume gates and wires have delays as shown
• Path delay – time for input to affect output
• Critical path – path with longest path delay
Digital Design 2e
Copyright © 2010 • Circuit delay – delay of critical path 68
Frank Vahid
 Chapter Summary
• Combinational circuits
– Circuit whose outputs are function of present inputs
• No “state”
• Switches: Basic component in digital circuits
• Boolean logic gates: AND, OR, NOT – Better building block than switches
– Enables use of Boolean algebra to design circuits
• Boolean algebra: Uses true/false variables/operators
• Representations of Boolean functions: Can translate among
• Combinational design process: Translate from equation (or table) to
circuit through well-defined steps
• More gates: NAND, NOR, XOR, XNOR also useful
• Muxes and decoders: Additional useful combinational building blocks

Digital Design 2e
Copyright © 2010 69
Frank Vahid
 Verilog introduction
For our own reference. The TAs will go over a better intro to
Verilog slides with you

Digital Design 2e
Copyright © 2010 70
Frank Vahid
 9.1

Verilog Introduction
DoorOpener
• A drawing of a circuit, or c
schematic, contains
h f
graphical information about p
a design
– Inverter is above the OR gate,
AND gate is to the right, etc.
a
• Such graphical information si tap
a
may not be useful for large rtn
designs o
c
o
t
• Can use textual language g
instead

Digital Design 2e
Copyright © 2010 71
Frank Vahid
Note: Slides with animation are denoted with a small red "a" near the animated items
 Textual Language – English
• Can describe circuit using English text rather than using a drawing
– Of course, English isn't a good language for a computer to read
– Need a more precise, computer-oriented language

(a) (b) We'll now describe a circuit whose name isDoorOpener.

DoorOpener
Inv_1 The external inputs are c, h and p, which are bits.
The external output isf, which is a bit.
c
We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
h f A 2-input ORgate, which has inputs x and y, and bit output F.
n1
p A 2-input AND gate, which has bit inputs x and y, and bit output F.
n2
AND2_1 The circuit has internal wires n1 and n2, both bits.
OR2_1 The DoorOpener circuit internally consists of:
An inverter named Inv_1, whose input x connectsto
external input c, and whose output connectsto n1.
A 2-input ORgate named OR2_1, whose inputsconnect to external
inputs h and p, and whose output connectsto n2.
A 2-input AND gate named AND2_1, whose inputsconnect to n1
and n2, and whose output connectsto external output f.
That's all.

Digital Design 2e
Copyright © 2010 72
Frank Vahid
 Computer-Readable Textual Language for
Describing Hardware Circuits: HDLs
• Hardware description language (HDL)
– Intended to describe circuits textually, for a computer to read
– Evolved starting in the 1970s and 1980s
• Popular languages today include:
– VHDL –Defined in 1980s by U.S. military; Ada-like language
– Verilog –Defined in 1980s by a company; C-like language
– SystemC –Defined in 2000s by several companies; consists of
libraries in C++

Digital Design 2e
Copyright © 2010 73
Frank Vahid
Combinational Logic Description using Hardware 9.2

Description Languages
• Structure DoorOpener
– Another word for "circuit" c

– An interconnection of h f
components p

– Key use of HDLs is to describe

structure

Note: The term "instantiate" will be used to indicate adding a new

copy of a component to a circuit
The OR component Three instances of the OR component
OR_1 OR_2

OR_3
Digital Design 2e
Copyright © 2010 74
Frank Vahid
 Describing Structure in VHDL
DoorOpener
• Entity – Defines new c
Inv_1

item's name & ports

f
(inputs/outputs) h n1
p
– std_logic means bit n2
AND2_1
l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;
OR2_1
type, defined in ieee e n t i t y Do o r Op e n e r i s
(a) por t ( c , h , p : i n s t d _ l o g i c ;
library f : out s t d _ l o g i c
We'll now describe a circuit whose name is DoorOpener. );
• Architecture – The external inputs are c, h and p, which are bits. e n d Do o r Op e n e r ;
The external output is f, which is a bit.
Describes internals, a r c h i t e c t u r e Ci r c u i t o f Do o r Op e n e r i s
We assume you know the behavior of these components: c o mp o n e n t I n v
which we named "Circuit" An inverter, which has a bit input x, and bit output F. por t ( x : i n s t d _ l o g i c ;

– Declares 3 previously- A 2-input OR gate, which has inputs x and y,

and bit output F.
F: out s t d _ l o g i c ) ;
e n d c o mp o n e n t ;
defined components A 2-input AND gate, which has bit inputs x and y, c o mp o n e n t OR2
and bit output F. por t ( x , y : i n s t d _ l o g i c ;
– Declares internal F: out s t d _ l o g i c ) ;

signals The circuit has internal wires n1 and n2, both bits. e n d c o mp o n e n t ;
c o mp o n e n t AND2
• Note "--" comment The DoorOpener circuit internally consists of: por t ( x , y : i n s t d _ l o g i c ;
An inverter named Inv_1, whose input x connects to F: out s t d _ l o g i c ) ;
– Instantiates and external input c, and whose output connects to n1. e n d c o mp o n e n t ;

connects those A 2-input OR gate named OR2_1, whose inputs s i g n a l n 1 , n 2 : s t d _ l o g i c ; - - i n t e r n a l wi r e s

connect to external inputs h and p, and whose output
components connects to n2. be gi n
A 2-input AND gate named AND2_1, whose inputs I n v _ 1 : I n v p o r t ma p ( x = > c , F = > n 1 ) ;
connect to n1 and n2, and whose output connects to OR2 _ 1 : OR2 p o r t ma p ( x = > h , y = > p , F = > n 2 ) ;
external output f. AND2 _ 1 : AND2 p o r t ma p ( x = > n 1 , y = > n 2 , F = > f ) ;
That's all. e n d Ci r c u i t ;

Digital Design 2e (b) (c)

Copyright © 2010 75
Frank Vahid
 Describing Structure in Verilog
DoorOpener
Inv_1
• Modules defined for c

Inv, OR2, and AND2 h n1

f

(details omitted) p
n2
AND2_1
OR2_1
– Note "//" comment
(a)
•
mo d u l e I n v ( x , F) ;
Module defined for We'll now describe a circuit whose name is DoorOpener. i nput x ;
The external inputs are c, h and p, which are bits. out put F;
DoorOpener The external output is f, which is a bit. / / det ai l s
e n d mo d u l e
not s h o wn

– Lists inputs and We assume you know the behavior of these components:
An inverter, which has a bit input x, and bit output F.
mo d u l e OR2 ( x ,
i nput x , y ;
y, F) ;

outputs A 2-input OR gate, which has inputs x and y,

and bit output F.
out put F;
/ / det ai l s not s h o wn

– Declares internal A 2-input AND gate, which has bit inputs x and y, e n d mo d u l e
and bit output F. mo d u l e AND2 ( x , y, F) ;
i nput x , y ;
wires The circuit has internal wires n1 and n2, both bits. out put F;
/ / det ai l s not s h o wn
– Instantiates and The DoorOpener circuit internally consists of: e n d mo d u l e
An inverter named Inv_1, whose input x connects to
connects three external input c, and whose output connects to n1. mo d u l e Do o r Op e n e r ( c , h , p , f ) ;
A 2-input OR gate named OR2_1, whose inputs i nput c , h , p ;
components connect to external inputs h and p, and whose output out put f ;
connects to n2. wi r e n 1 , n 2 ;
A 2-input AND gate named AND2_1, whose inputs I nv I nv_1( c, n1) ;
connect to n1 and n2, and whose output connects to OR2 OR2 _ 1 ( h , p , n 2 ) ;
external output f. AND2 AND2 _ 1 ( n 1 , n 2 , f ) ;
That's all. e n d mo d u l e

(b) (c)
Digital Design 2e
Copyright © 2010 76
Frank Vahid
 Describing Structure in SystemC
DoorOpener

•
Inv_1
Module defined c

– Declares inputs h f
n1
and outputs p
n2
#i nc l ude " s y s t e mc . h "
#i nc l ude " i nv. h"
– Declares internal OR2_1
AND2_1 #i
#i
nc l
nc l
ude
ude
"
"
or 2. h"
and2. h"
wires (a)
SC_ MODUL E ( Do o r Op e n e r )
• Note "//" We'll now describe a circuit whose name is DoorOpener. {
The external inputs are c, h and p, which are bits. s c _ i n<s c _ l ogi c > c , h , p ;
comment The external output is f, which is a bit. s c _ out <s c _ l ogi c > f ;

– Declares three
/ / i n t e r n a l wi r e s
We assume you know the behavior of these components: s c _ s i gna l <s c _ l ogi c > n 1 , n 2 ;
An inverter, which has a bit input x, and bit output F. / / c o mp o n e n t d e c l a r a t i o n s
previously-defined A 2-input OR gate, which has inputs x and y, I nv I nv1;

components and bit output F.

A 2-input AND gate, which has bit inputs x and y,
OR2 OR2 _ 1 ;
AND AND2 _ 1 ;

– Constructor and bit output F. / / c o mp o n e n t i n s t a n t i a t i o n s

SC_ CT OR( Do o r Op e n e r ) : I n v _ 1 ( " I n v _ 1 " ) ,
The circuit has internal wires n1 and n2, both bits. OR2 _ 1 ( " OR2 _ 1 " ) , AND2 _ 1 ( " AND2 _ 1 " )
function "CTOR" {

• Instantiates The DoorOpener circuit internally consists of: I nv_1. x( c) ;

An inverter named Inv_1, whose input x connects to I n v _ 1 . F( n 1 ) ;
components external input c, and whose output connects to n1. OR2 _ 1 . x ( h ) ;
OR2 _ 1 . y ( p ) ;
A 2-input OR gate named OR2_1, whose inputs
• Connects connect to external inputs h and p, and whose output OR2 _ 1 . F ( n 2 ) ;
AND2 _ 1 . x ( n 1 ) ;
connects to n2.
components A 2-input AND gate named AND2_1, whose inputs AND2 _ 1 . y ( n 2 ) ;
connect to n1 and n2, and whose output connects to AND2 _ 1 . F ( f ) ;
external output f. }
That's all. } ;

(b) (c)
Digital Design 2e
Copyright © 2010 77
Frank Vahid
 Combinational Behavior

• Combinational behavior
– Description of desired behavior of combinational circuit without
creating circuit itself
– e.g., F = c' * (h + p) can be described as equation rather than circuit
– HDLs support description of combinational behavior

Digital Design 2e
Copyright © 2010 78
Frank Vahid
 Describing Combinational Behavior in VHDL
• Describing an OR gate's
behavior
library ieee;
– Entity defines input/output ports use ieee.std_logic_1164.all;

– Architecture entity OR2 is

port (x, y: in std_logic;
• Process – Describes behavior F: out std_logic
);
– Process "sensitive" to x and y end OR2;
» Means behavior only
architecture behavior of OR2 is
executes when x begin
changes or y changes process (x, y)
begin
– Behavior assigns a new value F <= x or y;
to output port F, computed end process;
using built-in operator "or" end behavior;

Digital Design 2e
Copyright © 2010 79
Frank Vahid
 Describing Combinational Behavior in VHDL
• Describing a custom
function's behavior
– Desired function: f = c'*(h+p)
– Entity defines input/output ports architecture beh of DoorOpener is
begin
(not shown) process(c, h, p)
begin
– Architecture f <= not(c) and (h or p);
• Process end process;
end beh;
– Sensitive to c, h, and p
– Assigns a new value to output
port f, computed using built-in
operators "not", "and", and "or"

Digital Design 2e
Copyright © 2010 80
Frank Vahid
 Testbenches
• Testbench
– Assigns values to a system's inputs, check that system outputs
correct values
– A key use of HDLs is to simulate system to ensure design is correct

Testbench

Set input
values,
check SystemToTest
output
values

Digital Design 2e
Copyright © 2010 81
Frank Vahid
 Testbench in VHDL
• Entity l i br a r y i e e e ;
us e i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ;

– No inputs or outputs e nt i t y Te s t b e n c h i s

•
e nd Te s t b e n c h ;
Architecture a r c hi t e c t ur e b e h a v i o r of Te s t b e n c h i s
– Declares component to test, c o mp o n e n t Do o r Op e n e r
por t ( c , h , p : i n s t d _ l o g i c ;
declares signals ) ;
f : out s t d _ l o g i c

– Instantiates component, connects e n d c o mp o n e n t ;

s i gna l c , h , p , f : s t d _ l o g i c ;
to signals be gi n
Do o r Op e n e r 1 : Do o r Op e n e r p o r t ma p ( c , h , p , f ) ;

– Process writes input signals, pr oc e s s

checks output signal be gi n
- - case 0
• Waits a small amount of time c <= ' 0' ; h <= ' 0' ; p <= ' 0' ;
wa i t f o r 1 n s ;
after writing input signals a s s e r t ( f = ' 0 ' ) r e p o r t " Ca s e 0 f a i l e d " ;

• Checks for correct output value - - case 1

using "assert" statement c <= ' 0' ; h <= ' 0' ; p <= ' 1' ;
wa i t f o r 1 n s ;
DoorOpener1 a s s e r t ( f = ' 1 ' ) r e p o r t " Ca s e 1 f a i l e d " ;
- - ( c a s e s 2 - 6 o mi t t e d f r o m f i g u r e )
- - case 7
Testbench
process c <= ' 1' ; h <= ' 1' ; p <= ' 1' ;
wa i t f o r 1 n s ;
a s s e r t ( f = ' 0 ' ) r e p o r t " Ca s e 7 f a i l e d " ;
Set input
values, wa i t ; - - p r o c e s s does not wa k e u p a g a i n
e nd pr oc e s s ;
check SystemToTest e nd b e h a v i o r ;
Digital Design 2e output
Copyright © 2010 values 82
Frank Vahid