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DFT SCAN

Design for testability (DFT) encompasses practices that ensure fault detection, economical test development, and efficient test execution in electronic systems, which include digital logic, memory blocks, and analog circuits. Ad-hoc DFT methods improve testability by following good design practices, while structured DFT involves adding extra logic for predefined testing procedures, such as scan design. Scan design allows flip-flops to function as shift registers, enhancing control and observability during testing, though it incurs significant overhead in terms of gates and test pins.

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DFT SCAN

Design for testability (DFT) encompasses practices that ensure fault detection, economical test development, and efficient test execution in electronic systems, which include digital logic, memory blocks, and analog circuits. Ad-hoc DFT methods improve testability by following good design practices, while structured DFT involves adding extra logic for predefined testing procedures, such as scan design. Scan design allows flip-flops to function as shift registers, enhancing control and observability during testing, though it incurs significant overhead in terms of gates and test pins.

Uploaded by

pavipavi4488
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MOTIVATION

Design for testability (DFT) refers to those design practices that allow us to answer
the questions

1. Can tests that detect all faults be assured?


2. Can test development time be kept low enough to be economical?
3. Can test execution time be kept low enough to be economical?

Electronic systems contain three types of components:


(a) digital logic,
(b)memory blocks, and
(c) analog or mixed-signal circuits.

 Built-in self-test (BIST), which is also used for digital logic as well as for memory blocks
 Boundary-scan and analog test bus, provide test access to components embedded in a
system

Ad-Hoc DFT Methods


DFT techniques that aim at improving the testability of stuck-at faults

Logic DFT takes one of two possible routes: ad-hoc and structured.
The adhoc DFT relies on “good” design practices learned from experience
.
• Avoid asynchronous logic feedbacks. A feedback in the combinational logic can
give rise to oscillation for certain inputs. This makes the circuit difficult to
verify and impossible to generate tests for by automatic programs. This is
because test generation algorithms are only known for acyclic combinational
circuits.
• Make flip-flops initializable. This is easily done by supplying clear or reset
signals that are controllable from primary inputs.
• Avoid gates with a large number of fan-in signals. Large fan-in makes the
inputs of the gate difficult to observe and makes the gate output difficult to
control.
• Provide test control for difficult-to-control signals. Signals such as those produced
by long counters require many clock cycles to control and hence increase the length
of the test sequence. Long test sequences are harder to generate.

Once testability problems are found, either the circuit is modified or test points are
inserted.
In structured DFT, extra logic and signals are added to the circuit so as to allow the
test according to some predefined procedure. Apart from the normal functional
mode, such a design will have one or more test modes. Commonly used structured
methods are scan (discussed in
this chapter) and built-in self-test.

Scan Design
obtain control and observability for flip-flops all flip-flops functionally form one or
more shift registers
scan function is called random-access scan (RAS) [733]. In that design, flip-flops
work as addressable memory elements in the test mode in a similar fashion as a
random access memory (RAM.)
This approach reduces the time of setting and observing the flip-flop states, but the
design requires a large overhead both in gates and test pins.

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