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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1

Analysis of mm-Wave Multi-Stage

Rectifier and Implementation
Yun Fang, Member, IEEE, Wei Hong , Fellow, IEEE, and Hao Gao , Member, IEEE

Abstract— In the mm-wave frequency band, the rectifier’s sen-

sitivity is the bottleneck of a wireless-powered IoT transponder’s
distance. At a meter’s distance, the received power is weak,
and transistors in a front end of a wireless power receiver
operate in the weak inversion region. This article presents a
mathematical analysis of the mm-wave multi-stage rectifier in the
low-power region. A design methodology of a 57–64-GHz fully
integrated eight-stage rectifier with a bulk-drain connection in 40-
nm CMOS technology is presented. Parasitic effects on a multi-
stage rectifier are analyzed. Based on the analysis, an intrinsic
threshold voltage modulation is applied to improve the sensitivity.
A tree-type power splitter is also proposed for the RF power
signal’s phase balance. With this method, the RF signal arrives at
Fig. 1. Concept illustration of an mm-wave WPT system with its link budget
each stage with an equal phase, and its suppression at the output estimation at 60-GHz ISM band for a 1.5-m wireless transfer distance.
is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm
input sensitivity at 57 GHz with 1-V dc output voltage. The
overall sensitivity from 57 to 64 GHz is better than −4.5 dBm.
Compared to other mm-wave silicon-based rectifier state of the attractive solution for their unique advantage of maintenance-
arts, the proposed mm-wave rectifier achieves better sensitivity free usage.
while maintaining a compact size. In such an mm-wave wirelessly powered IoT transponder,
Index Terms— CMOS, mm-wave, rectenna, rectifier, sensitivity, the transponder works in a sequential architecture [1]: the
wireless power receiver. energy is temporarily stored and then consumed. Compared
to a duplex system, such as an RFID system, it can provide
I. I NTRODUCTION more instant energy. In this architecture, a rectifier’s sensitivity
dominates the communication distance instead of its efficiency.

S INCE the mm-wave frequency band was introduced into

commercial wireless communication, the IoT transponder
function at mm-wave frequencies has received much attention
At 60 GHz, in the order of 6 × 6 cm2 size, a power transmitter
could integrate with a 16 × 16-element slot array antenna
of 30-dBi gain [2]. A compact IoT transponder could also
for its potential massive deployment combined with cloud integrate with an 8 × 8-element array of 25-dBi gain, which
computing and AI technology. In these scenarios, low cost is in the order of a quarter-sized smart card. The rectifier’s
and small size are crucial requirements for the transponder. sensitivity requirement could be derived from a regulated
The conventional solution is mostly battery-operated. The 10-dBm output power of a 60-GHz power transmitter [3]
battery limits the transponder’s size, and its replacement adds and half-room-height (1.5-m) transfer distance, as shown in
significant maintenance costs for the massive deployment. Fig. 1. According to the Friis transmission equation, the
IoT transponders with the wireless power function would be an free-space path loss at the 60-GHz band with a 1.5-m distance
Manuscript received 30 March 2022; revised 7 June 2022; accepted 12 July is 71.5 dB. Furthermore, the 60-GHz band is characterized
2022. This work was supported in part by the Interuniversity Microelectronics by high levels of atmospheric energy absorption. The maxi-
Centre, imec, Belgium, through the Europractice-HSP Program, under Grant mum oxygen absorption is 10–15 dB/km [4], resulting extra
G2021016011L; and in part by the Project TERALINK. (Yun Fang and
Hao Gao are co-first authors.) (Corresponding author: Hao Gao.) 0.015–0.025-dB loss in this system. In this combination,
Yun Fang is with the Electrical Engineering Department, Eindhoven Uni- a rectifier with −6.6-dBm sensitivity is crucial for a 1.5-m
versity of Technology, 5612 AZ Eindhoven, The Netherlands, and also with distance indoor application.
the mm-Wave Laboratory, Silicon Austria Labs, 4040 Linz, Austria (e-mail:
[email protected]). At mm-wave frequency bands, a rectifier could be imple-
Wei Hong is with the School of Information Science and Engineering, mented by Schottky diodes with high efficiency due to its low
Southeast University, Nanjing 210096, China (e-mail: [email protected]). turn-on voltage [5], [6], [7], [8], [9]. However, the Schottky
Hao Gao is with the Electrical Engineering Department, Eindhoven Univer-
sity of Technology, 5612 AZ Eindhoven, The Netherlands, and also with the diode has a compatibility issue with deep submicrometer
School of Information Science and Engineering, Southeast University, Nanjing silicon-based technology in a fully integrated on-chip wireless
210096, China (e-mail: [email protected]). power receiver solution. A rectifier based on diode-connected
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TMTT.2022.3197755. transistors is an on-chip integration solution in deep submi-
Digital Object Identifier 10.1109/TMTT.2022.3197755 crometer silicon technology. To overcome the limited output
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/
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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

In this article, we propose a compact and robust mm-wave

multi-stage rectifier with a bulk-drain connection. This intrin-
sic threshold voltage modulation improves the sensitiv-
ity without introducing extra bias voltages. Compared to
inductor-peaking and IPVM rectifiers, this mm-wave multi-
stage rectifier is much more compact and allows broad-
band operation. The proposed mm-wave rectifier works at
the low input power range, and transistors operate in the
weak-inversion region at the front-end circuits. In this region,
the ac-to-dc analysis proposed in [10] and the analysis in [32]
are no longer applicable to this rectifier. A detailed analysis of
a multi-stage rectifier in a weak input power with bulk-drain
Fig. 2. mm-wave N -stage rectifier based on the Dickson multiplier structure. connected transistors is also presented.
This article is organized as follows. Section II presents the
bulk-drain connection transistor and N-stage rectifier model-
voltage from a one-stage rectifier, Dickson voltage multipliers ing with steady-state analysis in a low voltage swing situation.
are proposed in [10] and are widely used in [11], [12], [13], Section III describes the design methodology of an eight-stage
[14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], mm-wave rectifier in CMOS technology. The measurement
[25], [26], and [27]. The architecture is shown in Fig. 2. results are discussed in Section IV. The conclusions are drawn
However, the threshold voltage in a diode-connected transistor in Section V.
still limits the rectifiers’ sensitivity: the transistor would only
conduct a strong current when the voltage swing is larger than
II. MM -WAVE R ECTIFIER W ITH B ULK -D RAIN
the threshold voltage.
C ONNECTED T RANSISTORS
In history, several techniques have been proposed to over-
come the threshold voltage limitation in the Dickson voltage The sensitivity of an mm-wave rectifier in CMOS tech-
multipliers. They could be classified into three categories. nology is limited by the transistor’s threshold voltage. The
1) The first category is the equivalent threshold voltage 1-V sensitivity [23] is in the range of −3–1 dBm at 45, 60,
reduction technique. It could be achieved by shifting the and 24 GHz [1], [11], [12]. The threshold voltage can be
threshold voltage by introducing a gate-bias voltage [13], modulated through a bulk voltage by taking advantage of the
[14] or modulating the threshold voltage by a bulk- deep N-well in the bulk CMOS technology or SOI technology.
bias (BB) voltage [15], [16]. Those rectifiers’ bottleneck This threshold modulation technique can improve a rectifier’s
is the requirement of extra bias voltages. Therefore, 1-V sensitivity to −5 dBm at 60 GHz [15]. However, the
an internal-threshold canceling (ITC) rectifier in [17], external bias voltage limits its application in an on-chip
[18], [19], [20], [21], and [22] is applied to solve this wireless power receiver. Therefore, an mm-wave rectifier with
issue. bulk-drain connected transistors is proposed. In this method,
2) The second category is the inductor peaking (LP) tech- the bulk voltage is directly connected to the input RF node.
nique. The gate voltage swing is boosted by inserting an With an increased input signal, the threshold voltage can
inductor in-between the gate and source [23], [24], [25], be reduced with the input voltage amplitude. As shown in
[26]. However, the voltage phase difference between Fig. 3, under the same input power level and load conditions,
gate–source and drain–source generates a reverse leak- the bulk-drain connection rectifier improves sensitivity and
age current, limiting a rectifier’s performance. efficiency by 22% and 58%, respectively. Few studies report
3) The third category is the technique combination of this low input power region. In this section, an analysis with
threshold voltage reduction and gate voltage boost- a mathematical model is provided for an mm-wave bulk-drain
ing [27]. It could be achieved by inserting an in-phase connection rectifier for sensitivity optimization.
passive voltage multiplier (IPVM), and an ITC bias The cross-view of a bulk-drain connected transistor is
scheme to boost the forward current while minimizing shown in Fig. 4(a). In a deep submicrometer technology, the
the reverse-leakage current. However, it has a complex deep N-well option enables the bulk to be biased separately
control scheme, and the separation of bias and booster instead of connected to the lowest voltage. In this bulk-drain
would have the bottleneck of a starting issue. connection, the gate, the drain, and the bulk of an n-type
Furthermore, some other topologies have been explored transistor are connected together as the input port. The source
in [28], [29], [30], and [31]. He and Zhao [28] proposed an is the output port. Since the bulk and gate are connected
mm-wave switching rectifier, extracting the dc signal from the to the same voltage potential, an n-type transistor with a
drain of a switching transistor by mixing the RF signal and its bulk-drain connection has three effective parasitic diodes and
phase-shifted replica. Weissman et al. [29], Shaulov et al. [30], two effective parasitic capacitors. Those parasitic diodes are
and Vroede et al. [31] employed a differential Colpitts VCO the diode between bulk and source DBS , the diode between
along with an on-chip antenna to realize RF-to-dc conversion. bulk and N-well DISO , and the diode between N-well and
However, the switching rectifier and the Colpitts VCO-based P-substrate DWELL . Those effective parasitic capacitors are
rectifier show limited sensitivity. CGS and CBS . In this bulk-drain connection, DISO and DWELL
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FANG et al.: ANALYSIS OF mm-WAVE MULTI-STAGE RECTIFIER AND IMPLEMENTATION 3

Fig. 5. AC and ac-to-dc analysis of the ith-stage rectifier.

to a dc voltage level to keep the same forward-bias voltage

and the same conduction angle for each transistor.
Since the voltage and the current waveform are the same
for each stage in the steady stage, it would be convenient to
analyze only one stage and multiply its boost voltage with the
Fig. 3. Simulated output voltage and efficiency of rectifiers with different stage number, N, to get the final dc output voltage. The ac
bulk connections. and dc equivalent circuit for the i th-stage rectifier is shown in
Fig. 5. The ac portion of voltage at each node is indicated with
blue color, while the dc portion is indicated with red color. The
ac-to-dc conversion is provided by the unbalanced charging
current of nonlinear devices, so the charge contributed by any
linear device is zero in one input RF signal’s period. In this
way, the analysis of the i th-stage rectifier is divided into two
parts: ac analysis to determine the amplitude of V  ai and ac-to-
dc analysis to determine the boost voltage Vbst .
Fig. 4. (a) Cross view and (b) equivalent circuit of an n-type transistor with Because of the loading capacitors, the dc input and output
bulk-drain connection in a deep N-well technology. ports have extremely small ac portion voltages. In this consid-
eration, they are simplified as ac ground. Therefore, V  ai can be
calculated by the voltage division of Cc and the sum of C p1
are in series and creating a path between node Vin and ground. and C p2 . In the single-stage rectifier, M1,2 and their parasitic
Those two diodes are always reverse-biased, restraining the diode DBS1,2 are turned on alternatively in the negative and
leakage current to its reverse saturation current, and it is positive half periods, respectively. Since CBS is the parasitic
irrelevant to Vin ’s phase. The two parasitic capacitors are in capacitor of DBS , it will be shorted when DBS is turned on.
series and are modeled as C W : between bulk and N-well, Thus, the effective CBS would only be counted once in every
and between N-well and P-substrate. Therefore, the equivalent input period, while parasitic capacitors CGS and C W in both
circuit of the bulk-drain connection n-type transistor is shown transistors are always effective
in Fig. 4(b). The bulk-drain connection n-type transistor has
 Cc 
a parallel diode DBS , two parallel capacitors CGS and CBS , Vai = VRF (1)
along with a parasite capacitor C W , and a leakage current Ileak Cc + Cpar
between Vin and ground. where Cpar = C p1 + C p2 = 2(CGS + C W ) + CBS .

In ac-to-dc analysis, V ai and dc voltage differential Vbst are
A. Steady-State Analysis used to generate the unbalanced current I1 (t) or I2 (t). Because
M1 and M2 , and coupling and loading capacitors are in the
In the rectifier, each identical stage consists of two same size, the unbalanced current and the boost voltage are
bulk-drain connected transistors in a series-cascade way. The the same. For simplicity, the following analysis will be carried
sinusoidal RF signal VRF is ac-coupled to each stage’s series out with a one-transistor rectifier.
node. The loading capacitors are large enough to store the
charge without generating significant ripples.
Before a steady state, it is assumed that all the coupling and B. Analysis of One-MOS Rectifier
loading capacitors have no charges. When VRF < 0, forward- Fig. 6(a) shows the ac-to-dc conversion model of a single
biased Mi_1 charges CCi . When VRF > 0, Mi_2 charges CLi and bulk-drain connected transistor, and Fig. 6(b) shows the ac
generates the dc voltage. The same mechanism is repeated in portion Va , dc boost voltage Vbst , and the total current through
every subsequent stage, and the rectifier eventually offers a the n-type transistor with its parasitic diode. The leakage cur-
stable output dc voltage and load current. In the steady state, rent generated by DISO and DWELL is neglected for simplicity
every transistor’s forward and reverse current is the same. The considering the extremely small current contribution.
current is transported to the load current one by one. With Since the RF input signal is not large enough to turn on
identical capacitors, the output-to-input dc boost voltage will a transistor, the bulk-drain connected transistor is assumed
be the same. The series node Vai in each stage will be charged to work at the weak-inversion region during the whole
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

For the load capacitor, the charging current is formed by

the forward current of the bulk-drain connected transistor
and parasitic diode. The discharging current consists of load
current Iload and the reverse current from the nonlinear devices.
In the steady state, the input charge Q in equals the output
charge Q out , and it can be expressed as
t2
Q in = |Idsub (t) + Ibs (t)|dt (9)
t1
T +t1
Q out = Iload T + |Idsub (t) + Ibs (t)|dt. (10)
t2
Fig. 6. (a) AC-to-dc conversion model of a bulk-drain connected transistor
and (b) its voltage and current waveform. Because the above equations contain a term exp(cos ωt),
which has no Riemann integral function, the input signal
Va cos ωt is simplified as its first two terms of the Taylor series
period. The transistor is forward-biased during [t1 , t2 ] and expansion Va (1 − ω2 t 2 /2). This approximation can only be
reverse-biased during the rest of the period. The subthreshold used in [t1 , t2 ] to calculate Q in . Thus, |t1,2 | can be simplified
current in this region can be expressed as [33] as
    
Vds Vgs − Vth − VOFF |t1,2 | = 2(Va − Vbst )/Va /ω. (11)
Idsub = Is0 1 − exp − exp (2)
vt nv t
 The input charge contributed by the subthreshold current Q d1
W qεsi Nch 2 is expressed as
Is0 = μ0 v (3)
L 2φs t 
(1 + k)Va
where v t is the thermal voltage, n is the subthreshold swing Q d1 = Is1 erf ωt2
parameter, VOFF is the subthreshold region offset voltage, Vth is 2nv t

the threshold voltage of the transistor, μ0 is the mobility, q is (1 + k − n)Va
the electron charge, εsi is the silicon permittivity, Nch is the − Is2 erf ωt2 (12)
2nv t
doping concentration in the channel, and φs is the surface
potential. where
Given the transistor in bulk-drain connection, the varied 
Is0 exp [(1 + k)(Va − Vbst )/nv t ]
bulk–source voltage introduces varied threshold voltage Vth . Is1 = √ (13)
ω (1 + k)Va /2πnv t
Thus, the body effect should be considered in this analysis,
I  exp [(1 + k − n)(Va − Vbst )/nv t ]
expressed as Is2 = s0 √ . (14)
 ω (1 + k − n)Va /2πnv t
Vth = Vth0 + K 1 φs − Vbs − φs − K 2 Vbs (4)
The input charge contributed by the forward-biased diode
where Vth0 is the threshold voltage when Vbs = 0, K 1 and current Q b1 is expressed as
K 2 are first- and second-order body effect coefficients, respec- 
Q b1 = −2Isbs t2 + Isbs erf( Va /2Ntm ωt2 ) (15)
tively. Given that Vbs is quite small, the threshold voltage Vth
can be linearized as where
  
K1  
Vth = Vth0 − √ + K 2 Vbs  Isbs 2π Ntm Va − Vbst
2 φs Isbs = exp . (16)
ω Va Ntm
≈ Vth0 − kVbs . (5)
When the transistor is reverse-biased, the transistor leakage
Therefore, Idsub can be further expressed as
     current Idlk is the subthreshold current with Vgs = 0. Due to
 Vds (1 + k)Vds its small value, it would be unnecessary to calculate it without
Idsub = Is0 1 − exp − exp (6)
vt nv t any approximation. Here, Idlk is approximated as a sinusoidal
where wave
 ⎧
  ⎪ T π T π
 W qεsi Nch 2 Vth0 + VOFF ⎨|Idlkp | cos ω (t − ts ), − 
≤t ≤ + 
Is0 = μ0 v exp − . (7) Idlk = 2 2ω 2 2ω
L 2φs t nv t ⎪
⎩0, T π T π
t< − , t> +
Assuming that the current model of the parasitic diode 2 2ω 2 2ω
DBS is a resistance-free diode without current limiting feature (17)
because of small ac voltage, Ibs can be expressed as where ω = 3π/(T − 2t2 ) and ts = (T + 4t2 )/6
        
Vbs Va + Vbst k(Va + Vbst )
Ibs = Isbs exp −1 (8) 
Idlkp = Is0 1 − exp exp − .
N Vtm vt nv t
where N Vtm = NJ v t ; NJ is the junction emission coefficient. (18)
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FANG et al.: ANALYSIS OF mm-WAVE MULTI-STAGE RECTIFIER AND IMPLEMENTATION 5

Thus, the output charge contributed by MOSFET leakage

current Q dlk is
Q dlk = 2(T − 2t2 )|Idlkp |/3π. (19)
The output charge contributed by DBS reverse current Q blk is
Q blk = Isbs (T − 2t2 ). (20)
A further approximation is with Q in = Q out . Assuming that
Va > 6v t and Vbst is small enough to ensure that Va − Vbst >
6v t , (12), (15), (19), and (20) can be simplified as


Is0 2πnv t (1 + k)(Va − Vbst )
Q d1 ≈ exp (21)
ω (1 + k)Va nv t

Isbs 2π N Vtm Va − Vbst
Q b1 ≈ exp (22)
ω Va N Vtm Fig. 7. Comparison of the mathematical model in this work to the PDK
 model: eight-stage rectifier output voltage with different load resistances and
 input amplitudes.
4Is0 2(Va − Vbst )
Q dlk ≈ π−
3ω Va
(n − k)(Va + Vbst )
× exp (23)
nv
 t
2Isbs 2(Va − Vbst )
Q blk ≈ π− . (24)
ω Va
The output dc voltage is the root of the charge balance
equation
Q d1 + Q b1 = Q d2 + Q b2 + 2π Iload /ω. (25)
To validate this analysis, a multi-stage rectifier is designed
and implemented with 40-nm CMOS technology. The simula-
tion comparison to the mathematical model is performed with
different load resistances and input amplitudes at 55 GHz.
In SPICE simulations, the transistors and MoM capacitors
Fig. 8. Comparison of the mathematical model in this work to the PDK
are based on the foundry-provided PDK RF model. The model: output voltage of multi-stage rectifiers with different load resistances
transistor’s Vth0 is 435 mV. When the rectifier is working in a and stage numbers.
high sensitivity range, the transistors are in the weak inversion
region. Because the input impedance of an eight-stage rectifier
is 8–46.8 j , the −8-, −7-, and −6-dBm input power are the voltage-depended Cpar . The mathematical model assumes
transferred to 290, 330, and 370 mV in the voltage domain. that each stage has the same Cpar , hence the same Va . However,
Fig. 7 shows the output voltage of the eight-stage rectifier the parasitic capacitance contributor C W is not the same in
with different input voltage amplitudes V  RF . Fig. 8 shows the each transistor. For the parasitic capacitor CGS or CBS , the
output voltage of three rectifiers with input voltage amplitude voltages on them are always V  ai together with one boost

V RF = 370 mV. The rectifiers’ stage numbers are 2, 4, and 8,
voltage Vbst . However, C W is the overall capacitance between
respectively. Compared to the PDK model, the output volt- the bulk and N-well, and between N-well and P-substrate.
Its voltage is V ai together with N times Vbst , depending on
ages calculated by the mathematical model are getting larger
when the input voltage increases. The deviation is coming the stage number. Because of the different C W capacitances,
a decreased V ai is observed. Therefore, the deviation becomes
from the forward-biased parasitic diode DBS . It is usually
recommended to be reverse-biased for an active transistor larger when more stages are used.
operation. However, in an mm-wave rectifier, it is forward-
biased periodically to deliver more current to the load and C. Power Consumption and Efficiency of N-Stage Rectifier
achieve better sensitivity. However, the forward-biased current The power consumption of the one-stage rectifier is the sum
in the model file is facing the modeling limitation from the of leakage power consumption and nonlinear device power
PDK recommended region. consumption. The nonlinear power consumption is contributed
As shown in Fig. 8, the output voltages calculated by the by bulk-drain connected transistors and parasite diodes in
mathematical model are also getting larger with the increase in forward- and reverse-biased regions
the stage number. This deviation comes from the decreased ac
portion amplitude Va . According to (1), Va is determined by Ploss = 2(Pleak + Pd1 + Pb1 + Pb2 + Pd2 ) (26)
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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 9. Theoretical and simulated efficiencies of an eight-stage rectifier with Fig. 10. Theoretical and simulated total efficiencies of multi-stage rectifiers
different load resistances and input amplitudes.
with different load resistances and stage numbers.

where Pleak is the power consumption of the leakage current III. R ECTIFIER I MPLEMENTATION
source Ileak , and Pd1 and Pb1 are the power consumption of A. Stage Number Optimization of N-Stage Rectifier
bulk-drain connected transistor and parasite diode in forward-
According to the rectifier mathematical analysis and model-
biased region, respectively, while Pd2 and Pb2 are those in
ing, a rectifier with more stages would have an advantage on
reverse-biased region. The approximation of those components
the output voltage under the same input amplitude and load
is listed as
condition. However, the measurement of mm-wave rectifiers
is based on power. High-stage rectifiers suffer from a lower
Pleak = 2Va Ileak /π (27) input amplitude because of their decreased input impedance.

 nv t (1 + k)(Va − Vbst ) Therefore, the optimal stage number should be found to
Pd1 ≈ Is0 (Va − Vbst ) exp
2π(1 + k)Va nv t achieve the best sensitivity.
(28) For each stage, the input impedance is mainly contributed
   by the input capacitor Cc . From the RF input port, each stage
N Vtm N Vtm Va − Vbst
Pb1 ≈ Isbs Va − Vbst − exp is connected in parallel in an N-stage rectifier. Therefore, its
2π Va 2 N Vtm input impedance Z in (n) can be expressed as
(29)
   Z in (n) = Z in (1)/n (33)
4I 2t2 (n − k)(Va + Vbst )
Pd2 ≈ s0 1 − (Va + Vbst ) exp
3π T nv t where Z in (1) is the input impedance of a one-stage rectifier.
(30) With an input power Pin , the N-stage rectifier’s input ampli-
 
2t2 tude VRF is derived as
Pb2 ≈ Isbs Vbst 1 − + Isbs Va sin(ωt2 )/π. (31)
T
VRF (n) = 2Pin Z in (1)/n. (34)

Therefore, the efficiency of the N-stage rectifier can now Fig. 11(a) shows the simulated input impedance and the input
be expressed as amplitude of different rectifiers with the same input power.
Taking the input impedance and input amplitude with a fixed
Pout power level into consideration, the eight-stage rectifier shows
η= . (32) the best sensitivity, as shown in Fig. 11(b). Therefore, the
Pout + N Ploss
matching network is designed for the eight-stage bulk-drain
connection rectifier.
Fig. 9 shows the efficiency of the eight-stage rectifier
with different input voltage amplitudes Vin , i.e., 290, 330,
and 370 mV. Fig. 10 shows the total efficiency of four-, B. Matching Network of N-Stage Rectifier
eight-, and 16-stage rectifiers with input voltage amplitude An eight-stage mm-wave rectifier is implemented with

V RF = 370 mV. Since the rectifier is working in the weak bulk-drain connected transistors. Different RF power levels
inversion region, the efficiency in all different scenarios is will influence the transistor’s working region. Therefore, the
quite limited. With the increase in the stage number, the parasitic capacitance and the input impedance vary between
efficiency dropping can be observed. Therefore, rectifiers with the weak inversion region and the strong inversion region [34].
fewer stage numbers are better when the maximum-efficiency In this work, the input matching network is done with an input
strategy is adopted. power of −6 to −4 dBm for the high-sensitivity application.
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FANG et al.: ANALYSIS OF mm-WAVE MULTI-STAGE RECTIFIER AND IMPLEMENTATION 7

Fig. 13. 3-D model of the input matching inductor and the TTPS. (a) 3-D
Fig. 11. (a) Input impedance and input amplitude with the same input power. model of the input matching inductor with meshed ground shielding. (b) 3-D
(b) 1-V sensitivity of multi-stage rectifiers with different stage numbers. model of the TTPS with input and output ports for each stage.

Fig. 14. Comparison on SSR for a rectifier with and without the TTPS.

Fig. 13 shows the 3-D models of the input matching inductor

and the TTPS. The TTPS feeds the input RF signal to each
stage with the same phase. Therefore, there is only one transis-
tor charging/discharging the load capacitor. Otherwise, some
capacitors will be charged by two transistors causing higher
voltage while the others with lower voltage by discharging.
The overcharge/discharge state will pass from the first stage
to the last one, introducing the final output’s ac component.
In the wireless power receiver, a rectifier is a power supply.
The high-frequency ac component at the dc output introduces
distortion for the load. The signal suppression ratio (SSR) is
Fig. 12. (a) Proposed eight-stage mm-wave rectifier with bulk-drain con- defined as the ratio between RF leakage power and dc power.
nected transistors, an input matching network, and a TTPS. (b) Input matching Fig. 14 shows a comparison of a rectifier with the TTPS
illustration in the Smith chart.
and without TTPS. By introducing an equal phase at each
A series inductor L in is used as the input matching network. stage’s input, the rectifier with TTPS improves the suppression
Also, a tree-type power splitter (TTPS) is inserted in-between by 16 dB.
the input matching inductor and the coupling capacitors,
as shown in Fig. 12. By cascading one-stage rectifier, the input IV. M EASUREMENT R ESULTS
impedance Z in1 is transformed to Z in2 . Considering the PAD The chip is fabricated in 40-nm CMOS technology. The
parasite capacitor Cpad , the mm-wave rectifier shows a well- die area, including the input matching inductor, is 0.2 ×
matched 50- impedance with an input matching network. 0.12 mm2 . The die micrograph and the measurement setup
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8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

TABLE I
S ILICON -BASED MM -WAVE R ECTIFIER P ERFORMANCE C OMPARISON TABLE

Fig. 16. Measured S11 of the rectifier and comparison to the simulated result.

Fig. 15. Die micrograph and measurement setup.

are shown in Fig. 15. The chip is measured with on-wafer RF presented in Fig. 17. With −2-dBm input power, this rectifier
probes with the input signal provided by an Agilent E8257D can provide more than 3-V output voltage at 57 and 60 GHz,
signal generator. The input power is measured by an Agilent while the output voltage is near 2 V at 64 GHz. A comparison
E4419B power meter through a directional coupler (Agilent of the measured outputs to the proposed mathematical model is
83701E). The optimal load current for the rectifier efficiency also shown in Fig. 17. From this comparison, the mathematical
is accurately controlled by the Agilent E5270B precision modeling’s effectiveness in this article is also verified. With
measurement mainframe. The S-parameters of this rectifier are the input power increased, the forward-biasing current of
measured with the Agilent N5247A PNX-X network analyzer. the parasitic diode DBS results in a larger output voltage.
As shown in Fig. 16, the measured small-signal input matching Fig. 18 summarized this rectifier’s measured sensitivity for
S11 of the rectifier is −11.6 dB at 57 GHz and less than 1-V output voltage over 56–67 GHz, covering the whole
−7 dB from 48 to 66 GHz. Simulation results also predict 60-GHz ISM band. The rectifier achieves a peak sensitivity of
that the center frequency of S11 is at 57 GHz. To explore −7.1 dBm at 57 GHz. Over the entire 60-GHz ISM band, this
the output dc voltage versus input RF power characteristic of mm-wave rectifier can provide more than 1-V output voltage
this rectifier, different input powers from −15 to −2 dBm with an input power of −4.5 dBm. This sensitivity corre-
have been fed to this rectifier. The measurement results are sponds to a 1.5-m power transfer requirement at 57 GHz and
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FANG et al.: ANALYSIS OF mm-WAVE MULTI-STAGE RECTIFIER AND IMPLEMENTATION 9

Fig. 19. Normalized leakage current and the approximated sinusoidal leakage
current with Va = 350 mV and Vbst = 50 mV.

Fig. 17. Measured characteristic of the dc output voltage versus input RF

power and comparison to the mathematical model in this work.
attractive solution for their unique advantage of maintenance-
free usage. However, the sensitivity of the rectifier is the
limiting factor for the wireless power transfer distance. In a
high sensitivity situation, the transistor works below the
threshold voltage. This article presents a mathematical model
and analysis of a multi-stage mm-wave rectifier in the weak
inversion region. The intrinsic threshold voltage modulation
can improve the sensitivity of the multi-stage rectifier. This
work achieves −7.1-dBm input sensitivity at 57 GHz with
1-V dc output voltage. Over the entire 60-GHz ISM band,
this mm-wave rectifier provides more than 1-V output voltage
with an input power at −4.5 dBm. This sensitivity corresponds
to a 1.5-m power transfer requirement at 57 GHz and a
1-m wireless power transfer distance requirement over the
entire 60-GHz ISM band. Compared to other works, the
Fig. 18. Measured characteristic of rectifier sensitivity for 1-V dc output
proposed rectifier achieves better sensitivity while maintaining
voltage with input RF signal frequency. a compact size, suitable for the mm-wave wireless powered
transponder in a middle-distance application.

a 1-m wireless power transfer distance requirement over the A PPENDIX

entire 60-GHz ISM band. I NPUT AND O UTPUT C HARGE A PPROXIMATION
Table I shows the performance summary and a compar-
By solving (11) and (12), the input charge contributed by
ison of the proposed eight-stage mm-wave rectifier with
the subthreshold current Q d1 can be expressed as
bulk-drain connection to other state-of-the-art mm-wave rec- 
tifiers in silicon-based technologies. A sensitivity Figure of (1 + k)(Va − Vbst )
Merit (sFoM) is defined in (35) for comparing with other Q d1 = Is1 erf
nv t
mm-wave rectifiers in terms of sensitivity. In (35), Freq is 
the rectifier working frequency, Vout is the measured output (1 + k − n)(Va − Vbst )
sensitivity voltage, and Pin is the input power according to − Is2 erf . (A1)
nv t
the sensitivity voltage. This work achieves a sensitivity FoM
of 42.22 dB Assuming that (Va − Vbst ) > nv t and 1 + k − n > 1, the inputs
of both the erf function are greater than 1, so their outputs can
sFoM = 20 log(Freq [GHz]) + 20 log(Vout [V ]) − Pin [dBm]. be approximated as 1. Therefore, Q d1 can be further simplified
(35) with (13) and (14)
  

Is0 2πnv t (1 + k)(Va − Vbst )
V. C ONCLUSION Q d1 = exp
ω Va nv t
In an mm-wave wireless communication network, the IoT   
1 1 Va − Vbst
transponder function at mm-wave frequencies has the advan- × √ −√ exp − .
1+k 1+k−n vt
tage of potential massive deployment combined with cloud
(A2)
computing and AI technology. In these scenarios, low cost
and small size are crucial requirements for the transponder. By neglecting the much smaller term exp(−(Va − Vbst )/v t ),
IoT transponders with wireless power functions would be an Q d1 is finally simplified as (21). This approximation method
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

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Jun. 2021. include RFIC and mm-wave IC in CMOS technology.
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Vth-cancellation and power regulation functions for UHF RFIDs,” in preneurship Competition Award in 2021 and the China National Scholarship
Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 119–122. in 2020.
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FANG et al.: ANALYSIS OF mm-WAVE MULTI-STAGE RECTIFIER AND IMPLEMENTATION 11

Wei Hong (Fellow, IEEE) received the B.S. degree Hao Gao (Member, IEEE) received the B.Eng.
from the University of Information Engineering, degree from Southeast University, Nanjing, China,
Zhengzhou, China, in 1982, and the M.S. and Ph.D. in 2006, the M.Sc. degree in electrical engineering
degrees in radio engineering from Southeast Univer- from the ELCA-Group, Delft University of Tech-
sity, Nanjing, China, in 1985 and 1988, respectively. nology, Delft, The Netherlands, in 2008, and the
Since 1988, he has been with the State Key Lab- Ph.D. degree from the Eindhoven University of
oratory of Millimeter Waves, Southeast University, Technology, Eindhoven, The Netherlands, in 2015.
where he has been serving as the Director since In 2007, he was with Catena Microelectronics
2003 and is currently a Professor with the School of (now NXP), Delft. In 2008, he was with Philips
Information Science and Engineering. In 1993 and Research, Eindhoven. In 2012, he was the Marie
from 1995 to 1998, he was a short-term Visiting Skłodowska-Curie European Fellowship with the
Scholar with the University of California at Berkeley, Berkeley, CA, USA, and Catena Wireless Electronics Group, NXP, Stockholm, Sweden. In 2014,
the University of California at Santa Cruz, Santa Cruz, CA, USA. He has been he was ranked as a Staff Engineer at MediaTek, U.K. In 2014, he joined
engaged in numerical methods for electromagnetic problems, millimeter-wave the ELCA-Group, Delft University of Technology, as a Research Scientist.
theory and technology, antennas, RF technology for wireless communications, In 2016, he took a faculty position at the Electrical Engineering Department,
and so on. He has authored or coauthored more than 300 technical publications Eindhoven University of Technology, where he is currently a member of
and two books. the University Central Ethics Committee Board and the International Student
Dr. Hong was an elected IEEE MTT-S AdCom Member from 2014 to 2016. Selection Committee. He has been a Senior Principal Scientist and a Group
He is also a Fellow of the Chinese Institute of Electronics (CIE), the Leader, and among Research Unit Heads at Silicon Austria Labs, the Austria
Vice-President of the CIE Microwave Society and Antenna Society, and the national laboratory, Linz, Austria, since 2019, with a joint professorship.
Chair of the IEEE MTT-S/AP-S/EMC-S Joint Nanjing Chapter. He was twice He did consultant for industries for years, including NXP, The Netherlands,
awarded the National Natural Prizes, thrice awarded the first-class Science and Infineon, Austria. He is also an International Academic Advisor for OPPO
and Technology Progress Prizes issued by the Ministry of Education of Mobile, Germany. He has authored or coauthored over 120 papers in scientific
China and Jiangsu Province Government, and so on. He also received the and technical journals and conference proceedings. He has coauthored several
Foundations for China Distinguished Young Investigators and for “Innovation books, including Batteryless mm-Wave Wireless Sensors (Springer, 2018).
Group” issued by NSF of China. He has served as an Associate Editor He holds several U.S. and China patents.
for the IEEE T RANSACTIONS ON M ICROWAVE T HEORY AND T ECHNIQUES Dr. Gao was a recipient of the Philips Semiconductor Scholarship, Delft,
from 2007 to 2010 and one of the guest editors for the 5G special issue of in 2006. He was also a recipient of the IMS and ISCAS grants. He was
IEEE T RANSACTIONS ON A NTENNAS AND P ROPAGATION in 2017. also a recipient and a co-recipient of several best paper rewards, including
the IEEE MTT-S Radio Wireless Week Award, the International Conference
on Information and Communications Signal Processing Award, the IEEE
MTT-S International Wireless Symposium Award, and the IEEE IMS Student
Design Competition Award. He was also a co-recipient of the 2015 ISSCC
Distinguished Technical Paper Award, the CATRENE Innovation Award with
the EAST Project, and others. He has served as the TPC Co-Chair of the IEEE
International Symposium on Radio-Frequency Integration Technology (RFIT).
He is also the TPC Co-Chair of the IEEE Radio Frequency Integrated Circuits
Symposium (RFIC), the IEEE International Solid-State Circuits Conference,
Student Research Preview (ISSCC SRP), and others. He is also an Associate
Editor of the journal Wireless Power Transfer (Cambridge).