2025 Spring EE303 Digital System

Lecture 12
Derivation of State Graphs and Tables

Youngjoo Lee | Associate Professor

School of Electrical Engineering
KAIST, Korea
Learning Objectives
Given a problem statement for the design of a Mealy or Moore
sequential circuit, find the corresponding state graph and table.

Explain the significance of each state in your graph or table in

terms of the input sequences required to reach that state.

Check your state graph using appropriate input sequences.

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Design of a Sequence Detector
Detecting sequence?
✓ Generate the detection flag (output) for the pre-defined input patterns
✓ Example:
- Make the output Z = 1 for any input sequence ending with 101

- We know that the sequential circuits should be considered, but how many FFs?
- First, we allocate the circuit states as S0, S1, …, and later assign FF states
- Need to construct the state graph first, starting from the initial state S0

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Design of a Sequence Detector
Mealy machine? Moore machine?

✓ Need to check the input/output timing à Mealy machine in this case

✓ From S0 (initial state), X = 0? X = 1?
- Need to define the next state (S1) to identify the starting point of 101 sequence
✓ From S1, X = 0? X = 1?
- Move to the new state (S2) or stay to denote the starting point again
✓ From S2, X = 0? X = 1?
- Now we can detect the input sequence 101 J
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Design of a Sequence Detector
Incremental construction of a state graph
✓ First check the desired detecting path (incomplete)
✓ Then, fill the rest edges for all the possible inputs (complete)

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Design of a Sequence Detector
Converting a state graph to a state table
✓ Now, we are ready to design the target sequential circuit with two FFs

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Design of a Sequence Detector
Find the corresponding transition table (D flip-flop case)

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Design of a Sequence Detector
Find the corresponding transition table (D flip-flop case)

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Design of a Sequence Detector
Final design of a sequence detector

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Design of a Sequence Detector
Moore machine version?
✓ Possible, but the output timing is now shifted by one cycle
✓ Incremental state allocations to detect 101 sequence:
- Need one more state compared with the Mealy machine case

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Design of a Sequence Detector
State table and transition table
✓ Now easy to design the FF-based circuit (still need two FFs)

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Design of a Sequence Detector
Sliding window sequence detector
✓ How we define the detecting cases?

✓ Of course, more options can be pre-defined

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More Complex Design Problems
Detecting two input sequences ending in either 010 or 1001
✓ Need to understand this requirement from the following input example:

- Point a: The input ends in 010 - Point d: The input ends in 010
- Point b: The input ends in 010 - Point e: The input ends in 010
- Point c: The input ends in 1001 - Point f: The input ends in 1001

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More Complex Design Problems
Starting from the initial state
✓ Design a state graph for detecting 010 sequence first

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More Complex Design Problems
Now, construct the part of the state graph for the 1001 sequence
✓ S4: Receiving 1
from the initial state

✓ S3: Now representing

the sequence ends
in 10 (not 010)

✓ S5: Receiving the sequence

ends in 100

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More Complex Design Problems
Finally, make a complete graph
✓ Check the original input sequence for validating this graph

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More Complex Design Problems
Moore machine example
✓ Output Z becomes 1 if the total number of 1’s received is odd and at least two
consecutive 0’s has been received

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More Complex Design Problems
Start with the Moore state graph making the output be 1
✓ At this time, assume we only receive consecutive 1’s

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More Complex Design Problems
Start with the Moore state graph making the output be 1
✓ When we accept two consecutive 0’s, the output can be 1

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More Complex Design Problems
Make a complete graph

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Guidelines for Construction of State Graphs
Helpful guidelines (not mandatory)
✓ Make some sample input/output sequences to understand the problem
✓ Check the conditions going to the initial state (reset the circuit)
✓ Construct a partial state graph for sequences leading to a nonzero output
✓ Check the sequences (or groups of sequences) that must be remembered
✓ Whenever adding an arrow, check existing states to find the destination
✓ A node should have only one out-going path for each input configuration
✓ Validate your complete graph using the original sequence

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Guidelines for Construction of State Graphs
Example #1 (Mealy machine)
✓ Examine groups of four consecutive inputs
✓ The output Z = 1 when the input sequence 0101 or 1001 occurs
✓ Reset the circuit after every four inputs

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Guidelines for Construction of State Graphs
Example #1 (Mealy machine)

✓ Partial state graph:

Last two inputs should
be 01 for making Z = 1

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Guidelines for Construction of State Graphs
✓ Make the complete version (S5 and S6 are used for the reset condition)

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)
✓ One input sequence (X) generating two output sequences (Z1 and Z2)
✓ Z1 = 1 when the input sequence 100 is completed, provided that the sequence 010
has never occurred
✓ Z2 = 1 when the input sequence 010 is completed

- Note that once a Z2 = 1 has occurred, Z1 = 1 can never occur

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)

✓ Constructing the part of the state graph giving

the correct output for the sequences 100 and 010

✓ How can we remember the output Z2 = 1?

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)
✓ Need to make new states to remember this case (Isolated state transitions)

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)
✓ Complete the partial state graph before Z2 = 1

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)
✓ Partial graph for the 010 loop

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Guidelines for Construction of State Graphs
Example #2 (Mealy machine)
✓ Final complete state graph and table

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Guidelines for Construction of State Graphs
Example #3 (Moore machine)
✓ Two inputs (X1, X2) and one output (Z)

✓ The input sequence X1X2 = 01, 11 causes the output to become 0

✓ The input sequence X1X2 = 10, 11 causes the output to become 1
✓ The input sequence X1X2 = 10, 01 causes the output to change value
✓ The output remains a constant value for the rest cases

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Guidelines for Construction of State Graphs
✓ Need to check the current output and previous inputs to define states
- The input sequence X1X2 = 01, 11 causes the output to become 0
- The input sequence X1X2 = 10, 11 causes the output to become 1
- The input sequence X1X2 = 10, 01 causes the output to change value
- The output remains a constant value for the rest cases

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Guidelines for Construction of State Graphs
✓ Using the state designation, we can set up the state table below
- The input sequence X1X2 = 01, 11 causes the output to become 0
- The input sequence X1X2 = 10, 11 causes the output to become 1
- The input sequence X1X2 = 10, 01 causes the output to change value
- The output remains a constant value for the rest cases

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Guidelines for Construction of State Graphs
Example #3 (Moore machine)
✓ Complete state graph from the table

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Serial Data Code Conversion
More practical case study
✓ Transfer a serial stream of bits
- How to accept the clock signal synchronous to the data stream?

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Serial Data Code Conversion
Various transmission coding options
✓ Non-return-to-zero (NRZ), non-return-to-zero-inverted (NRZI), return-to-zero (RZ),
Manchester code, …(More switching patterns à Easy to recover the clock signal)

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Serial Data Code Conversion
Circuit from NRZ to Manchester
✓ Additional (faster) Clock2

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Serial Data Code Conversion
Conversion circuit from NRZ to Manchester
✓ Two consecutive (same) NRZ inputs for each bit
✓ Mealy type circuit may include output glitches

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Serial Data Code Conversion
Conversion circuit from NRZ to Manchester
✓ Moore machine to remove the glitches but one-cycle latency

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Serial Data Code Conversion
Conversion circuit from NRZ to Manchester
✓ Moore machine to remove the glitches but one-cycle latency

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Alphanumeric State Graph Notation
More convenient way to construct/understand state graphs
✓ Example: Two inputs (F = forward, R = reverse), and three outputs

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Alphanumeric State Graph Notation
Complete version
✓ We have four inputs for each state: F′R′, F′R, FR′, FR
✓ Let F have priority over R

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Incompletely Specified State Tables
Consider the following “practical” cases
✓ Some input sequences may never occur
- Unspecified next states in the table
✓ The output from a sequential circuit is only observed at certain times
- Unspecified outputs in the table

✓ Incompletely specified state table including don’t-care terms

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Incompletely Specified State Tables
Case example #1:
✓ S2 and S5 only accept a 0-input case

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Incompletely Specified State Tables
Case example #2
✓ We only care the output after accepting three serial inputs

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