ISSCC 2016 / SESSION 27 / HYBRID AND NYQUIST DATA CONVERTERS / 27.

27.5 A 4GS/s Time-Interleaved RF ADC in 65nm CMOS In this work, two methods are evaluated to correct for interleaving timing skew
errors, the first being analog trim and the second digital-only post processing.
with 4GHz Input Bandwidth While digital FIR filters are flexible and amenable to advanced CMOS, the power
and die area of digital correction impacts system metrics. If the two methods
Matt Straayer1, Jim Bales2, Dwight Birdsall2, Denis Daly1, achieve equivalent correction of errors, an analog trim is preferred in that it
Phillip Elliott2, Bill Foley1, Roy Mason2, Vikas Singh3, Xuejin Wang2 consumes essentially no power or area. Shown in Fig. 27.5.2 is de-skew trim
circuitry for each of the 8 sampling clock phases, where the load capacitance of
1
Maxim Integrated Products, North Chelmsford, MA, two inverters is modulated by MOS capacitors connected as varactors with a
2
Maxim Integrated Products, Fort Collins, CO, digital control word. Trim resolution of approximately 10fs is chosen based on
3
Maxim Integrated Products, San Jose, CA spurious content requirements, and the 10b tuning range is ±5ps.

The performance and power consumption of high-speed ADCs has advanced such Measured 64kpt FFT spectra with analog and digital timing skew trim methods
that some receiver architectures can directly sample the input without down- are shown in Fig. 27.5.4. For this data, the sampling rate is 2.949GS/s and the
conversion. This work looks to extend the applicability of such high-speed ADCs input frequency is 1.842GHz. A single digital post-processing algorithm is used
by digitizing wireless communications bands up to 4GHz with a high level of to optimize the correction parameters, and in both cases the interleaving error
spectral purity. Fabricated in foundry 65nm CMOS and operating up to 4GS/s with correction is maintained to better than -86dBFS for a -4dBFS input signal. When
power consumption of 2.2W, the reported ADC achieves noise performance of using digital error correction, the analog de-skew control words are reset and
over 60dBFS and linearity performance of 64dBc at 1.842GHz input frequency. held constant. The first 4 harmonic distortion tones are highlighted, showing
At 3.8GHz input frequency, SNR is dominated by aperture jitter of 50fs and two- 66dBc third-order distortion and better than 78dBc for all other distortion tones.
tone IMD3 is >60dBFS. No calibration was used for correcting these harmonic distortion levels, although
existing techniques could be applied [1,2] especially considering that the third-
Any interleaved converter with stringent spectral requirements requires correction order distortion results from the RF buffer, which has a simple architecture and
of interleaving errors such as gain, offset, and timing skew mismatch. There are smooth nonlinearity.
several established methods to correct these interleaving errors as long as the
errors are described by simple parameters. However, frequency or signal- Figure 27.5.5 plots measured performance of the RF ADC vs. frequency, sampling
dependent errors such as limited bandwidth or kickback into complex impedances rate, and input amplitude at Tj=70C. First, in the upper left, the return loss and
can contribute complex error terms that are more challenging to correct in a transfer characteristic of the ADC are shown to have very wide bandwidth of 4GHz.
wideband time-interleaved ADC. Therefore, achieving a very high front-end The transfer characteristic includes losses from the input transformer, printed
sampling bandwidth without channel-to-channel coupling is prioritized. To this circuit board, and package, the sum of which dominate the amplitude rolloff vs.
end, as shown in Fig. 27.5.1, dual RF buffers are implemented instead of a single frequency. In the upper right, IMD3 performance of the ADC is plotted for 3
buffer. While introducing additional offset and potential gain error, the choice of different input frequencies, with >60dBFS IMD3 at near full-scale and >70dBFS
a dual buffer limits the capacitive loading on the buffer output and also allows for IMD3 at 3.8GHz in a backoff condition of -12dBFS. In the lower left, SNR of over
a higher degree of electrical symmetry in the signal routing layout. The schematic 60dBFS with an input frequency of 1842MHz is achieved at 4GS/s. Performance
for the unity-gain buffer is shown in Fig. 27.5.2, where the input terminates with degradation of 1dB is observed at 5GS/s, which indicates there is robust design
on-chip differential 50Ω resistors. The simplicity of the design as well as the margin in timing and bandwidth. Finally, SNR vs. amplitude is plotted for 3
optimized layout are both key to meeting the high bandwidth and linearity targets. different input frequencies. The degradation in SNR at large amplitudes is
consistent with rms aperture jitter of 50fs, so this indicates that analog de-skew
Each of the RF buffers connects to 4 capacitive sampling circuits, where only one trim is a viable option even for low-jitter designs.
of the capacitors is loading the buffer at a time. Having 2 dedicated clock periods
for sampling each capacitor is a direct result of the dual-buffer scheme, and At 4GS/s the ADC draws 1111mA from a 1.0V and 613mA from a 1.8V supply for
compared to a single buffer this offers both significantly relaxed sampling clock a total power consumption of 2214mW. Of this power, 66mW is in the clock
generation as well as a much higher degree of isolation to sample-to-sample generation, 207mW is consumed in the RF buffers from 1.8V, 384mW is for the
kickback. After sampling, each capacitor is placed in feedback around a hold amplifiers, 110mW is for bias generation and supply of internally regulated
continuous-time hold amplifier (as shown in the lower right of Fig. 27.5.1) that power, and 1447mW is in the sub-ADC considering both rails. Note that for
has 5 full clock periods to fully settle the sub-ADC input voltages, leaving one simplicity and cycle time, the sub-ADC stages are not scaled, which does
clock period to reset the capacitor before connecting again to the input. Shown contribute significant power to the design.
in Fig. 27.5.2, dummy sampling switches are connected to the capacitors in a
cross-coupled manner, which cancels charge injection in the off (hold) state due Comparison with two recent high-resolution multi-GHz ADC is outlined in Fig.
to CDS feedthrough. The floorplan and orientation of the sampling and sub-ADC 27.5.6. With an input signal of -4dBFS and a sampling rate of 4GS/s, the proposed
circuits was selected to randomize mismatch and coupling effects, and extensive design achieves a Schreier FOM of 145.1dB. While [1] has higher SFDR, it
extractions and simulations were conducted on both the signal and clock achieves this result only to 1GHz bandwidth in a high-performance bipolar process
interconnects to minimize cross-coupling and ensure signal integrity. using harmonic-distortion calibration and over 20W power consumption.
Reference [3] is lower power with similar full-scale noise performance, but does
Nonlinearity errors and thermal noise in the sub-ADCs were budgeted to be not include an input buffer, which is critical when interfacing with off-chip
significantly lower than other sources of ADC error, which drive the design of the components. In addition, aperture jitter of [3] is significantly higher, bandwidth
sub-ADC in terms of power and speed. The 250MS/s sub-ADC comprises 4 MDAC is limited to 2.5GHz, and high-order distortion terms are more prevalent as noted
stages and a hybrid 6b FLASH/SAR quantizer, where the MDAC stages each have by the THD of only 57dB. Other multi-GS/s ADC designs not referenced in the
13 quantization levels and a gain of 4, resulting in a residue range of nominally table are found to have either substantially different noise, linearity, or input
±VREF/3 as shown in the residue plot of Fig. 27.5.3. VREF for this ADC is 0.7V, bandwidth performance.
resulting in 1.4VPP fullscale range. 5-level dither [-VREF/12, -VREF/24, 0 +VREF/24,
+VREF/12] is introduced to both the MDAC and bit-decision comparators (BDC) of A die photo of the ADC is shown in Fig. 27.5.7. The overall die is 5.2×5.6mm2,
sub-ADC stages 1 and 2 with probability functions that result in uniform statistics with the ADC active area occupying 3.8×2.9mm2.
that smooth the small-signal linearity performance of the ADC. For the MDAC, the
dither voltage is sampled onto the feedback capacitors during input sampling, References:
and in the BDC a dedicated sampling capacitor is added for sampling the dither. [1] B. Setterberg et al., “A 14b 2.5GS/s 8-Way Interleaved Pipelined ADC with
Since the dither voltage is much smaller than VREF, for both the MDAC and BDC Background Calibration and Digital Dynamic Linearity Correction,” ISSCC Dig.
the dither capacitor size is a fraction of the input and reference capacitors, and Tech. Papers, pp. 466-467, Feb. 2013.
the dither voltage is correspondingly larger. In the case of the MDAC, this allows [2] R. Vansebrouck et al., “Digital Distortion Compensation for Wideband Direct
for use of the existing feedback capacitors, and in the BDC this minimizes the Digitization RF Receiver,” Proc. IEEE NEWCAS, June 2015
noise and offset penalty of the additional capacitor. The effective residue plot for [3] J. Wu et al., “A 5.4GS/s 12b 500mW Pipeline ADC in 28nm CMOS,” Symp.
the sub-ADC stages with dither is also shown in Fig. 27.5.3. VLSI Circuits Dig. Tech. Papers, pp. 92–93, 2013.

Authorized licensed use limited to: ULAKBIM UASL - Yeditepe Universitesi. Downloaded on October 24,2024 at 07:18:34 UTC from IEEE Xplore. Restrictions apply.
464 • 2016 IEEE International Solid-State Circuits Conference 978-1-4673-9467-3/16/$31.00 ©2016 IEEE
 ISSCC 2016 / February 3, 2016 / 3:15 PM

Figure 27.5.2: Front-end circuit schematic of the input buffer and sampling
Figure 27.5.1: Simplified block diagram of the 4GS/s ADC with front-end timing. network including analog de-skew timing circuit.

Figure 27.5.3: Details of the sub-ADC illustrating how dither is added for the Figure 27.5.4: Measured FFT output spectra with analog (top) and digital
first two stages. (bottom) timing skew correction.

27
Figure 27.5.5: Measured performance characteristics of the RF ADC. Figure 27.5.6: Performance summary and comparison.

Authorized licensed use limited to: ULAKBIM UASL - Yeditepe Universitesi. Downloaded on October 24,2024 at 07:18:34 UTC from IEEE Xplore. Restrictions apply.
DIGEST OF TECHNICAL PAPERS • 465
 ISSCC 2016 PAPER CONTINUATIONS

Figure 27.5.7: Die photograph.

Authorized licensed use limited to: ULAKBIM UASL - Yeditepe Universitesi. Downloaded on October 24,2024 at 07:18:34 UTC from IEEE Xplore. Restrictions apply.
• 2016 IEEE International Solid-State Circuits Conference 978-1-4673-9467-3/16/$31.00 ©2016 IEEE