BJT Amplifiers, Small-Signal Operation and Models :

(a) DC equivalent circuit (b) AC equivalent circuit

 Small-Signal Equivalent Circuit Models

(a) (b)

For small-signal operation of BJT. Two different versions of simplified hybrid-Π model
(a) represents the BJT as a voltage-controlled current source ( a transconductance amplifier)
(b) represents the BJT as a current-controlled current source (a current amplifier).
Two slightly different versions of what is
known as the T model of the BJT. The
circuit in (a) is a voltage-controlled
current source representation and that in
(b) is a current-controlled current source
representation. These models explicitly
show the emitter resistance re rather than
the base resistance Πr hybrid-π model.
featured in the
(a) (b)
Common emitter Amplifier: DC analysis to find IB , IC , IE and VB,VC and VE

IC
IB VC
VB
β

IE
VE

Lets assume the BJT is operating in Active Mode. Thus, IC= α.IE , IC= β.IB and α=β/(β+1)
Since IE = I mA ; IB = IE / (β+1) mA ; VB = 0 - IB.RB ; VE = VB - 0.7 ;
Now IC= α.IE = (β.IE) / (β+1) ; VC = VCC - IC.RC and if CBJ remains RB then assumption is OK

Exercise-5: Find the operating point if VCC=VEE=10V, RC=8 kΩ, RB=100 kΩ, I=1mA & β=100
Solution: Q or operating point is, IC=0.99 mA ; VCE=0.3 v (as VB= -1v, VC = 2v, VE = -1.7v)
Common emitter Amplifier: AC analysis to find Gain, Input & output Impedances

Remember,
r 0=|VA|/IC
gm=IC/VT
rπ=VT/IB

Exercise-6: Find Rin ,Rout ,Av & Gv; if Rsig=RL=5kΩ, RB=100k, RC=8k; IC=1mA, IB=0.01mA, VA=100V, VT=25mV

Solution: Ri=2.43 kΩ; Rout=7.4 kΩ, Av=-119 V/V, Gv=-39 V/V (as rπ=2.5K, gm=40 mA/V, r0=100k)
Review of CE amp:
- S/C DC voltage source
- O/C DC current source

Find model
parameters
(rπ, re, gm)

DC analysis: O/C capacitors AC analysis: S/C capacitors

& find IB, IC, IE, VB, VC, VE & find Î Rin, Rout, AV, Ai

Exercises-7:
 Exercises-8:

Common emitter Amplifier with Re (emitter resistor): Controlled voltage amp

DC analysis IC= α.IE ,

IC IC= β.IB
α=β/(β+1)
and
β
IB gm=IC/VT;
IE re=VT/IE ;

Exercise-9: Find the operating point if VCC=VEE=10V, RC=8 kΩ, RB=100 kΩ, I=1mA & β=100
Solution: operating point, IC=0.99 mA ; VCE=3.7 v (as IE=1mA ; VB= -1v, VC = 2v, VE = -1.7v)
AC analysis

Remember, re=VT/IE & Resistance reflection ruleÎ Rbase≈(β+1)R emitter

; Remember, gm=IC/VT

(as ro of T-model is neglected to ease solution process)

Common Emitter (CE) with Emitter Resistance (Re ): AC analysis (cont’d…)

introduce a negative feedback

Exercise-10: if IE=1mA, IC=0.99mA, Re=225Ω, RB=100kΩ, RC=8kΩ, Rsig=RL=5kΩ, β=100, VT=25mV,

Neglect ro to FIND Rin , Rout , Av,, Gv Î Sol: Ri=20.16 kΩ; Rout=8 kΩ, Av= -12.18V/V, Gv=-9.76v/v
5.7.5:Common Base (CB) Amplifier: Unity-gain-current-amplifier or Current-buffer

DC analysis

Lets assume Active Mode.

VB = 0 ; VE = VB - 0.7 ;
IE = I mA ; IB= IE / (β+1) mA;
IC= α.IE = (β.IE) / (β+1) ;
VC = VCC - IC.RC and
if CBJ remains RB
then assumption is OK

AC analysis: For the AC equivalent circuit given in the figure in the next page,
Common Base (CB) Amplifier: Low Zin makes it not good voltage amplifier
AC analysis
5.7.5:Common Collector (CC) Amplifier: Emitter Follower
DC analysis Assume Active Mode.
IE=I mA; IB=IE/(β+1)mA
VB =0–(IB)(RB) ;
VE=VB - 0.7 ;
IC=α.IE = (β.IE)/(β+1) ;
VC = VCC
if CBJ remains RB
then assumption is OK

AC analysis
 AC analysis

Emitter to Base:

Base to Emitter
Exercises-12
Design Criteria of a BJT Amplifier (review):

Figures from text book

CHAPTER 3

FIELD EFFECT TRANSISTOR (FET)

 3.1. Introduction

Field Effect Transistor (FET) is a three terminal semiconductor device. The three
terminals are gate (G), source (S) and D drain (D).
It is unipolar transistor i.e. depends only on one type of charge carrier, either electron or

hole. The current is controlled by the applied electric field hence, it is a voltage
controlled device.
FET is simple to fabricate and occupies less space on a chip than a BJT.

About 100,000 FETs can be fabricated in a single chip. This makes them useful in VLSI

(very large scale integrate) system.

It has high input Impedances and Low output Impedance so they are used as buffers at

the front end of voltage and other measuring devices.

There are two types of FET where each can be either n-channel or p-channel
 i. The JFET (Junction Field Effect Transistor) and
 ii. MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
 Difference between BJT and FET

BJT FET
• Current controlled device • Voltage controlled device
• Bipolar (current conduction due to • Unipolar (current conduction due
flow of holes and electrons) to flow of majority charge carriers)
• Has Low input impedance as • Has High input impedance
• Ac voltage gain is high • Ac voltage gain is low
• Less temperature stable • More temperature stable
• Larger in size • Smaller in size

3
 3.2. Junction Field Effect Transistor (JFET)

Junction field effect transistor (JFET) is a type FET that operates with a reverse biased p-n
junction to control current in a channel.
Depending on the structure, JFET fall in two categories: n-channel and p-channel JFET

As an illustration an N-channel is fabricated by diffusing 2-P type junctions on

opposite sides of N-type semi-conductor material as shown in fig (a).

Fig1 (a). N-channel JFET construction and (b). p-channel JFET construction
circuit symbol and circuit symbol
 3.2. Junction Field Effect Transistor (JFET)

The n- channel JFET consists of a bar of n-type semiconductor with

two islands of p- type material embedded in the sides.
The drain and source terminals are made by ohmic contacts at the end

of p-type of semiconductor bar.

Majority charge carrier i.e. electrons can be cause to flow along length

of bar by means of a voltage applied between the source and drain .

The electrons leave from drain the third terminal, known as the gate is

formed by electrically connecting the two p-type regions.

The circuit symbol of p- channel JFET is similar to that of an n-channel

JFET except that the gate arrow points outward as shown in below.
 Operation of JFET

The gates are always reverse biased and therefore the gate current Ig is practically zero.
The source terminal is always connected to that end of the drain supply which provides

the necessary charge carriers.

As an example an N-channel JEET is discussed when either VGS or VDS or both are

changed.
There are three basic operating conditions forp g a JFET

VGS= 0, VDS increasing to some positive value

VGS < 0, VDS at some positive value

Voltage-controlled resistor

7
 a) When VGS=0 and VDS is increased from zero.

 Electrons which are the majority charge carriers flow through the channel
from the source to the drain. Due to this flow there is a uniform voltage drop
across the channel resistance.
 This voltage drop acts as reverse bias at the gate.

 The depletion region between p-gate and n-channel increases as

electrons from n channel combine with holes from p-gate.
 Increasing the depletion region, decreases the size of the n-channel which
increases the resistance of the n-channel.
 Even though the n-channel resistance is increasing, the current (ID) from
source to drain through the n- channel is increasing. This is because VDS is
increasing.
 The gate is more negative with respect to those points which are nearer to
the drain than those to source, therefore the depletion regions penetrates
more deeply into the channel at points which lie closer to the drain than source.
𝑉𝐷𝑆
𝐼𝐷 = ,
𝑅𝐷𝑆

8
 a) When VGS=0 and VDS is increased from zero.

As VDS is increased, the current ID increases up to a

maximum value IDSS (saturation current). At this stage
ID=IDSS which is constant.
Under this condition the channel cross-sectional

area becomes minimum and the channel is said to be

pinched off and the corresponding value of VDS is
called pinch off voltage (VP).
 In case VDS is increased beyond this point, VP,
ID does not increase. It remains constant until the
JFET breaks down and ID increases to an excessive
value.
9
 At the pinch-off point:
Any further increase in VGS does not produce any
increase in ID. VGS at pinch-off is denoted as VP
ID is at saturation or maximum. It is referred to as IDSS.

The ohmic value of the channel is maximum.

10
 b) When VGS is -ve and VDS is
increased.

 VGS is made more negative, increasing the gate reverse VDD

bias and therefore increasing the thickness of depletion.

The JFET experiences pinch-off at a lower voltage (VP).
ID decreases (ID < IDSS) even though VDS is increased.

Eventually ID reaches 0 A. VGS at this point is called VP or

VGS(off).
As VGS is increased to the -ve, a point is reached when
the 2 depletion regions touch one another and the
channel is cut off. This value of VGS that cuts the channel
off is called VGS(off).
As VGS is made more -ve, values of VP as well as
breakdown voltage are decreased.
A P-channel JFET operates exactly in the same
manner as N-channel except that channel carriers are
holes, and the polarities of both VDD and VGS are
reversed.
11
c). Voltage-Controlled Resistor

12
 Operation of p Channel JFETS

The p-channel JFET behaves the same as the


n-channel JFET, except the voltage polarities
and current directions are reversed

13
P-Channel JFET Characteristics

14
 N-Channel JFET Transfer Characteristics

The transfer characteristic of input-to-output is not

as straightforward in a JFET as it is in a BJT.
In a BJT, β indicates the relationship between IB

(input) and IC (output).

In a JFET, the relationship of VGS (input) and ID

(output) is a little more complicated:

15
 BIASING OF FETS JFET (DC Biasing)

 It can be biased using either;

Separate power source VGG.
Source biasing.

Self biasing.

Voltage divider bias.

16
17
 Self biasing

• VGS bias is obtained from the flow of drain current ID through RS and VS=ISRS and
VGS=-ISRS.
• The gate is kept at this much -ve potential (voltage) with respect to the ground.
• Addition of RG does not upset this d.c bias because no gate current flows through it apart
from the gate leakage current.
• Without RG the gate would be floating which would collect some charge and cut off the JFET.
• Also RG serves the purpose of avoiding short circuiting of the a.c input voltage Vin.

18
19
Example Find the values of VDS in the circuit below if ID=4mA, VDD=12V, RD=1.5K and RS=500.

𝑉𝐷 = 12 − 4 × 10−3 × 1.5 × 103 = 6𝑉

𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆
VDS= 6 − 2 = 4𝑉

20
21
 MOSFETs
MOSFETs have characteristics similar to JFETs and additional
characteristics that make them very useful
There are two types of MOSFETs:

• Depletion -Type
Enhancement- Type

23
Depletion
Depletion-
p -Type
yp MOSFET Construction
The Drain (D) and Source (S) connect
to the to n-doped
p regions.
g These n-
doped regions are connected via an n-
channel. This n-channel is connected to
the Gate (G) via a thin insulating layer
of SiO2.

The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called Substrate
(SS).

24
 Basic MOSFET Operation

A depletion
depletion-type
type MOSFET can operate in two modes:

• Depletion mode
• Enhancement mode

25
 D-Type MOSFET in Depletion Mode

Depletion Mode

Thee characteristics
c c e s cs aree similar
s
to a JFET.

• When VGS = 0 V
Wh V, ID = IDSS
• When VGS < 0 V, ID < IDSS
• The formula used to plot the transfer
curve still applies:
2
⎛ V ⎞
I D = I DSS ⎜⎜ 1 − GS ⎟⎟
⎝ VP ⎠

26
D-Type MOSFET in Enhancement Mode
Enhancement Mode

• VGS > 0 V
• ID increases above IDSS
• The formula used to plot
the transfer curve still
applies:
2
⎛ V ⎞
I D = I DSS ⎜⎜ 1 − GS ⎟⎟
⎝ VP ⎠

Note that VGS is now a positive polarity

27
p-Channel D
D--Type
yp MOSFET

28
D-Type
yp MOSFET Symbols
y

29
 E-Type MOSFET Construction
• The Drain (D) and Source (S) connect
t th
to the tto n-doped
d d regions.
i Th
These n-
doped regions are connected via an n-
channel

• The Gate (G) connects to the p-doped

substrate via a thin insulating layer of
SiO2

• There is no channel

• The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called the
Substrate (SS)

Electronic Devices and Circuit Theory, 10/e 32

Robert L. Boylestad and Louis Nashelsky
Basic Operation
p of the E-
E-Type
yp MOSFET

The enhancement-
enhancement-type MOSFET operates only in the enhancement mode.
mode

• VGS is always positive

• As VGS increases, ID
increases

• As VGS is kept constant

and VDS is increased,
th ID saturates
then t t (IDSS)
and the saturation level,
VDSsat is reached

Electronic Devices and Circuit Theory, 10/e 33

Robert L. Boylestad and Louis Nashelsky
 E-Type MOSFET Transfer Curve

T d
To determine
t i ID given
i VGS:
I D = k ( VGS − VT ) 2

Where:
VT = threshold voltage
or voltage at which the
MOSFET turns on

kk, a constant, can be

b ddetermined
i db by using
i VDSsat can be
b calculated
l l d by:b
values at a specific point and the formula:
VDsat = VGS − VT
I D(ON)
k=
(VGS(ON) − VT) 2

Electronic Devices and Circuit Theory, 10/e 34

Robert L. Boylestad and Louis Nashelsky
 p-Channel E-Type
p yp MOSFETs

The p-channel enhancement-

enhancement-type MOSFET is similar to the n-
channel, except that the voltage polarities and current directions
are reversed
reversed.

35
MOSFET Symbols

36
Summary Table

42