CIRCUITE INTEGRATE LOGICE DIGITAL INTEGRATED CIRCUITS www. datasheetcatalog.com 1990Acest catalog a fost elaborat in endrul Intreprinderii de Piese Radio si gtupa A.C.LT. de: ing. D. CRACEA — coordonato: ing. M. CONSTANTINESCU ing. S. PUCHIANU ing. D. RAIU ing. R. RAPEANU riniconduetori—Baneasa Au eolaborat: M. COSASU M. DUMITRESCU E. DUMITRU M. GEORGESCU I. STANCU ing. V. ULIERU Informafiile din acest CATALOG au fost verificate cu atenfie si se pot considera reale gi utile. Cu toate acestea, nu se asuma nici © responsabilitate pentru eventualele omisiuni sau inadvertente. In acelasi timp, IPRS. Baneasa nu rispunde de interpretarea gresit’ a informafiilor continute in acest CATALOG. Specificatitle componentelor electronice pro- duse de TP.R.S. sint supuse modificarilor. De asemenea, producatorul are posibilitatea, la cererea beneficiarilor, si livreze componentele sale m&surate si in alte condifii electrice sau mecano-climatice. www. datasheetcatalog.com ‘The informations of this CATALOGUE has ‘been carefully checked and is belived to be true and reliable. However, no responsability is assumed for possible omissions or inac- curacies, In the same time, I.P.R.S.-Bineasa has no responsability in case of wrong inter- pretation of informations contained in this CATALOGUE. Specifications of _ electronic components manufactured by I.P.R.S. are subject to change. Also, the manufacturer has possibility, at custom demand, to deliver his components tested at any other electrical and mechanical conditions. INTREPRINDEREA POLIGRAFICA CLUJ, Municipiul Cluj-Napoca e-da nr. 2/1988 BlINDEX ALFANUMERIC......-.+-+-+-++-+2---2 ALPHANUMERICAL INDEX Microprocesor bipolar seria 14000. 2 2... 2. ee ee ee Bipolar mieroproeessor 14000 series @ BP 14500; PROCESOR DE 1 BIT... BPC 14500 1 BIT PROCESSOR @ BP 14104; NUMARATOR DE PROGRAM DE 4 BITI, EXPANDABIL BPC 14104 4-BIT EXPANDABLE PROGRAM COUNTER @ BP 14113; DEMULTIPLEXOR 1:8 CU MEMORIE......--- BPC 14113 i TO 8 DEMULTIPLEXER WITH MEMORIE: @ oP 1415 MULTIPLEXOR 8-1 CU [ESIRE IN 3 STARI ....- BPC 1415 8 TO 1 TRI STATE MULTIPLEXER aaa Cireuite integrate TTL. ©. 2 2. ee ee TTL integrated eireuits @ CDB 400 E: 4 PORTI “SI-NU" CU 2 INTRARI. 2... 2.2 ee CDB 400 EM; QUADRUPLE 2INPUT NAND GATES CII 30 @ CDB 402 E; 4 PORTI “SAU-NU” CU 2 INTRART. 2... - 2 ee CDB 402 EM QUADRUPLE 2-INPUT NOR GATES e@ CDB 403 -—E 4 PORTI “SI-NU" CU 2 INTRARI $I IESIRI CU CDB 403 ED COLECTOR IN GOL (5,5 V) QUADRUPLE 2-INPUT NA COLLECTOR OUTPUTS @ CDB 404 6 INVERSOAR CDB 404 EM; HEX INVERT! CII 236 e@ CDB 405 E; 6 INVERSOARE CU IESIRI CU COLECTOR IN CDB 406 BM GOL (SV)... ss eee eee ee es HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS @ CDB 406 E; 6 INVERSOARE DE PUTERE CU IESIRI CU COLECTOR CDB 406 EM INGOL (OV)... . eee ee ee ee HEX INVERTERS BUFFERS/DRIVERS WITH OPEN- COLLECTOR HIGH-VOLTAGE OUTPUTS @ CDB 407 E; 6 PORJI DE PUTERE CU IESIRI CU COLECTOR CDB 407 EM IN GOL (30V) ... 1... ee ee ee ee ee ee HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HICH-VOLTAGE OUTPUTS @ CDB 408 E; 4 PORTI “SI” CU 2INTRARI... 2... eee ee ee CDB 408 EM QUADRUPLE 2-INPUT AND GATES @ CDB 409 E; 4 PORTI “SI” CU 2 INTRARI SI IESIRI CU CDB 409 EM COLECTOR IN GOL (55V) . eee ee QUADRUPLE 2INPUT AND GATES WITH OPEN- COLLECTOR OUTPUTS CUPRINS a BANEASA CONTENTS 13 a 37 47 53 cy 67 70 73 76 79CUPRINS www. datasheetcatalog.com CONTENTS wy @ CDE 410 3 PORTI “SI-NU” CU 3 INTRARI CDB 410 TRIPLE 3-INPUT NAND GATES CII 48 @ CDB 413 E; 2 PORJI “SI-NU" TRIGER SCHMITT CU 4INTRARI. . 91 CDE 413 EM DUAL 4-INPUT NAND SCHMITT TRIGGERS @ CDB 416 E; 6 INVERSOARE DE PUTERE CU IFSIRI CU COLECTOR CDB 416 EM INGOL(I5V) 1.2... eee 94 HEX INVERTERS BUFFERS/DRIVERS WITH OPEN- COLLECTOR HIGH-VOLTAGE OUTPUTS @ CDB 417 E; 6 PORJI DE PUTERE CU IESIRI CU COLECTOR IN GOL CD B]417/5 Maas (15 5V) ee ee ee 97 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS @ CDB 420 2 PORTI “SI-NU" CU 4 INTRARI 2.2... coco 100 CDB 420 DUAL 4-INPUT NAND GATES ci 108 @ CDE 430 POARTA “SI-NU” CU BINTRARI 2... ee - 108 CDB 430 8-INPUT NAND GATE ci 33 @ CDE 432 4 PORTI “SAU” CU 2INTRARI 2... eee eee 106 CDE 432 QUADRUPLE 2-INPUT OR CATES @ CDE 437 4 PORJI DE PUTERE “SI-NU” CU 2 INTRARI .... 109 CDB 437 QUADRUPLE 2INPUT NAND BUFFERS @ CDB 438 4 PORJI DE PUTERE“SI-NU” CU 2 INTRARI CDE 438 $I IESIRI CU COLECTOR IN COL (55 V).... 112 QUADRUPLE 2INPUT NAND BUFFERS WITH OPEN- COLLECTOR OUTPUTS @ CDB 440 J - : PORJI DE PUTERE “SI-NU” CU 4 INTRARI .... 115 CDB 440 EM; DUAL 4-INPUT NAND BUFFERS cll 32 @ CDE 442 E; DECODOR BINAR-ZECIMAL . 2... eee ee ee 118 CDB 442 EM BCD-TO-DECIMAL DECODER @ CDB 446 E; DECODOR-DRIVER BCD-7 SEGMENTE CU TESIRI cu CDE 446 EM COLECTOR IN GOL (30 V) . . 123 BCD-TO-SEVEN-SEGMENT DECODER/DRIVER OPEN- COLLECTOR @ CDE 447 E; DECODOR-DRIVER BCD-7 SEGMENTE CU TESIRI CU CDB 447 EM COLECTOR IN GOL (15 V) «1.2... eee 129 BCD-TO-SEVEN-SEGMENT DECODER/DRIVER OPEN- COLLECTOR OUTPUTS @ CDB 450 E; 2 PORJI “SI-SAU-NU” CU 2x2 INTRARI (0 POARTA CDB 450 EM EXPANDABILA) . 136 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES (ONE GATE EXPANDABLE) @ CDB 451 2 PORTJI “SI-SAU-NU” CU 2x2 INTRARI . 2... . 140 CDB 451 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES ci 31 @ CDB 453 PORTI EXPANDABILE “SI-SAU-NU" CU 4x 2INTRARI 143 CDB 453 EXPANDABLE 4-WIDE AND-OR-INVERT GATES @ CDB 454 PORTI “SI-SAU-NU” CU 4x2 INTRARI see eee 147 CDB 454 4-WIDE AND-OR-INVERT GATES cir 46Lo POR: 8. € CUPRINS CONTENTS BBANEASA | www.datasheetcatalog.com— ~ a ~~ CDB 460 EB; 2 PORTJI “EXPANDER” CU 4INTRARI 2.1... D 150 CDB 460 EM DUAL 4-INPUT EXPANDER CDB 472 EB; = BASCULA “J-K MASTER-SLAVE” .. 2.2... 00 154 CDB 472 EM; AND GATED J-K MASTER-SLAVE FL cir 44 WITH PRESET AND CLEAR CDB 473 E; 2 BASCULE “J-K MASTER SLAVE”... . 2... 159 CDB 473 EM; DUAL J-K MASTER-SLAVE FLIP-FLOPS WITH CLEAR cir 85 CDB 474 E; 2 BASCULETIP“D".. 2... 164 CDB 474 EM DUAL D-TYPE EDGE-TRIGGERED FILP-FLOPS WITH PRESET AND CLEAR CDR 475 E; 4 BISTABILI “DE STOCARE” . . . 170 CDB 475 EM 4-BISTABLE LATCHES CDB 476 2 BASCULE “J-K MASTER-SLAVE’ 175 CDB 476 EM DUAL J-K MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR CDB 481 E; MEMORIE CU 16 BIJI.... 2.2.22. ee 181 CDB 481 EM; 16-BIT RANDOM-ACCESS MEMORIE ca 74 CDB 483 EB; SUMATO R451 3 Laie e ean eae ee a 186 CDB 483 EM = 4-BIT BINARY FULL ADDERS CDB 486 E; 4 PORJI “SAU EXCLUSIV” CU 2 INTRARI. ... . . 190 CDB 486 EM; QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES cI 198 CDB 490 EB; | NUMARATOR ZECIMAL/DIVIZOR CU 2 SI DIVIZOR CU 5 193 CDB 490 EM © DECADE COUNTER|DIVIDE-BY-TWO AND DIVIDE-BY- FIVE CDB 492 B; | NUMARATOR/DIVIZOR CU 12 DIVIZOR CU 2 SI DIVIZOR 57452 AC ULG Rr 197 COUNTER/DIVIDE-BY-TWELVE DIVIDE-BY-TWO AND DIVIDE-BY-SIX CDB 493 B; NUMARATOR BINAR CU4BIJI............ 201 CDB 493 EM = 4-BIT BINARY COUNTER CDB 495 E; REGISTRU DE DEPLASARE CU 4 BITI CU ACCES PA- CDB 495 EM RALEL ..... 205 4-BIT PARALLEL. CDR 4121; MONOSTABIL . we ee 209 CDB 4121 FEM MONOSTABLE MULTIVIBRATOR CDB 4123 E; MONOSTABIL, DUBLU RETRIGHERABIL CU STERGERE 215 CDB 4123 EM DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRA- TORS WITH CLEAR CDB 4151 B; MULTIPLEXOR/SELECTOR DE DATE 8 BIJI....- 219 CDB 4151 EM —‘1-TO-8 DATA SELECTOR/MULTIPLEXER CDB 4153 E; MULTIPLEXOR/SELECTOR DUBLU DE DATE 4:1... 224 CDB 4153 EM = DUAL 4-LINE-TO-I-LINE DATA SELECTOR/MULII- PLEXER CDB 4157 E; MULTIPLEXOR/SELECTOR QUADRUPLU DE DATE 2:1 228 CDB 4157 EM = QUADRUPLE 2-LINE-TO-1-LINE DATA SELECTOR/MUL- TIPLEXER CDB 4180 FE; GENERATOR CONTROLOR DE PARITATE 8 BIJI . . 232 CDB 4180 EM 8&-BIT PARITY GE!CUPRINS LP, Fe SF CONTENTS eo @ CDB 4192 FE; NUMARATOR ZECIMAL, REVERSIBIL, SINCRON . . 237 CDB 4192 EM | SYNCHRONOUS UP/DOWN BCD COUNTER © CDB 4:93 E: NUMARATOR BINAR, REVERSIBIL, SINCRON . . . 242 CDB 4193 EM | SYNCHRONOUS UP/DOWN BINARY COUNTER @ CDB 837 E; 6 RECEPTORI DE LINIE 2 wwe ee 247 CDB 837 EA HEX UNIFIED BUS RECEIVERS e@ CDB 838 E; 4 EMITATORI/RECEPTORI DE LINIE ........ 251 CDB 838 EA; QUAD UNIFIED BUS TRANSCEIVERS CDB 838 EM @ CDB 8136; COMPARATOR 6 BITI..... ere 256 CDB 8136 C 6-BIT COMPARATOR Cireuite integrate TTL—M > 2 1. we 261 TTL—U integrated circuits @ CDB 400 HE; 4 PORJI “SI-NU" CU 2INTRART. 2... 2... 263 CDB 400 HEM; QUADRUPLE 2INPUT NAND GATES cir 50 @ CDB 410 3 PORTI “SI-NU” CU 3 INTRART....... er 266 CDB 410 TRIPLE 3-INPUT NAND GATES car 52 @ CDB 411 3 PORTI "SI" CU SINTRARI. 2... ee ee 269 CDB 411 TRIPLE 3-INPUT AND GATES cm 78 @ CDB 430 POARTA “SI-NU" CU SINTRARI.. 2... 0. 272 CDB 430 8-INPUT NAND GATE @ CDB 440 2 PORTI DE PUTERE “SI-NU" CU 4 INTRARI ... . 275 CDB 440 DUAL 4-INPUT NAND BUFFERS cir 54 @ CDB 451 2 PORTI “SI-SAU-NU” CU 2x2 INTRARI ww... 278 CDB 451 DUAL 2-WIDE 2INPUT AND-OR-INVERT GATES cH 58 @ CDB 454 POARTA “SI-SAU-NU" CU 24242;3 INTRARI.... 281 CDB 454 4-WIDE AND-OR-INVERT GATE cH 60 Cireuite integrate TTL—LPS ... 1. 1 1 ee ee ee 285 TIL—LPS integrated circuits © 74 LS 00; 4 PORTI “SI-NU" CU 2 INTRARI . w 2. ee eee 287 54 LS 00 QuaDRU NPUT NAND GATES @ 74 LS 02; 4 PORT 3 290 54 LS 02 QUADRUPLE 2INPUT NOR GATES @ 74 LS 03; 4 PORJI “SI-NU"” CU 2 INTRARI SIIESIRI CU COLEC- 54 LS 03 TOR IN GOL (6,5 V) ww. we ew ee 293 QUADRUPLE 2-INPUT NAND GATES WITH OPEN- COLLECTOR OUTPUTS @ 74 LS 04; @ INVERSOARE .......--020000- Pees 296 54 LS 04 HEX INVERTERS www. datasheetcatalog.com(ert PBS. ff BANEASA @ 74 Ls 08; 54 LS 08 e@ 74 LS 09; 54 LS 09 o74 54 74 54 o 74 54 @ 74 ‘54 @ 74 54 o% ‘54 e e e 7 e Circuite integrate HLL 2... 2... Ls Ls Ls LS Ls Ls Ls Ls Ls Ls Ls Ls Ls Ls 10; 10 I; 1 123 12 www.datasheetcatalog.com 4 PORTI “Sl” CU 2 INTRARI. . . QUADRUPLE 2INPUT AND GATES 4 PORTI “SI” CU 2 INTRARI SI IESIRI CU COLECTOR INGOT (5/Chv) eae aren er ee QUADRUPLE 2-INPUT AND GATES WITH OPEN- COLLECTOR OUTPUTS 3 PORJI “SI-NU” CU SINTRARI........-.- TRIPLE 3-INPUT NAND GATES 3 PORTI “SI” CU SINTRARI. 6. ee TRIPLE 3-INPUT AND GATES 3 PORJI “SI-NU” CU 3 INTRARI SI IESIRI CU COLECTOR IN GOL (55 Vw. ee ee ‘TRIPLE $-INPUT NAND CATES WITH OPEN-COLLECTOR OUTPUTS 3 PORJI “SI” CU 3 INTRARI SI IESIRI CU COLECTOR TEGOL|(S'ShV) ae ee eee ‘TRIPLE 3-INPUT AND GATES WITH OPEN-COLLECTOR OUTPUTS 2 PORTI “SI-NU” CU 4 INTRARI 2.1... ee ee DUAL 4INPUT NAND GATES 2 PORTI “SI” CU 4 INTRART. 2... eee DUAL 4-INPUT AND GATES 2 PORTJI “SI-NU” CU 4 INTRARI SI IESIRI CU COLECTOR IN GOL (55V) ... 00-0. ee DUAL 4-INPUT NAND GATES WITH OPEN-COLLECTOR OUTPUTS 4 PORJI “SI-NU” CU 2 INTRARI SI IESIRI CU COLECTOR IN GOL (I5 Vv) . . te See QUADRUPLE 2-INPUT NAND GATES WITH OPEN- COLLECTOR OUTPUTS 3 PORTI “SAU-NU” CU 3INTRARI..... 2... - TRIPLE 3-INPUT NOR GATES POARTA “SI-NU” CU 8 INTRARI.. 2... ee 8-INPUT NAND GATE 4 PORTI “SAU” CU 2INTRARI 6. ee ee QUADRUPLE 2-INPUT.OR GATES 2 PORJ? “SI-SAU-NU” CU 2x3/2x2INTRARI.... . DUAL 2-WIDE 3-.INPUT/2-WIDE 2-INPUT AND-OR-INVERT GATES POARTA “SI-SAU-NU” CU 2x2/2x3 INTRARI .. . AND-OR-INVERT GATE WITH 2x 2/2x3 INPUTS POARTA “SI-SAU-NU” CU 2x4 INTRARI 2... 3-WIDE 4-INPUT AND-OR-INVERT GATE HLL integrated eireuits © FZH 101; FZH 105 4 PORJI “SI-NU” CU 2INTRARI.. 2.2... eee QUADRUPLE 2-INPUT NAND GATES CUPRINS CONTENTS 299 302 305 311 314 317 323 326 329 332 338 341 344 347 349CUPRINS LP. BOs: AQ CONTENTS - { BANEASA Wd @ F2H 111; 4 PORTI “SI-NU" CU 2INTRARI 2... 2.11 ee 352 PZH 115 QUADRUPLE 2-INPUT NAND GATES @ F2H 121; 2 PORTI “SINU” CU 5 INTRARI... 2... 2 eee 335 FZH 125 DUAL 5-INPUT NAND CATES © FZH 131; 2 PORTI “SI-NU” CU SINTRARI.. 2... aren 358 F2H 135 DUAL 5-INPUT NAND GATES @ PZH 141; 2 PORTI DE PUTERE “SI-NU” CU 5 INTRARI .... 361 FZH 145 DUAL 5.INPUT NAND BUFFERS @ FZH 171; 2 PORTI EXPANDABILE “SI-NU” CU 4 INTRARI .. 364 FZE 175 DUAL EXPANDABLE 4-INPUT NAND GATES Cireuite integrate TIL 2. 2... 2. ee ee ee eee 367 IIL integrated eireuits © BP 1005 REGISTRU DE APROXIMATIT SUCCESIVE DE 10 BIJT 369 10-BIT SUCCESIVE APROXIMATION REGISTER © 6? 1009; PROCESOARE DE COMENZI CASETOFON ......- 373 6P 1010 PROCESSORS FOR CASSETTE-DECK CAPSULE ee ne einen eer ere oo 387 PACKAGES ANEXA: LISTA DE ECHIVALENTE. «0. eee 391 APPENDIX: CROSS REFFERENCE GUIDE TNEOR MAT en ne een ae eer 429 INFORMATION www.datasheetcatalog.comF Ar I. Pp. RS. INDEX ALFANUMERIC a By sannasa ALPHANUMERICAL INDEX TIP PAGINA ‘TIP PAGINA TYPE PAGE TYPE PAGE 54 LS Powe ee ee (287 CDB 400 HEM... 2... 263 54 LS Foe ee ee ee 290 cbDB402E ... 64 54S 03%... ...-.-- 293 CDB 402 EM... 64 7) 296 CDB 67 S415 08222255222 299 cDB 67 54 LS Foe ee ee 302 cDB 70 5415 We ee ee 305 cDB 70 SUSI. ee 308 cDB 3 SLBIZ%.. 2. ee 31 cDB 73 5415 Mowe wee 3i4 CcDB 76 . 317 cDB 76 . 320 cDB 729 . 323 cDB 73 * 326 cDB 82 . 329 cDB 82 332 cDB 335, CcDB 338 cbB 341 cDB 344 cDB 287 oe 290 coe 203 sal cDB aD cDB 3 cDB 302 305 CcDB 308 cDB 311 cDB 314 cDB 317 cps 320 CDB 323 CDB 326 cDB 329 CDB 332 ee 335 CDB eee cDR ett cDB 344 CDB CDB CDB 400 E 61 cpB CDB 400 EM 61 cpB CDB 400 HE 263 CDB * DATE PRELIMINARE PRELIMINARY DATA www.datasheetcatalog.comINDEX ALFANUMERIC ALPHANUMERICAL INDEX TIP PACINA ‘TIP PAGINA TYPE PAGE TYPE PAGE cDB 275 CDB 838 EA 251 CDB 118 CDB 833 EM 251 CDB 118 CDB 123 CDB4I21E.... 2... 209 CDB 123 CDB 4121 EM 2... ee. 209 CDB 129 CDB423E..... 000 215 CDB 129 CDB 4123 EM 2... 1. 215 CDB 136 CDB4I5IE.... eee 219 CDB 136 CDB 4151 EM 2... 219 CDB 140 CDB 4153 © 224 CDE 140 CDB 4153 EM 224 cDB 278 CDB 4157 B 223 cDB 278 CDB 4157 EM 228 cDB 143 CDB 4180 E 232 CDB 143 CDB 4180 EM 232 cDB 147 CDB 4192 E 237 cDB 147 CDB 4192 EM 237 DB 281 CDB4I9E... ee. ee 242 cDB 281 CDB4I99 EM 2... eee 242 (DB 150 cDB 150 CDR 8136 2... ee 256 cDB 154 CDB 8136C Le 256 cDB 154 cbB 159 cu 30... 61 cDB 159 cI 31 140 cCDB 164 cu 32... 115 DB 164 cir 33. 103 CDB 170 cm 44... 154 CDB 170 cm46 le 147 cDB 175 cma. ee 88 cDB 175 cu50. 2... ee 263 cDB 181 Geo eocao5acoae 266 cDB 181 cr 54... 500508 275 cDB 186 (Ni E3coo5000a000c 278 cDB 186 GNC)ooc040050000 281 cDB 190 07d 181 cDB 190 CWB... 269 cDB 193 En SS eee eee 159 CDB 193 (a 65000040000 100 cDB 197 (5 oo cana000G 190 cDB 197 (SNF) 6000000000 70 DB 201 cDB 201 e2Eg1 0 eee 349 cDB 205 F2H 105. ......008 349 cDB 205 F2H 11... ws 9000 352 CDB 837 E 247 e200 See 352 CDB 837 EA 247 FZH 121. ee ee ee 355, CDB 838 E 251 hast Joooo000000 355 10 www. datasheetcatalog.comr Ss LP. B.S. INDEX ALFANUMERIC | ALPHANU} ; 24 BANEASA LPHANUMERICAL INDEX TIP PAGINA TIP PAGINA TYPE PAGE TYPE PACE FZH 131 358 BP 14104... 37 FZH 135 358 BP 14113. . 47 FZH 141 361 BP 14151. 53 FZH 145... . 361 BP 14500 . ae . see 24 FZH 171... + 364 BPC 14104... le 37 FZH 175 364 BPC 14113... 0.000. 47 BPC 14151... 2... ee 53 pP 1005... 2... 369 bios lll lll pe BPC 14500... 2. se 24 BP 101l0 . |. 373 __wiww.datasheetcatalog.comwww.datasheetcatalog.comww.datasheetcatalog. MICROPROCESOR BIPOLAR — SERIA 14000 14000 SERIES BIPOLAR MICROPROCESSORwww. datasheetcatalog.comBP 14500 BP 14113 RP 14104 BP 14151 MICROPROCESSOR BIPOLAR SERIA 14000 BIPOLAR MICROPROCESSOR 14000 SERIES DESCRIERE GENERALA Seria de circuite integrate 14000, avind ca pilot procesorul de 1 bit BP 14500, este desti- nat controlului automat al proceselor industri- ale si automatizirilor in electronica de larg consum, Ba cuprinde urmitoarele cireuite integrate: @ SP 14500, procesor de 1 bit (unitate cen- tralf) ; @ BP 14104, numiritor de program de 4 Digi, expandabil ; © SP 14113, demultiplexor 1: 8 cu memorie (interfafi de iegire) ; @ P 14151, multipleror 8:1 TRI STATE (interfafi de intrare) Primele 3 cirenite sint procesate in tehnologie UAL, iar ultimul, BP 14151 in tehnologie TTL. In funefie de dimensiunile aplicatiei, cu seria 14000 se pot construi automate programabile eu zeci, sate sau chiar mii de intrari si iesiri, avind ‘0 capacitate proporfional de mare Pentrn memoria de program. Aceste automate programabile inlocuiesc cu succes sistemele cn relee electromagnetice sau logica TTL cablaté, aducind avantaje ca: fiabilitate ridicats, intrefinere usoar, dezvol- tarea san modificarea prin program a logicii de control. Ele acopera cu usurint’ aria auto- matizirilor ,,simple” (dar si cele mai des in- tilnite) unde un sistem ,,puternic”, cu micro- procesor de 8 bifi ridic& probleme de eficienfa : consum& prea mult sau e prea voluminos san prea scump, AUTOMATE PROGRAMABILE CU PRELU- CRARE DE BIT In majoritatea automatizirilor industriale, semnalele primite de la traductoarele de proces Precum si comenzile date elementelor de exe- cutie sint mirimi cu dona stiri, de tip : ,,deschis/ inchis” san ,,pornit/oprit”. Iaté un exempin:este intrerupitorul K1 inchis si K2 deschis? GENERAL DESCRIPTION ‘The 14000 I.C. series, based on the 1-bit con- troller 6P 14500, is destinated to industrial and consumer automation. It contains the following integrated circuits: @ BP 14500, 1-bit controller (central unit) @ @P 14104, 4-bit, expandable program counter ; © GP 14113, 1 to 8 demultiplexer with memory (output interface) ; @ GP 14151, 8 to 1 tr state multiplexer (input interface). ‘The first three circuits are processed in I'L technology; BP 14151 is a TLI circuit. Depending on the dimension of application, the 14000 series can configurate programmable controllers having tenth, hundreds or even thousands inputs and outputs and an appro- piate memory capacity. ‘These programmable controllers succesfully sub- stitute relays systems and solid state logic, offering advantages like; long term reliability, easy servicing, software posibility of changing or developing the control logic ‘They easy cover the area of “simple” (but most met!) automations, where a “strong” system, with an 8-bit microprocessor, rises efficiency problems consumes too much, ite too bulky or too expensive. BIT-PROCESSING PROGRAMMABLE CONTROLLERS In most automation problems, both input information from process and output com- mands are two-state signals, like “open/closed” or “onjoff*. For exemple: is K1 switch closed and K2 switch open? Start motor MI and alternately switch on and off 18 LED, till FTS phototransistor becomes saturated. In 6BBP 14500 BP 14113 BP 14104 BP 14151 Daci da, porneste motorul MI gi aprinde intermitent LED-ul 13, pind la saturarea fototranzistorului FTS In astfel de aplicafii, analiza traductoarelor de proces (intrerupiitor deschis/inchis, foto- tranzistor saturat/blocat) se face pe rind (unul cite unul). De asemenea, comenzile citre ele- mentele de execufie (motoare, electrovane, triace) se dau tot pe rind (una dupa alta). Aceasté manieri a unui sistem programabil, de a prelucra ia un moment det starea unei singuse linii (Ge intrare sau de iesire) se numeste PRELUCRARE DE BIT. Automatele programabile realizate cu seria 14000 sint structurate pentru prelucrarea de bit. Ele sint pilotate de un microprocesor de 1 bit, BP 14000, care oferi solutia OPTIMA la rezolvarea genului de automatiztiri descrise mai sus. INTR-UN AUTO- CONSTRUIT CU CIRCULATIA DATELOR MAT PROGRAMABIL SEWIA 1400° Fluxul de prelucrare a datelor si generare a comenzilor intr-un automat programabil con- struit cu seria 14000 este prezentat in fig. 1. LO, L0C AND ,ANOC OR ORE xNOR 16 LP.RS. _BANEASA eo such applications, the process signal analysis (switch open/closed, phototransistor on/off), ig made in seqvence, one by one. Output com- mands (to engins, triacs, electrovalves) are also done on a one-at-a-time basis. This pecu- liar way of processing one I/O line loyic state at a time is called BIT PROCESSING. ‘The 14000 series based on programmable con trollers are bit processing systems. Their cen- tral unit is a 1-bit controller, 3P 14500, wich offers THE OPTIMAL WAY to solve such kind of automation as previously described. DATA TRANSFER IN A 14¢ SERIES BASED ON PROGRAMMABLE CONTROLLER www. datasheetcatalog.com Data flow-chart in a 14000 serie based on programmable controller can be seen in fig. 1. RESUIT REGISTERQLPRS bid BANEASA BP 14104 BP 14152 BP 14500 BP 14113 Stirile intririlor Ip, I, ... In pot fi citite pe rind (una cite una) prin intermediul unui MULTIPLEXOR. Valoarea unci date de intrare se poate tncirca, prin intermediul unitifii logice, im registrul rezultat (RR) aflat pe post de acumulator de 1 bit. Tot cu ajutorul unitafii logice, in registrul rezultat se pot fnclirca diverse combinafii (SI, SAU, SAU- EXCLUSIV-NU) intre o variabil’ de intrare si propria stare (RR) de la momentul ante- rior, Funcfia unitifii logice se alege cu ajutorul uneia din urmitoarele 7 instructiu @ LD (LOAD): incarei RR cu date de intrare (IRR); @ LDC (LOAD COMPLEMENT): incared RR_cu data negaté (I+ RR); @ AND: incarci RR cu valoarea functiei T-RR: @ ANDC (AND COMPLEMENT): incarcé RR cu valoarea funcfiei I- RR; @ OR: incared RR cu valoarea functiei I + +RR; @ ORC (OR COMPLEMENT): incarei RR cu valosrea functiei 1+ RR; @ XNOR (KOR NEGATE): incarcé RR cu valoarea functiei T@RR, (sau, mai expli- cit: daca [= RR, KRW “1”"). Continutul registrului reznltat (RR) poate fi transferat la oricare din iesirile Qo, Q, ... Qu, printr-un circuit demultiplexor terminat ct celule de memorie (M1). Data emisi este memorati pe fiecare iesire, pentru a se realiza COMENZI MENTINUTE. Emisia de date se face cu una din urmitoarele dona instrucfiuni ; @ STO (STORE): emite valoarea lui RR la iesire (RR + O) ; @ STOC (STORE COMPLEMENT): emite valoares Ini RR Ia iegire (RR — Q). SCRIEREA PROGRAMULUL | } La redactarea umni program, instructiunile de citire sau de scriere trebuiesc insofite de adresa intrarii (respectiv iesirii) 1a care se refer 4. De exemplu, daca segistrul RR trebuie incircat cu valoarea intririi T,, instrucfiunea necesari este: IDI, — Circuite integrate logice Inputs logic state is read one-by-one, through a multiplexer. Input data can be loaded via the logic unit in the result register (RR), an 1-bit accumulator. The logic unit also genera- tes Bodeau functions (AND, OR, EX-OR- NEGATE) between input data and the con- tent of result register, to be loaded again in the result register. ‘The logic unit function is selected with one of the next 7 instructions: LD; LOAD result register: I+ RR LDC; LOAD COMPLEMENT: I+RR AND; logical AND: RR-I+RR ANDC; logical AND COMPLEMENT: R-I+RR OR; logical OR; RR + I + RR ORC; logical OR COMPLEMENT: RR+IGRR XNOR; EXCLUSIVE OR NEGATE: RR®I—RR; in other words: if RR=1, RRO ‘The result register content can be transfered to anyone of Qs, Q, ... Qy¢ outputs through a memory ended demultiplexer. Emited data is memorated on each output, to realise MAIN- TAINED COMMANDS. Data is emitted using one of the next instruc- tions: © STO; STORE result register: RR+Q @ STOC; STORE COMPLEMENT: RR +Q PROGRAM EDITING When editing control programs, read/write instructions must be followed by the appropiate input/output adress, As an exemple, the instruc- tion for KR loading with I, input logic state is: wi, wv www. datasheetcatalog.comBP 14500 BP 14113 BP 14104 BP 14151 Daca se doreste scrierea confinutului registrului RR In iegirea Q, gi RR la iegirea Q,, se folosese instructiunile : STO Q, STOC Quis www.datasheetcatalog.com CONTROL, TT INTERFACE L PRS. & or BANEASA 9 ‘Transfering RR contents to Q» ou put and RR to Qi is made with next instructions: STO Q, STOC Que INSTR Fig. 2 ARHITECTURA UNUL AUTOMAT PROGRA- MABIL CONSTRUIT CU SERIA 14000 Dup& cum se vede in figura 2, un automat programabil coustruit cu seria de circuite integrate 14000 foloseste ca unitate centrald procesorul BP 14500. 18 14000 SERIE BASED ON PROGRAMMABLE CONTROLLER ARCHITECTURE ‘As can be seen in figure nr, 2, a 14000 serie ‘based on programmable controller uses BP 14500 controller as central unit.mates 4 BANEASA Accesul datelor de intrare se face secvential, prin multiplexare, cu ajutorul unuia sau mai multor circuite BP 14151 legate in paralel pe linia de 1 bit DATA. Transferul datelor din acumulatorul procesoru- ini c&tre iegiri se face tot secvential, ins& prin demultiplexare, eu ajutorul unuia sau mai multor circuite BP 14113. Programul de control se afl& inseris intr-o memorie ROM. Memoria este adresat& de un numiritor de program realizat prin legarea in serie a mai multor circuite BP 14104. De exemplu, cu 3 circuite SP 14104 se pot adresa 2% — 4096 locafii de memorie. Funcfionarea numardtorului de program, este condifionata de iegirile de control (flaguri) ale procesorului BP 14500. Se pot executa salturi in program, apeliti de subrutine si cuiburi de subrutine pe dot nivele. Pe linia de DATA mai pot fi cuplate gi alte circuite, ca de exemplu: o memorie RAM organizaté pe bit, circuite de temporizare analogica (tip monostabil) san numerica (numi- ritor programabil), convertoare A/D sau DjA ca acces serial etc. APLICATIT ALE SERIEI 14000 Pentru a facilita accesul seriei 14000 spre utilizatori, IPRS-Bineasa a lansat fabricatia unot module de automate programabile, nn- mite KIT-uri PROCESOARE, Aceste module au format standard EUROCARD (10 x 16 cm?) gi conector de 3 x 32 (2 x 32) contacte, DIN 14612 Ele au arhitectura tipicd prezentata in figura 2, inglobind toatd partea de prelucrare logicé a datelor, inclusiv memoria de program. Pentru realizarea unei automatiziri cu un KIT PROCESOR-IPRS utilizatornl mai are de rezolvat urmitoatele probleme : © HARDWARE = Circuite de _interfapi KIT — proces; =sursi_ de alimentare de +5.V: =cofret de montaj, tip RACK. BP 14500 RP 14113 BP 14104 BP 14151 Input data acces is made sequentially, by multiplexing, using one or more BP 14151 IC. parallel conected on the I-bit DATA line. ‘Transiering RR accumulator contents to the outputs is made sequentially too, by demulti- plexing, using one or more (P 14113 I.C. The control program is written in ROM me~ mory. The memory is adressed by program counter, composed by several BP 14104 LC, As an exemple, 3 SP 14104 circuits can adress 2" = = 4096 memory locations. ‘The program counter function is selected with BP 14500 control flags. It is permitted to JUMP in to the program, to CALL subrouti- nes and even to use two level nested subrouti- nes technique. DATA line may be loaded with many other devices, like: an I-bit organised RAM memory, analog timers, programmable counters, A/D or D/A serial acces converters ete. 14000 SERIES APPLICATIONS www.datasheetcatalog.com To easily penetrate with 14000 series on the market, IPRS-Bineasa began a programmable controller modules fabrication, called KIT PROCESSOR. This modules have standard Eurocard format (10 x 16 cm?) and termi- nate on DIN 14612, 3 x 32 (2 x 32) pins connector. Their architecture follows the mode! presented in figure nr. 2, containing the whole Gata logic control and the program memory. To automate a procces using IPRS-KIT PROCESSOR the user still has to do: @ HARDWARE = KIT/process interface cir- cuit = +5 Vde power supply; = assembling rack.BP 14500 RP 14113 BP 14104 BP 14151 @ SOFTWARE =redactarea programului de control si inscrierea Iui_in memoria PROM (EPROM) de pe KIT-ul PROCESOR. 1. KIT PROCESOR 14090 Este un modul programabil super-miniaturizat (utilizatorul fi poate ,,ajusta” dimensiunile pind la un format de 10 x 10 cm) destinat automatizirilor de complexitate redusi, Principalele caracteristici tenice stint: @ (6 intrari TTL, gi 16 iegiri TTL cu memoric; 3 temporiziri analogice cu durata reglabild ; @ Lungimea programului : maxim 256 instruc- tiuni Generator de tact incorporat; gama de frecventi: 0... 500 kHz; Programare facili: set de 16 instructiuni ; Salturi tn program, cuiburi de subrutine pe 2 nivele ; AUTORESET Ia conectarea tensiunii de alimentare si 2 intriri de RESET: RESET CENERAL 5i RESET PROCESOR ; Memorie de program tip PROM (612 x 4) sou (optional) EPROM 2k x 8; © singuri sursi de alimentare: +5 V; consum tipic: 370 mA. e@ e8 6 @ SOFTWARE =control program editing and ROM programming. 1. KIT PROCESSOR 14000 A It's super-miniaturised programmable control- Jer (the user can “adjust” it till a 19 x 10 cm* format) destinate to small size automations. Basic characteristics are : @ 16 TTL inputs and 16 TTL latched out- puts ; @ 3 analog timers with variable timing; program leaght: max. 256 instructions; incorporated clock generator: frequency interval 0... 500 kilz; easy to program: 16 instructions set; JUMP instruction, 2-level nested subrouti- nes CALL; Power supply connecting AUTORESET and 2 RESET inputs GENERAL RESET and CONTROLLER RESET; 512 x 4 wide PROM or (optional) 2k x 8 EPROM program memory, ©@ single power supply: +5 V; typical con- sume: 370 mA. www.datasheetcatalog.com 2 KIT PROCESOR 15000 Liste un modu! programabil destinat aplicati- flor cuun numér mare (zeci, sute) de intrari gi iesiri, Un automat programabil de asemenca dimeusiuni e compus dintr-un modul KIT PROCESOR. 15000 si mai multe (maxim 63) MODULE DE EXTENSIE 15000, legate tn paralel pe BUS-ul de instructiuni/adrese, KIT- ul PROCESOR 15000 are urmitoarele carac- teristic’ tehnice : © 1Gintrisi TTT, 9 16 iegiri TTL cu memoric; ® 6 temporiziri analogice cu durata reglabili, interogabile; @ Cimp de adrese pentru 1024 intr&ri, iegiti i temporizini ; 2. KIT PROCESSOR 15000 It’s a programmable controller recommended for applications with large number (tenth, hundreds) of 1/0. Such a programmable controller contains one module KIT PROCESSOR 15000 and several (63 maximrum) extension modules, named MODUL EXTENSIE 15000. All this modules are parallel connected on the instruction/address bus. KIT PROCESSOR 15000 is characterised by: @ 16 TTY, inputs and 16 TTI, latched out- puts;Payi. P.B.S. 5 BANEASA @ Lungimea programului ; maxim 4096 instruc @ Memorie RAIL pentru date de Lk x I bit cu posibilitatea alimentirii separate (regim STAND BY); @ Instructiuni de scriere simultani a datei la iegiri si in RAM (RAM oglind’) @ Memorii de program EPROM, de 2k x 8 bifi sau pentru capacitates ‘maximi de 4k x 8 biti; @ 4 instructiuni de salt: JMP, JMPZ (IF RR=0), CALL, RTN; 2 nivele de subrutine ; Consum tipic: 600 mA la Vee = +5 V; Format EUROCARD: 10 Xx 16 cm*, ee 3. KIT EXTENSIE 15000 (date preliminare) Acest moditl este destinat extinderit numarulai de intrari, iesiri si temporiziri intr-un auto- mat programabil construit cu KIT-ul PROCE- SOR 15000. El are urm&toarele caracteristici tehnice : @ 16 intrari TTL si 16 iesiri TTL cu memorie ; @ 8 temporiziri analogice interogabile; Adresa de selectie a modulului (5 biti) accesibili pe conector ; @ Consum tipic: 500 mA la Vec = +5 V Se pot conecta direct la KIT-ul 15000 maxim 3 module de extensie, pentru configurarea unui automat programabil cu 64 intrari i 64 icsiri. In cazul folosirii mai multor module de extensie este uecesar un buffer de linie, 4. SISTEM DE (date preliminare) ACHIZITIE A DATELOR Acest sistem foloseste seria de cirenite 14000 pentru controlul achizitiei gi conversiei de Semnale analogice in numere de 8 bifi, El are urmitoarele caracteristici : @ 8 canale anslogice adresabile; @ ‘ensiune maximi de intrare: 10 Vee; BP 14500 BP 14113 BP 14104 BP 14151 © 6 analog timers with vaciable timing; @ 1024 I/O and timers address field ; @ program lengh: max. 4096 instructions; e@ ikx1 DATA RAM with STAND BY supplying mode; @ simultaneous store to outputs and RAM instructions ; @ 2k x 8 or (for maximum capacity) 4k x 8 EPROM program memory; e@ 4 jump instructions: JMP, JMPZ (if RR = 0), CALL, REN, 2 level nested subroutines ; @ typical current consumption: 600 mA at +5 Vde; @ 10 x 16 cm* EUROCARD format. 3. KIT EXTENSIE 15000 (preliminary data) This module serves to external I/O and timers in a programmable controller built with KIT PROCESSOR 15000. Basic characteristics: @ 16 TTL inputs and 16 TTL latched out- puts; @ 8 analog timers with variable timing; © S-bit module adress select available’ on connector ; @ typical power consumption: 500 mA at +5 Vde. One may directly connect maximum 3 extension modules to configurate a 64 I/O programmable controller. More extension modules need a line-buffer. www.datasheetcatalog.com 4. DATA ACQUISITION SYSTEM (prelimi- nary data) ‘This system uses 14000 series to control analog signal acquisition and 8-bit A/N conversion. Basic characteristics : @ 8 analog addressable channels; @ maximum input voltage: £10 Vde; 21RP 14500 BP 14113 RP 14104 BP 14151 Auplificator de precizic, programabil, incor- porat ; Registru de aproximatii succesive de 8 biti Rata de cgantionare: 50 kHz; Tegire seriald a datelor de conversie A/D; Sistemul e pilotat de un procesor BP 14500; Arhitecturd microprogramata ; Dimensiuni EUROCARD: 10 x 16 cm* Compatibil (ca modul de extensie) ew KIT-al PROCESOR 15000. ©00000 © 0 LP. RS. Ny __ BANEASA hs programmable precision amplifier incorpora- ted; &-bit succesiv approximation register ; sample and hola rate: 50 kHz; serial output for A/D converted ‘data; uses a BP 14500 for system control ; microprogrammed architecture ; 10 x 16 cm? EUROCARD format; compatibility (as extension module) with KIT PROCESOR 15000 BUS. www.datasheetcatalog.com 5. CONSOLA DF 1 PENTRU KIT-ol preliminare) VOLTARE/EXERSARE, PROCESOR 14000 A (date Consola de dezvoltare/exersare este destinata redactirii, corectirii si verificdrii ,,pe_viu” a programelor de control pentru KIT-ul PROCESOR 14000 A. Caracteristici tehnice : @ Include 2 KIT-uri PROCESOARE 14000 A, unul pentru exersare gi unul pentru controlul claviaturii ; @ Afijaj hexazecimal pentru adrese gi instructi- uni; Martor sonor Ja optsarea tastelor; Posibilitatea rullirii de programe scrise in RAM sau EPROM; © Posibilitatea simulirii interactiei_ cu pro- cesul, cu ajutorul a 16 intrerupatoare si 16 LED-uri conectate la intririle, respectiv iegirile KIT-ului exersat. Cu ajutorul unor taste dedicate, se pot selecta urmitoarele funcfii ale consolei de dezvoltare/ exersare : © Editare si corectie de program, cod obiect ; Execufia programului pas cu pas: Execufia programului in timp real: @ Autorepetarea functici la mentinerea co- menzilor_ ,INCREM” si ,,STEP”; @ Adresi de intrerupere pregramabil; e seris in Stergerea (resetarea) memoriei de program; Copierea unui program din EPROM in RAM; @ fnscrierea programului din RAM in EPROM. 5. DEVELOPPING/EXERCISING KEYBOARD FOR KIT PROCESSOR 14000 A (preliminary data) ‘The developping/exercising keyboard is used to edit, correct and “live” check of control. programs written for KIT PROCESSOR 14000 A. Basic characteristics : © includes 2 pcs, KIT PROCESSOR 14000 A, one for exercising and the other for keyboard control; hexadecimal display for instructions ; soft touch keyboard with beeper; RAM/EPROM program storage; adresses and process dialogue simulation using 16 swit- ches and 16 LED's connected to I/O exerci- sed KIT. Special function keys are used to select one of the following keyboard function : @ object code program editing and correcting; @ step by step program execution; © real time program execution; © autorepeat on “INCREM” and “STEP* keys; @ programmable Break Point; program memory KESE’ @ RAM from EPROM program copy ; e EPROM programming,6 LP. R. s. ( BANEASA 6. SUPORT SOFTWARE PENTRU 6P 14500 Pentru a ugura activitatea de proiectare a automatizrilor eu KIT-ul PROCESOR 14000 A, IPRS-Bineasa pune la dispozitia beneficiari- lor urmatorul set de programe: © Un asamblor de limbaj 14500; @ Un simulator al activitatii | KIT-ului; @ Un program pentru inscrierea codurilor object intr-o memotie EPROM de 2k x 8 biti. Programele pot fi rulate pe un minicalculator din seria CORAL 4000, (PDP 11) im sistemul de operare RT 11, Ele pot fi copiate de la IPRS pe FLOPPY disc sau pe band’ perforata. In prezent se finalizeaz’ (ia colaborare cu Centrul Teritorial de Calcul Tirgu-Mures) un asamblor pentru KIT-ul PROCESOR 15000. Programul este scris pentru microcalculatoare de tip M 18, M118, TPD, JUNIOR, INTELLEC. 80, sub sistemul de operare CP/! www. datasheetcatalog.com BP 14500 BP 14113 RP 14104 RP 14151 6. BP 14500 SOPTWARE SUPPORT ‘To easy automate with KIT processor 14000 A, IPRS-Baneasa offers by request the next software; 14500 language assembling program ; @ XIT activity simulator program; @ 2k x 8 EPROM ,,buming” program. ‘The software support is written for CORAL 4000 microcomputer series (PDP Il) under RT 11 operating system, It may be coppied on 8 inches floppy disk or punch tape. Presently is to be finished (in cooperation with C.T.C, Tirgu-Mures) a KIT-15000 lan- guage assembling program, The assembler is written for: M 18, M 118, TPD, JUNIOR, INTELLEC 80 microcomputers, under CP/M operating system. 23BP 14500 ‘i PRS. eo RPC 14500 _BANEASA Oi PROCESOR DE 1 BIT 1 BIT PROCESSOR Vo RR oxy x2 PIN FLD LE THEE HEHE HEHEHE] BST WRITE OTA 13001201) 1B GND MP 117 Conexiuni Pin configuration vec x2 MP RIN oS DOH | Ri | RST WRIE OBTA Bo hy oO } Schema bloe Funetional block diagram www.datasheetcatalog.com 24(art PRS. BANEASA | i q DESCRIERE GENERALA Circuitele integrate @P 14500, PPC 14500 au rolul de unitate central& in schemele de automate programabile constraite cu seria 14000. Ele an un set de 16 instructiuni de program gi exccuta cite o instructiune pe perioa- da de tact. Funcfionarea este urmitoarea: Inceputul perioadei de tact coincide cu fron- tul cizlitor al tactului, cind instructiunea serisi in cod binar (I,I,I,Iy) este memorat’ in registrul de instructiuni (INSTRUCTION REGISTER, in schema bloc). Unitatea logic (LOGIC UNIT) decodifica instructiunile si formeazi functiile de incareare a registrului rezultat RR, aflat pe post de acumulator de I bit. Tot unitatea logic tran- sfer& informatia din acumulator (RR sau RR) pe linia DATA, La scriere (emisie), DATA functioneazi ca TESIRE si e activi o perioada de tact. De asemenea iesitea WRITE trece in stare “I” in prima jumitate a perioadei de tact (cind C= 0). Registrele IEN (INPUT ENABLE) si OEN (OUTPUT ENABLE) conditioneazi accesul datelor de intrarefiegire pe linia bidirectional DATA. Incircarea se face cu instrucfiuni specifice: TEN, respectiv OEN. Atunci cind ambele registre IEN, OEN sint in starea “I”, datele de intrarefiesire cireuli neafectate, conform instructiunilot de pro- gram. Daci registrul TEN are starea “0, data pcitita’” de unitatea logic’ este intotdeanna “0”, indiferent de nivelul logic aplicat pe linia DATA, Daci registrul OEN are starea “0”, procesornl de 1 bit ignori (nu executa) nici © instrucfinne de scriere: linia DATA e in starea de impedanya mare (Z) iar iesirea WRITE fn starea "0". La inifializare (RST=1) registrele IEN, OEN gi RR sint aduse in starea “0”. Inciircarea lor se face pe linia DATA, pe frontul crescitor al tactului X,. Cu alte cuvinte, instructiunile de citire se incarci pe frontul cizitor gi se executi pe frontul crescitor al tactului X,. Validarea incircirii este dati de blocul CON- TROL, in urma decodificirii instructiunii de BP 14500 RPC 14500 GENERAL DESCRIPTION @P 14500 and BPC 14500 integrated circuits are used as central unit in the programmable logic controllers, builded with 14000 serie. ‘They have a 16 program instructions set and execute ome instruction per clock period, The sequence of operation is: ‘The clock period begins with the folling edge of the clock pulse, when the instruction in binary code (IylqliIq) is memorated in the INSTRUCTION REGISTER (ce block dia- gram). The LOGIC UNIT decodes the instructions and creates the load functions for the RESULT. REGISTER (RR), an one-bit accumulator. ‘The logic unit also transfer the information from accumulator (RR or RR) on the DATA line. In the WRITE (emiting) moae, DATA works as an output and is active a full clock period, Write output is also active (high state) during the first half clock period (when X,=0), INPUT ENABLE (IEN) register and OUTPUT ENABLE (OEN) register control data transfer on the DATA bidirectional line. They are loaded with specific instructions: TEN and OEN, respectively. When both IEN and OEN register are in high state, the inputfoutput date are transferred unafécted, following the program instructions. If TEN register is in low state, the logic unit reads allways data as being low state, no mater what logic level is applied on DATA linet If OEN register is in low state, the one bi processor ignores (does not execute) any write instruction: DATA line is HIGH IMPEDANCE and WRITE output in low state. After the reset function (RST input high) TEN, OEN ond RR registers are cleared. ‘Their loading are made on the leading edge of X, clock. In other words, the read instructi- ons are loaded on the falling edge and are executed on the leading edge of X, clock. Load enabling is made by the CONTROL block, according to the program instructions. 25 www. datasheetcatalog.com‘BP 14500 RPC 14500 program. Tot blocul control activeazi iesirile de flag: FLF, FLO, RTN 5i JMP, care ramin active (nivel “I") pe intreaga perioadi de tact. Cirenitele integrate SP 14500 au incorporat un oscilator de tact (OSC) a c&rni frecven}i se stabileste cu ajutorul unui circuit exterior RC. Schema de conectare si caracteristica de frecventa se dau in fig. 3. =} ' ILP RS. _BANEASA ‘The CONTROL block also activates the flags FLE, FLO, RTN and JMP, wich remain actives (high level) a full clock period. @P 14500 and BPC 14500 integrated cir- cuits contains a clock generator (OSC), wich frequency value is determined by an external RC circuit. Connecting scheme and frequency characteristics are presented in fig. 3. rT i Mie F x wi} R 13 ‘Dout2| ' | @ IR=2 ‘oir ca v ®WonF Fig. 3 Intrarea RST (activ in starea “1") fixeazi iesirea X, in starea “1”; dup’ caderea intr&rii RST fn starea “0, amorsarea oscilasiilor are Joc dup% circa 100 ns. Pentru sincronizare extern’, intrarea X, se conecteazi la masa iar pe terminalul X, (rimas fn starea “‘I”) se aplicd un semnal drept- unghiular de la o iesire TTL. CARACTERISTICI PRINCIPALE, BASIC CHARACTERISTICS The RST input (active in high state) forces X, output to high level; when RST goes low, the oscillator starts after 100 ns approx. For external sincronisation, Xj input must be grounded and a square form sigual must be sended to X, pin (latched in high statey through a TTL output. | \ y, CAPSULA | CAMA TEMP. DE FUNCTIONARE | FRECVENTA DE TACT | Yeo) FACKAGE| OPERATING TEMPERATURE | CLOCK FREQUENCY RANGE | man. max, a Al +85 1 MHz . P 14500 | MP 117 OPC + 485°C Hi 45 55 BPC 14500 | MP 117 —10°C + +70°C 200 kHz 475 5,25 www. datasheetcatalog.comAt PRS. | ws BANEASA SETUL DE INSTRUCTIUNI INSTRUCTION SET RP 14500 BPC 14500 www. datasheetcatalog.com | cop my ICA, FUNCTIB | cope MNEMONICA FUNCTION o 0000 NOPO Activeaza iegirea FLO: N= FLO Activate FLO output: 1 0001 LD Incarc& registrult reaultat: [DATA RR Load Result Register : 2 0010 Lpc | Incarci complement : ‘DATA -+RR - Load Complement : SI logic: DATA + RRRR Logical AND $1 complementar : +RRRR | Logical AND Complement : 5 or | OR SAU logic: DATA +RRRR j— | Logical OR: 6 0110 | ORC SAU complementar: DATA +RR—RR ‘Logical OR Complement : 7 ould XNOR SAU-EXCLUSIV-NU DATA @RR—RR Exclusive OR Negated: 8 1000 STO Afigeazi RR : RR DATA; Store RR: N+ WRITE 9 1001 sToc Afiseazi complement : RR | DATA; Store Complement : N— WRITE A 1010 | TEC Incarc’ registrul TEN: DATA —IEN Toad IEN Register: B 1011 OEN fucarcd registrul OREN: DATA + OEN Load OEN Register: ¢ | 100 JMP Activeaza iesirea JMP: fl— JMP | Activate JMP output: D 1101 RIN Activeazit iesirea RIN gi ig- nord urm&toarea instructiune : —+RTN Activate RTN output and skip : _next instruction z 1110 SKZ tion : FO) ou NOPF ‘Activeazi iegirea PLE : PLE | Activate FLF output : QTBP 14500 BPC 14500 DIAGRAME FUNCTIONALE FUNCTIONAL WAVEFORMS frol - f - te ee ee ee i TCONT > es) oe es ee es oe aR __ INSTR C D FE z ye n son ST Fig. 4. Instructiunile NOPO, NOPF, JMP, RTN si SKZ NOPO, NOPF, JMP,RTN and SEZ instructions | www. datasheetcatalog.com aBP 14500 BPC 14500 DIAGRAME FUNCTIONALE FUNCTIONAL! WAVEFORMS 2 aa INTRA 0 gy 2 72 7 7 2 3 3 3 [OU int Ro IN. en _[ TEA www. datasheetcatalog.com RS. re mA) Fs WIR? 4 2 bas 5 Un trite tintin a op UIEN=1) (CONT > RS. mJ Paar INSTR:7 77 7&1 RA 4 Fo m1 nn iewanTeRN———L_ Fig. 5. Instructiuni de citire: LD, LDC, AND, ANDC, OR, ORC, XNOR gi IEN. Linia DATA functioneazi ca intrare. Read instructions: LD, LDC, AND, ANDC, OR, ORC, XNOR and IF) DATA works as an input.BP 14500 LPERS. & BPC 14500 BANEASA 6 DIAGRAME FUNCTIONALE FUNCTIONAL WAVEFORMS CEN CINTERND im, write = SL ton - www. datasheetcatalog.com RS a INSTR__9 8 8 ’ f ; 9 LSS a SEN INTERN) ia gata wae Fig. 6, Instrucfiuni de scriere (STO, STOC) gi de validare a scrierii (OBN). Simbolul 1" miarcheaz& zouele In care linia DATA functioneaza ca intrare (se citese) ni- vele logice din exteriorul circuitului integrat. Store (STO,STOC) and Output Enable (OBN) instructions ,,"” symbol indicates that DATA works as an input (READ function). 30RP 14500 RPC 14500 CARACTERISTICI ELECTRICE ELECTRICAL CHARACTERISTICS www.datasheetcatalog.com VALOR! iN TOT DOMENIUL DE TEMPERATURA, FARA ALTE SPECIFICATS CONTRARE VALUES OVER OPERATING TEMPERATURE RANGE, UNLESS OTHERWISE SPECIFICATION SEMBOL PARAMBTRI CONDITH DE Test | MIN. TH, MAX. | ONITATE SYMBOL PARAMETERS TEST CONDITIONS | MIN. TYP. MAX. UNITS Vin, | Tensiune de intrare in stare Vecmin 2 v High-level input voltage Vir, | Tensiune de intrare in stare “0"| Vocmin 08 v Low-level input voltage | - —_ 1 — Iyx | Curent de intrare in stare “1” | Vecmax 80 160) A High-level input current Vy= 24 V ‘| Tyr | Curent de intrare cu tensiune | Vr = 5,5 V Vecmaz 08 15) mA | Input current at maximum in- | put voltage Vr= 5.5 V a ~ — i -In, Curent de intrare in stare “0” | Vecmax j 03 08 | ma Low-olevel input current Vy = 04 V Vou | Tensiune de iegire in stare “1” 24° 3.5 v High-level output voltage Vor, | Tensiune de iesire in stare “0” | Vocmin 0.25 04 v Low-level output voltage Io =8 mA Ios | Curent de scurteircuit 1a iegire | Vecmay 4 8 16 mA Short-cireuit output current | Vo — 0 V Joc | Curent de alimentare pe capsulé 30 40 mA Supply current per package —Vrx | Tensiune pe diodele de limitare| 1 18 v Input clamp voltage 3hBP 14500 BPC 14500 CARACTERISTICI DINAMICE DYNAMIC CHARACTERISTICS (Ty = +25°C; Vee = 5.0 V) mor munca = SYMBOL PARAMETERS MAX. UNITS T, Perioada impulsului de tact | ee 14500 | o2 | ows Clock period BPC 14500 5 us twe | Durata impulsului RST | BP 14500 500 ns Reset pulse width BPC 14500 1000 ns tsr ‘Timpul de stabilire a instructiunii SP 14500 400 ns Z Instruction set-up time | ppc 14500 1000 | _ns tar | Timpul de menfinere a instructiunii BP 14500 100 | ns Instruction hold time BPC 14500 200 ns tsp | Timpul de stabilire a datei BP _14500 200 ns Data set-up time BPC 14500 500 ns tap | Timpul de menfinere a datei BP 14500 | 200 | as | Data hold time BPC 14500 500 ms te Timpul de crestere a impulsului 20 ns Pulse rise time te Timpul de cidere a impulsului 20 ns Pulse fall time Ry Sarcina de intrare 50 a Input load Ry Sarcina de iesire vezi fig. 7 Output load see fig. 7 www.datasheetcatalog.com 3aRP 14500 BPC 14500 Fig. 7. Sarcini de iesire Output loads CARACTERISTICI DINAMICE anna DYNAMIC CHARACTERISTICS (‘* = 4 ] | SYMBOL, | PARQUETERS = FIG) MAX. UNITS lary | tun tenn: Timp de propagare de la | gp 14500 8 | 500 st 1—~RR X, la RR | Propagation delay time | | --— from X, to RR | BPC 14500 1500 ag | Timp de propagaredelaX, | gp 14500 9 400 me Ja flaguri Propagation delay time oe tasno | _ from X, to flags BPC 14500 | | 1000 ns | | | | Timp de propagate de la | gp 14500 10 500 ns | X, la DATA Propagation delay time §—§ || | | from X, to DATA BPC 14500 1000 ns tprzi tpnz | Timp de intrare in starea | gp 14500 aby 500 ns X,— DATA de impedanf& ridicata Propagation time to high | ee | impedance state BPC 14500 1000 ns 8 — Circuite integrate logice 33LPRS Oy _BANEASA wa CARACTERISTICE DINAMICE (cont.) DINAMIC CHARACTERISTICS (Ty = +25°C; Vee = 5.0V) BP 14500 BPC 14500 summer, PARAMBTRI mig. rast} wax. | unrriti SYMBOL, PARAMETERS TEST wax. | unees | tyr tpzt, ‘Timp de activare a liniei | gp 14500 500 Ea X,— DATA DATA n Propagation time to active | i state of DATA BPC 14500 1000 ns tena) tpaL: ‘Timp de propagare de la | gp 14500 450 ns X,— WRITE X, la WRITE uM Propagation delay time |__| -——_ from X, to WRITE BPC 14500 1000 ns tem: Timp de propagare de la | pp 14500 500 ns RST 4 RR RST la RR 12 Propagation delay time = |_| -—— from RST to RR BPC 14500 1000 ns tom, : Timp de propagare de la | gp 14500 800 EST — FLF, FLO,| RST Je flaguri 8 32 es RTN, JMP.| Propagation delay time = | et from RST to flags BPC 14500 1000 ns tous tren: Timp de propagare de la | pp 14500 450 ns RST +X, RST la X, 12 Propagation delay time = [———— ———_} from RST to X, BPC 14500 1000 ns toun; tem: ‘Timp de propagare dela X,| gp 14500 500 ms Ba Xi la X, 12 Propagation delay time §— [—————— a from Xq to X; BPC 14500 1000 ns www. datasheetcatalog.comBP 14500 BPE 14500 an --4 ee ithe Xo TT $ X= — ty ane =a oe gy tou ton! Fig. 10 tyra, tpmr,: X, + DATA www. datasheetcatalog.com‘BP 14500 BPC 14500 ' ~ Tr ; \ tour] [ten Fig. 11 Timpi de acces pe linia DATA si iesirea WRITE Acces time to DATA line and WRITE output www.datasheetcatalog.com ks a iy fy ny \ = - sv [rst oxal Vya=art i Pre ee Cee ony ' : eel [toe tytn [ten RR FLAGS 7 . isv tem | Fig. 12 Timpi de propagare de la intririle RST si X, Propegation delay time from RST and X, inputs g)or PPR. Ss. BP 14104 ‘WSS BANEASA | BPC 14104 NUMARATOR DE PROGRAM DE 4 BITI, EXPANDABIL 4-BIT EXPANDABLE PROGRAM COUNTER RST (yp @3 Qs. Og =X OND. MP 117 Conexiuni Pin configuration www. datasheetcatalog.com Oy O5 5 t= neu MUX 4-4 INC ‘ r RIB aay C Eyer Schema bloc Functional block diagram 37BP 14104 TABEL DE ADEVAR TRUTH TABLE | FoNeTIE a S& | Br a FUNCTION 0 0 0 ° NEOPERARE NOP NO OPERATION 0 1 ) 0 | INCREMENT INC 0 x 0 1 APEL DE SUBRUTINA CALL* SUBROUTINE CALL ° x 1 0 | REVENIRE DIN SUBRUTINA RIN® RETURN FROM SUBROUTINE 9 x 1 1 SALT yup JUMP 1 x x x | RESET RST ‘smal P 14104 only www.datasheetcatalog.comPart P. BS. RP 14104 mes BPC 14104 CARACTERISTICI PRINCIPALE BASIC CHARACTERISTICS eras eee Toa vase = arms | AM | RU [tem | rr tea | ‘wurme | ‘gece, |————— (TURE RANGE) FREQUENCY | MIN, MAX. BP 14104 MP 117 —40°C = 485°C 1 MHz 45 55 : BPC 14104 MP 117 —10°C + +70°C 200 kHz 4.75 5.25 www.datasheetcatalog.comBP 14104 BPC 14104 www.datasheetcatalog.com DESCRIERE GENERALA Circuitele integrate @P 14104, BPC 14104 joaca rolul de numérator de program in sche- mele de automate programabile coustruite cu seria 14000, Ele au lungimea cuvintului de 4 biti si pot fi legate mai multe in serie, pentru obfinerea unui numiritor de program extins de 8, 12, 16... biti Dupi cum se vede si in tabelul de adevar, numiritorn! de program are mai multe fanctii selectate cu ajutorul intririlor JS gi RT: @ funcfia de numarator sineron de 4 bifi cu transport Cn, Cn44; ©@ funcfia de salt la adresi dati (JMP); @ funcfia de apel de subratin’ (CALLJRTN, numai BP 14104) Se pot efectua apeluri de subrutina in cniburi pe coud nivele Circuitele integrate BP 14104, BPC 14104 contin (vezi schema bloc) un’ registru de 4 bistabili ,,D", PC. Acestia se incarcd pe fie- care front creseator al tactului X,, ca un cuvint de 4 biti selectat de multiplexorul MUX. Yn functie de starea intririlor de control JS si RT, cuvintul (Q, Q, Q, Qj)a incarcat la momentul tn poate fi: @ (2,0:0,00)u = (25020,20) a1 + Ca Daci JS=0 si RT=0, registrul PC Iucreazt ca numiritor binar de 4 bifi, cu transport Ca Coty. Tesirea Cay, este activa (Ca. cind ; 1") atunei Ca=Qo=01:= == @ (0,0:0,00)0 =(TaleliTe)na si (RARgRyRo)a =(Qs020:00)n—a Daca JS=1 si RT=0 registrul PC memoreaz’ cuvintul de 4 biti aplicat pe intrarile paralele TyIqljIy, iar unul din registrele RT,, RT, me- moreaza starea anterioari a registrului PC. Aceast_operatie are semnifieajia de APEL DE SUBRUTINA (CALL), a carei adresi de Program s-a specificat la intrarile I,I.1[y. Dou apeluri succesive de subrutina’ incarcd ambele registre RT,, RT, cu adresele curente (Q:2,0,9,). De exemplu, in cazul wnor apeluri la momentele ta $i teyp (1,P=1,2,3...) confinutul registrelor, 4@ GENERAL DESCRIPTION BP 14104 and BPC 14104 integrated circuits have the function of program counter in the programmable logic controllers builded with 14000 series. They have a 4-bit word Jengh and may be conected in a scrial mode, to obtain an extended 8, 12, 16... bit program counter. As can be seen in the truth table, the program counter has many functions, selected with JS and RT control inputs: © 4-bit synchrouns counter, with carry (Cn, Cn44); © JUMP ‘function, to a specified adress; @ SUBRUTINE CALL function (CALL/RTN, BP 14104 only). It is possible to call two level nested subrouti- nes, BP 14104 and BPC 14104 integrated cir- cuits contain (see the functional block diagram) a4 — "D” latches register, PC. The PC register is loaded on each loading edge of X, clock, with a 4-bit word selected by a multiplexer (QU). Depending on the logic state of JS and RT control inputs, the word (0,0,0,Q,)n loaded at ta moment can be © (2:9:9,9)a = (Q:2:2,00)n4 + Ca If JS=0 and RT=0, the PC register works as a 4-bit binary counter, with carry Cn, Casa. Case Output is in high state if: © (0,0,0,0.)n =GsE10))n and (RaReRiRo)a =(0s920100) aa If JS=1 and RT=0, PC register memories the 4-bit word applied to the parallel inputs I,1,L1, and one of RT, RT, register memories the ancient state of PC register ‘This operation signifies a SUBROUTINE, CALL, wich program adress is specified to the I,I,l,Ig inputs. Two suceesives subroutine calls load both RT, and RT, registers with current adresses (0,0,0,0,). For exemple, in the case of two calls at ta and ta,p moments (a,p= 12,3...) the content of PC, RT, andBP 14104 BPC 14104 PC, RT, si RT, devine: PC : (Q:Q:0,00)n = (stahTe)a—1i (Q:2:0,2)n+p = st tTo)nep—a RY: (RIRRERDaep = (2,2,0,0) espa RT: (RERIRIRG) agp = (Q3Q2Q:Qe) a1 Cele dona registre RT, si RT, permit executa- rea unor cuiburi de subrutine pe dowa nivele. @ (Q:0:0,0.)a=(RsRsRiRo) Daci JS=0 si RT=1 registrul PC incarcad adresa ultimului apel de subrutina. Aceasté ieatia de REVENIRE DIN Dou reveniri consecutive incarci mai intii ultima adresi de apel (ailata de exemplu in RT) si apoi penultima adrest (confinuta in celalait registra, RTs) Selectarea incircarii in (din) cele doua registre RT, RT, este facut’ de blocul de control (CTRL), care confine un bistabil “T” (indicator de stivé de 1 bit) pentru memorarea nivelului de subrutina. Schimbarea stiri acestuia se face dupit executa~ rea fiecirei instructiuni de apel de subruting (CALL) sau de revenire (RT), pe frontul c&zitor al tactului X,. © (2:0:0,90)n = Cale Tiaa Daci JS=1 si RT=1 registrul PC memoreazd cuvintul aflat la intrarile paralele IyIgl,Iy. Registrele RT,, RT, si indicatorul de stiva isi conservi. starea, Aceasti operatic are semnificatia de SALT simplu (JMP) la o adresi de program dati. Daca intrarea RST este in starea “1”, registrul PC este adus la zero: Qo = Q1 — 2 = Qs Cae = 0 RT, registers becomes as follows: PC : (Q,2:2,2))n = RT,: PC : (Q,0,0,0.) TsTelilo)nipa RT, : (RERARIRD ap = (0,0:0,00)aipa RT, : (RERIRRay p = (2.2QQ)na The two registers RT, and RT, allow the execution of two levels nested subroutines. © (Q,0,0,00)n=(RsRoR,Ra) If JS=0 and RT=1 the PC register is loaded with last subroutine call adress. This operation signifies a RETURN FROM SUBROUTINE (RTN). Two consecutive return operations primary load the last call adress (memorised, let’s say in RT,) and secondary the last but one adress (memorised in the other register, RT). ‘The loading select in to (irom) the two registers RT, RT, is made by a control block (CTRL), which contains a “T” latch (1-bit stack pointer) to memories the subroutine level. ‘The stack pointer logic state changes after the execution of each CALL or RETURN instruction, on the falling edge of X, clock © (Q:0:0,Q0)n = FtetiTona If JS=1 and RT=1 the PC register memories the word applied to the parallel inputs I,1,L,[y. RT,, RT, registers and the stack pointer keep their state unchanged. This operation signifies a JUMP (JMP) to a specified program adress. If RST input is in high state, PC re; in the low state: 0-21-21 =D =Car ter falls www.datasheetcatalog.com 41BP 14104 BPC 14104 CARACTERISTICT ELECTRIC ELECTRICAL CHARACTERISTICS www. datasheetcatalog.com BANEASA VALORI N TOT DOMEMUL DE;TEMPERATURA, FARK ALTE SPRCIFICATIE CONTRARE VALUES OVER OPERATING TEMPERATURE RANGE, UNLESS OTHERWISE SPECIFICATION sIMROL, PARAMETRE | conprr pe test | aux. vir, max. | usrriqe SYMBOL PARAMETERS ‘TEST CONDITIONS | MIN. TYP. MAX. | UNITS Vin | Tensiune de intrare in stare “1” | Vee min a v High-level input voltage Viz, | Tensiune de intrare in stare "0" | Vcc min 08 v Low-level input voltage Tra | Curent de intrare in stare “1” | Vec max 80 160] pA High-level input current Vp=24V Typ | Curent de intrare eu tensiune Vp=55 0 Input current at maximum in- put voltage 08 15) mA Curent de intrare in stare “0” | Vec max 03 08 | ma ‘Low-level input current Vou | Tensiune de iegire in stare “ 24 38 v High-level output voltage Vor, | Tensiune de iegire in stare “0 | Vcc in 0.25 04 v Low-level output voltage Ip=8 mA —Ios | Curent de seurtcireuit la iegire | Voc max, 4 8 16 | ma Short-circuit output current | Vy=0V Ice | Curent de alimentare pe capsuli| Vecmaz 200 «40 mA Supply current per package —Vyx | Tensiune pe diodele de limitare] Voc min 1 18 v Input clamp voltage —Ir= 10 mA 426B Gig BP 14104 Wid pANeasa www.datasheetcatalog.com BPC 14104 CARACTERISTICI DINAMICE DYNAMIC CHARACTERISTICS (Ty = +25°C; Vee 5.0 V) CONDITIT DE TEST TEST CONDITIONS simnon PARAMETRI max. | UNITATI SYMBOL PARAMETERS max. | Units Tx | Perioada impulsului de tact BP 14104 2 Bs eee Clock period BPC 14104 5 ps twr Durata impulsului RST eP 14104 500 ns RST pulse width PC 14104 1000 | __ ns ts: ‘Timpol de stabitire;pentra CIy...1, | BP 14104 400 ns | Settmp timettor C. To.-Ts BPC 14104 1000 | ns tar _| Timpul de menfinere pentru C, Ip...1, | PP 14104 | 0 ns | Hold time for C, Ip..-Ts |_pPC 14104 |__100 ns toe | Timpul de stabilire pentru JS, RT BR 14104 |__400 ns Set-up time for JS, RT BPC 14104 1000 tap ‘Timpul de menfinere pentru JS, RT fe 14104 150 | __| Hold time for JS, RT BPC 14104 | 300 ms te Timpul de erestere a impulsului 20 s Pulse rise time | r ; A | i te ‘Timpul de cddere a impulsului |} 20 as | Pulse fall time | | Ry Sarcina de intrare | 50 Qa | Input load | | cy, Sarcina de iegire ee pF Output loadRP 14104 EP. Res. ry BPC 14104 BANEASA ws www.datasheetcatalog.com_ CARACTERISTICI DINAMICE DYNAMIC CHARACTERISTICS (Ty, = +25°C; Vec = 5.0 V) |. 4 7 simnoL PARAMETRI WIG. TEST) MAX. | UNITATI SYMBOL PARAMETERS TEST. FIG) MAX, | UNITS _ l tern: tpn: Timp de propagare de | X,+05,0, | ta X la Oy... O, Q:,9, | Propagation delay time | from X, to Q, | \_ © Sincronizare cu Ty, BP 14104 | 13 500 ns Synchro with I | |_—_—— PC 14104 1000 na | | @ Sincrouizare cu JS, ep ioe | ot 500 | ns RT - | | aL BPC 14104 1000 ns or ‘Timp de propagare de Pp 14104 15 500 ~ 8 SE Ou Oe | ig RST In Qs == Qs. Care |” ° im Propagation delay time OO from RST to Q,--. Qs, Cave BPC 14104 1000 ns t 3 ty ' ay ope Timp de propagare dela BP 14104 16 500 ns a Cota Propagation delay time from Cy to rom Ca to Care BPC 14104 1000 | nsBP 14104 BPC 14104 Kerry LAPLH Lied Fig. 13 tpy, tpun: Xi Qe --. Qu Sincronizare cu I, Synchro with I,. www.datasheetcatalog.com mn Fig. 14 tor, tpar,: X1 + Qe---Qs, Sincronizare cu JS, RT Synchro with JS, RT Fig. 15 typ? RST + Qe Qy, Qe Qe Case aBP 14104 BPC 14104 Fig. 16 tpyz, tpen,! Cn + Cane www. datasheetcatalog.comBo: PRS BP 43 fd DANEASA BPC 14113 ww. ). datasheetcatalog. com ee DEMULTIPLEXOR 1:3 CU MEMORIE 1 TO 8 DEMULTIPLEXER WITH MEMORY ct 05 06 a7 Ae AL OA? fiefs} fa} Hae a3 a2 a1 ap RST Xt GND X\ MP 117 Conexiuni Pin configuration DON'T CARE UNCHANGED {POSITIVE TRANSION, aaBP 14113 BPC 14113 CARACTERISTICL PRINCIPALE BASIC CHARACTERISTICS y — PRS. Fy _BANEASA 4) Gama Teme, pe | PRECYENTA bE uP CAPSULA PUNCTIONARE wie Vea") nr FACKAGE orneatixe erect TEMPERATURE RANGE) FREQUENCY MIN, = MAN. ep 14113 MP 117 —40°C = +85°C 1 MHz | 45 55 | ePc 14113 MP 117 —10°C + 470°C 200 kits | 4.75 5.25 DESCRIERE GENERALA GENERAL DESCRIPTION Cireuitele integrate BP 14113, BPC 14113 GP 14113 and BPC 14113 integrated cit- joaci rolul de interfatA de iesire in schemele de automate programabile construite cu seria 14000. Dupa cum se vede gi in schema bloc, ele contin un decoder “I din 8”, care permite, in funepie de intrarile de adres. . Ao, increarea unuia din cei 8 bistabili “D" cu starea logica a intrarii D. fnc&rcarea datei se face dupa fixarea adresei de selectie (cu intrarile Ag, Ay, A,). pe frontul crescitor al tactului X,. Intrarea RST, activa in starea "1" reseteazd tofi cei 8 bistabili "D": O,=0, Qr=0. www. datasheetcatalog.com 48 cuits have the function of ontput interface in the programmable logic controllers builded with 14000 serie. As can be seen in the functional block diagram ‘they contain an “1 fron 8” decoder, wich ena- bles, depending on A,, A,, A» adress inpnts, one of the 8 “D” flip-flops to be loaded with the logic state of D input. Data is loaded after the select adress setting-up on the loading edge of X, clock. The RST inpat, active in all the 8 “D* flip-tlops: Q. igh-state, clearsaoe wh BANEASA CARACTERISTICI ELECTRICE ELECTRICAL CHARACTERISTICS www.datasheetcatalog.com RP BPC VALORI IN TOT DOMENIUL DE TEMPERATURA, FARA ALTE SPECIFICATII CONTRARE VALUES OVER OPERATING TEMPERATURE RANGE, UNLESS OTHERWISE STECIFICATION 14113 14113 | Hish-tevel output voltage sminon PARAMETRI ITH DR TEST | MIN, THR, MAX. | UNITATI SYMBOL PARAMETERS | mpsrconpirioss | mix, TYP, MAX, | UNrTs | Vaz | ‘Tensiune de intrare in stare““1”| Vee min | 2 v | High-level input voltage | | t —_ _ __| __| Vy, | Tensiune de intrare in stare “0” | Vec mia | 08 Vv | Low-level input voltage | Vin | Curent de intrare in stare “1” | Voc max | 80 160] 4A High-level input current | vV=24v | — a —| pe x | Curent de intrare cu tensiune | | Vy =55 V | Vee mex 08 15] mA Input current at maximum input} Vy = 5.5 V voltage | Curent de intrare stare “ 0.3 08 mA Low-level input current v Vox | ‘ensiune de fesire in stare “1” 24 35 Input clamp voltage —Ty'= 10 ms 4 — Cirevite integrate logice “ Voy,” | Tensiune de iegire in stare “0” 02s 04 v | nuw-level output voitage | _— i - Tos | Curent de scurtcireuit ta fegire | Veo mox 4 8 6 mA | Short-circuit output current | Vy =0°'V Tce | Curent de alimentare pe capsula! V 20 30 mA Supply current per package Vix | Tensiune pe diodele de limitare) Vee miu 1 18 v