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VLSI Physical Design - Week 0 Questions

The document outlines the Week 0 assignment for the NPTEL VLSI Physical Design course, including various questions related to digital logic design and circuit implementation. It includes questions on functional completeness of gates, minimum NAND gates for a function, and factors affecting circuit delay. Additionally, it addresses topics such as memory addressing and characteristics of CMOS technology.

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I.Vivek Anand ECE
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18 views3 pages

VLSI Physical Design - Week 0 Questions

The document outlines the Week 0 assignment for the NPTEL VLSI Physical Design course, including various questions related to digital logic design and circuit implementation. It includes questions on functional completeness of gates, minimum NAND gates for a function, and factors affecting circuit delay. Additionally, it addresses topics such as memory addressing and characteristics of CMOS technology.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1/18/25, 11:44 AM VLSI Physical Design - - Unit 3 - Week 0

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(https://swayam.gov.in)
(https://swayam.gov.in/nc_details/NPTEL)

NPTEL (https://swayam.gov.in/explorer?ncCode=NPTEL) » VLSI Physical Design (course)

Announcements (announcements) About the Course (preview) Q&A (forum) Progress (student/home) Mentor (student/mentor)

Mentee List (student/mentee) Review Assignment (assignment_review) Course Recommendations (/course_recommendations)


Click to register for
Certification exam

Week 0: Assignment 0
(https://examform.nptel.ac.in/2025_01/exam_form/dashboard)

If already registered, click Assignment not submitted

to check your payment 1) Which of the following set of gates is/are functionally complete? 1 point
status
a. {AND, OR}
b. {NAND}
c. {EXOR}
Course outline
d. {NOT}

About NPTEL ()
2) What is the minimum number of 2-input NAND gates required to realize a 4-input NAND function? 1 point

a. 3

https://onlinecourses.nptel.ac.in/noc25_cs73/unit?unit=16&assessment=242 1/3
1/18/25, 11:44 AM VLSI Physical Design - - Unit 3 - Week 0

How does an NPTEL b. 4


online course work? () c. 5
d. 6
Week 0 ()
3) The number of full adders required to implement an 8-bit ripple-carry adder is __________
Practice: Week 0:
Assignment 0
(assessment? 1 point
name=242)
4) On what factors does the delay of a combinational circuit depend? 1 point
Week 1 ()
a. The number of gates in the circuit.
b. The number of gate levels.
c. The frequency of the clock.
d. None of these.

5) Without using any additional gates, which of the following switching functions can be realized by a 2-to-1 multiplexer? 1 point

a. NOT
b. AND
c. OR
d. EXOR

6) Consider a 1 Kbyte byte-addressable memory. How many address lines will be there? 1 point

a. 8
b. 16
c. 10
d. 24

7) For a 3-input NOR gate realization using CMOS technology, the total number of MOS transistors required will be _____________.

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1/18/25, 11:44 AM VLSI Physical Design - - Unit 3 - Week 0

1 point

8) For a CMOS gate, the rise time at the output will depend on: 1 point

a. The effective resistance of the pull-up network.


b. The effective resistance of the pull-down network.
c. The total capacitive load the output is driving.
d. All of these.

9) For a J-K flip-flop, if we apply logic 1 to both J and K inputs, and feed a 256 Hz rectangular periodic signal to the clock input, the
frequency of the signal generated at the output Q will be ___________ Hz.

1 point

10) Which of the following statement(s) is/are true? 1 point

a. FGPA based design takes less design effort as compared to ASIC design.
b. FPGA based designs are faster than ASIC implementations.
c. FPGA based design can be carried out on-site whereas ASIC design requires fabrication.
d. All of these.

Check Answers and Submit

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