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Practice Sheet 5

This document is a practice sheet focused on latches, flip-flops, and sequential circuits, containing various exercises such as completing timing diagrams, deriving characteristic tables, and designing counters. It covers the conversion of flip-flops, the construction of shift registers, and the design of state machines for specific input sequences. The exercises require knowledge of digital logic design and sequential circuit behavior.

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khanjan010106
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2 views

Practice Sheet 5

This document is a practice sheet focused on latches, flip-flops, and sequential circuits, containing various exercises such as completing timing diagrams, deriving characteristic tables, and designing counters. It covers the conversion of flip-flops, the construction of shift registers, and the design of state machines for specific input sequences. The exercises require knowledge of digital logic design and sequential circuit behavior.

Uploaded by

khanjan010106
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PRACTICE SHEET 5

Latches, Flip flops, Synchronous and Asynchronous Sequential Circuits


1. Complete the timing diagram for a falling-edge-triggered J − K FF for the following two
cases:
(a) Assume Q begins at 0.
(b) Assume Q begins at 1.

2. Complete the timing diagram by finding the input for a rising-edge-triggered D FF and T
FF that would produce the output Q as shown.

3. Can a cross-coupled 2-input XOR gate configuration function as an S-R latch? Justify
with reasons. Repeat the same exercise for cross coupled 2-input XNOR gate
configuration. For both cases, assume that there is no provision of asynchronous set/reset.

4. What is the function table for the feedback circuit shown below where X, Y are inputs
and Q, P are outputs?
5. For the input waveforms CLK and Din as shown, plot:
(a) QM and QS for the circuit a
(b) QM and QS for the circuit b

6. Derive the characteristic table, excitation table, truth table, characteristic equation and
state diagram for S − R, D, J − K and T FFs.

7. Convert an S − R FF into:
(a) D FF
(b) J − K FF
(c) T FF

8. Convert a D FF into:
(a) S − R FF
(b) J − K FF
(c) T FF

9. Convert a J − K FF into:
(a) S − R FF
(b) D FF
(c) T FF
10. Design a 2-bit counter that will count in the following sequence: 00,11,10,01, and repeat.
Using T flip-flops:
(a) Draw a state diagram.
(b) Derive a state table.
(c) Implement the circuit.

11. Construct the following using J − K flip-flops:


(a) a 4-bit Johnson counter
(b) a 4-bit Parallel-in Parallel-Out register

12. A 4-bit universal shift register has its functionality decided by the control signals S1 and
S0. When S1S0 = 00, the register retains its previous state. When S1S0 = 01, the register
multiplies its contents by 2. When S1S0 = 10, the register divides its contents by 2. When
S1S0 = 11, the register loads a new 4-bit data. Design such a universal shift register using
flip-flops and combinational circuits, if it treats its stored contents as an:
(a) unsigned number
(b) two’s complement number

13. Design a counter that counts in the following sequence: 1, 5, 9, 11, 13,15, (repeat) 1, 5, . .
14. Design a 5-bit binary counter that counts up only in:
(a) Even numbers (0, 2, 4, 6, 8, . . .)
(b) Odd numbers (1, 3, 5, 7, 9, . . .)

15. Along input sequence enters a one-input one-output synchronous sequential circuit, that is
required to produce an output symbol z = 1 whenever the sequence 1111 occurs.
Overlapping sequences are accepted; for example, if the input sequence is 01011111. . .,
the required output sequence is 00000011. . ..
(a) Draw the state diagram.
(b) Draw the state table.
(c) Show the state encoding which you have adopted.
(d) Draw the corresponding logic diagram using D flipflop

16. A long input sequence enters a one-input one-output synchronous sequential


circuit, that is required to produce an output symbol z = 1
whenever the sequence 0101 occurs. Overlapping sequences are accepted.
(a) Draw the state diagram.
(b) Draw the state table.
(c) Draw the corresponding logic diagram using D flip-flops.
17. Show how a mod 16 counter works as a frequency divider using a timing diagram.
18. How can we construct a mode 28 counter by cascading counters.

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