VLSI DESIGN COURSE FILE

Contents:
1. Cover Page – ALIET/7.5.1/FT 01

2. Status Papers - ALIET/7.5.1/FT 02

3. Guidelines to study the subject - ALIET/7.5.1/FT 03

4. Course objectives and outcomes - ALIET/7.5.1/FT 04

5. Course schedule - ALIET/7.5.1/FT 05

6. Schedule of instructions – Unit wise ALIET/7.5.1/FT 06

7. Course completion status -- ALIET/7.5.1/FT 07

8. Record of tutorial class conducted, if any -- ALIET/7.5.1/FT 08

9. Lesson plan(Instructional Learning Outcomes) -- ALIET/7.5.1/FT 09

10. Lesson notes -- ALIET/7.5.1/FT 10

11. Class Time Table -- ALIET/7.5.1/FT 12

12. Individual Time Table -- ALIET/7.5.1/FT 13

ADDITIONAL DOCUMENTS LIST:

1. Syllabus copy

2. Academic Calendar (University and Department)

3. PEOs and POs

4. Mapping tables: CEOs with Cos and Cos with POs.

5. Brief note on the importance of the course.

6. Detailed notes

7. Additional topics

8. University Question papers of previous years

 9. Assignment topics

10. Unit wise Questions

11. Tutorial problems, if any

12. References, Journals, websites and E-links

13. Mid & Weekly question papers.

14. Scheme of Evaluation.

15.CO PO ATTAINMENTS

16.OPEN BOOK ASSIGNMENTS

17.WORKSHOP CONDUCTED(IF ANY)

18. Quality measurement sheets

a) Course exit (end) survey

b) Teaching evaluation ( ASSESMENT SHEET)

 ALIET/7.5.1/FT 01

COURSE PLAN (COURSE FILES) – EACH FILE / SUBJECT / SECTION

Department: ……ECE
Name of the Faculty: RAVI.GORAPUDIYear : …III…………Sem: …II……..
Designation: …ASST. PROFESSOR……………Name of the Program:……B.TECH………………
Title of the subject: VLSI DESIGN Subject code: R2032042
No.of Students: ……129……………….

Note to faculty members on how to use this course file format

1. Get a new file from your office for each course and file each sheet of these formats as and when it is
complete
2. Individual Time Table and Syllabus copies provided to you shall also be filed in it.
3. Please attach the Marks list of the students in respect of ( Continuous Assessment Exams) for this
subject in your course file
4. Photo copy of the best and the worst answer sheets for ( Continuous Assessment Exams), be included
in the file
5. List of Assignments / Seminar Topics you have given to the students should also included in the course
file
6. Model Question Paper, which you have distributed to the students in the beginning of the Semester for
the subject should be included in the file
7. Any additional resources like OHP transparencies, handouts used also to be filed

Faculty / Date HOD/ Date

 4.STATUS PAPER ALIET/7.5.1/FT 02

1. TARGET

a) Percentage Pass : 100 b) Percentage I Class : 75

2. COURSE PLAN

To be attached

3. METHOD OF EVALUATION

a) Continuous Assessment Examinations

b) Assignments/ Weekly test
d) Quiz
e) Term End Examination

4. List out any new topic(s) or any innovations you would like to introduce in
teaching the subject in this semester.

1. PPT
2. Weekly tests in addition to mid semester exam.
 5. GUIDELINES TO STUDY THE SUBJECT ALIET/7.5.1/FT 03

Guidelines to Study the subject:

 Refer to the text books and Internet.

 Preparing notes with examples and numerical.
 Look at university question papers and cover the topics if any were missed earlier.
 7.COURSE OBJECTIVES, OUTCOMES ALIET/7.5.1/FT 04

Course Objectives:
1. Understand the various fabrication steps of IC and come across basic
electrical properties of MOSFET..
2. Apply the Concept of design rules during the layout of a circuit..
3. Understand the Sheet Resistance, Capacitance and how to scale MOS
transistors.
4. Understand the Protection and testing of Circuits .
5. Understand various Architectures of various FPGAs ..

Course outcomes:

C323 VLSI Design

students will be able to Understand the properties of MOS active devices and simple
C323. circuits configured when using them and the reason for such encumbrances as ratio rules
1 by which circuits can be interconnected in silicon.

C323. students will able to know three sets of design rules with which nMOS and CMOS
2 designs are fabricated and various Layouts
students will able to understand the basic circuit concepts and scaling factors
C323.
determining the characteristics and performance of MOS circuits in silicon
3

C323. Students will be able to discuss about the ESD Protection, input and output circuits and
4 understand the concepts of Design for Testability.
students will able to classify the various FPGA building block architectures and their
C323. families along with introduction to Synthesis.
5
 ALIET/7.5.1/FT 05
10 COURSE SCHEDULE
Department: ECE
Name of the Faculty : RAVI GORAPUDI Year : III ECE Sem:II
Title of the subject: VLSI DESIGN Subject code: R2032042

The Schedule for the whole Course / Subject is:ECE-1

Sl Description Duration (Date) Total No.of
From To Periods
1 Introduction & Basic Electrical Properties of
9-1-2023 23-2-2023 20
MOS and Bi-CMOS Circuits
2 Basic Circuit Concepts & Scaling of MOS
24-2-23 17-3-2023 08
Circuits
3 Basic building blocks of analog IC design
20-3-2023 28-3-2023 06

4 CMOS combinational and sequential logic

29-3-2023 15-4-2023 07
circuit design
5 FPGA Design and advanced technologies 17-4-2023 29-4-2023 08

Total No. Of instructional periods available for the course: 49 Periods

Faculty / Date
 ALIET/7.5.1/FT 06
Schedule of instructions – Unit wise

Name of the faculty : RAVI.GORAPUDI Academic Year: 2022-23

Course Name : VLSI DESIGN
Program : B.Tech
Branch : III ECE Semester : EVEN
Unit Total Date Of Taken
Sl No. No. of Object Reference
No perio Topics covered ive text book
Teaching Aids
ds No.
INTRODUCTION AND BASIC 1 T1:1-4 C&B
9-01-2023 ELECTRICAL PROPERTIES OF MOS
1 CIRCUITS: Introduction to IC Technology
Fabrication Process: nmos 1 T1:4-5 PPT
2 9-01-2023
Pmos fabrication 1 T1:6 C&B
3 30-01-2023
cmos fabrication 1 T1: 7-9 PPT
4 31-01-2023
14-02-2023 Ids vsVds relationships 1 T2:38 C&B
5
Aspects of Mos transistor ,Threshold T1:9-18
14-02-2023 C&B
6 Voltage(Vt) 1
Pull up to Pull down ratio for nmos inverter T1:28-33
9-01-2023 C&B
7 I driven by another nmos inverter 1
Pull up to Pull down ratio through one or T1:33-34
11-02-2023 more transistors C&B
T1:40-43
8 1
20
11-02-2023 Alternative form of pull up. T1:36 C&B
9 1
20-02-2023 CMOS inverter T1:43-46 C&B
10 1
20-02-2023 Latch up in CMOS inverter T1:43-46 C&B
11 1
21-02-2023 Bi- CMOS fabrication T1:47-48 C&B
12 1
21-02-2023 Bi-CMOS inverter T1:48-50 C&B
13 1
22-02-2023 Comparision of cmos and bi-cmos transistors T1:50-54 C&B
14 1
MOS & BICMOS CIRCUIT DESIGN T1:55-65
22-2-23 C&B
15 PROCESS: Mos layers 2
Stick Diagrams T1:65-71 PPT
16 22-2-23 2
Design rules& layout,general observation on T1:73-75 PPT
23-2-23
17 the design rules 2
2um double metal,double poly 2 T1:75-76 PPT
18 23-2-23
1.2um double metal,double poly cmos rules 2 T1:76 C&B
19 23-2-23
Layout diagram for NOR gates. T1:80 C&B
20 23-2-23 2
II 08 BASIC CIRCUIT CONCEPTS: sheet T1:86-89 C&B
24-2-23 resistance 3
21
Sheet resistance concept applied to MOS T1:89-93
24-2-23 C&B
22 transistor & Inverters 3
23 24-2-23 Area capacitance of layers 3 T1:93-98 C&B
24 25-2-23 Delay unit, inverter delays 3 T1:108-110 C&B
25 25-2-23 Driving large capacitance loads 3 T1:135 C&B
Scaling of MOS circuits : scaling models and 3 T1:136-148
28-2-23 C&B
26 scaling factors
27 28-2-23 Scaling factors for device parameters 3 T1:136-138 C&B
28 7-3-23 Limitations of scaling 3 T1:138-142 C&B
29 14-3-23 Switch logic 3 T1:143-146 C&B
30 17-3-23 gate logic 3 T1:148-152 C&B

BASIC BUILDING BLOCKS OF 4 T2:134 C&B

20-3-23
31 ANALOG IC DESIGN
21-3-23 Body effect T2:134-145 C&B
32 4
Current mirror 4 T2:134-145
24-3-23 C&B
33
Cs amplifier 4 T2:145-154
25-3-23 C&B
34
27-3-23 Cd amplier 4 T2:145-154 C&B
35
Cg amplifier 4 T2:151-162

29-3-23 C&B

36 III 06
IV CMOS COMBINATIONAL AND 4 RT1:63 C&B
SEQUENTIAL LOGIC CIRCUIT
DESIGN
Ratioed logic 4 RT1:63 C&B
37 29-3-23
Static logic 4 RT1:63 C&B
38 29-4-23
07 1-4-23 Examples 4 RT1:63 C&B
39
Dynamic logic 4 RT1:63 C&B
40 10-4-23
Mux based latches 4 RT1:63 C&B
41 11-4-23
Clocked cmos registers 4 RT1:63 C&B
42 14-4-23
Nand/nor based latches 4 RT1:63 C&B
43 15-4-23
V 08 FPGA DESIGN: FPGA design flow RT1:63-74
5 C&B
44
17-4-23 Basic FPGA architecture,FPGA technologies 5 RT1:64-67 C&B
45
18-4-23 FPGA families-Altera flex 8000 FPGA 5 RT1:67-70 C&B
46
19-4-23 Fpga families 5 RT1:70-73 C&B
47
21-4-23 Fpga families 5 RT1:70-73 C&B
48
24-4-23 Design flow 5 RT1:70-73 C&B
49
25-4-23 T-FET 5 RT1:70-73 C&B
50
51 27-4-23 Finfet 5 RT1:70-73 C&B
 29-4-23 Short channel effects 5 RT1:70-73 C&B
52

C & B : CHALK & BOARD, PPT: POWER POINT PRESENTATION.

TEXT BOOKS

T1:Essentials of VLSI Circuits and Systems By Kamran Eshraghian, Douglas and A. Pucknell and
Sholeh Eshraghian, Prentice-Hall of India Private Limited,2005 Edition.
T2: CMOS Digital Integrated Circuits Analysis and Design- Sung-Mo Kang, Yusuf
Leblebici, Tata McGraw-Hill Education, 2003.

REFERENCES

1. Advanced Digital Design with the Verilog HDL, Michael D.Ciletti, Xilinx Design
Series, Pearson Education.
2. Analysis and Design of Digital Integrated Circuits in Deep submicron
Technology, 3’rd edition, David Hodges.

ALIET/7.5.1/FT 07
12. COURSE COMPLETION STATUS
Department: ECE
Name of the Faculty : RAVI.GORAPUDI Year : III ECE Sem: II
Title of the subject: VLSI DESIGN Subject code: R2032042

Actual date of completion and remarks in any, :

Unit Remarks No of Objectives

achieved
1 Completed each unit as planned at the beginning of 1( COB 1)
the semester
2 Completed each unit as planned at the beginning of 1( COB 2)
the semester
3 Completed each unit as planned at the beginning of 2( COB 3& 4)
the semester
4 Completed each unit as planned at the beginning of 2( COB 2&4)
the semester
5 Completed each unit as planned at the beginning of 2( COB 5 &6)
the semester
Note: After completion of each unit, mention the no of objectives achieved

Faculty / Date

ALIET/7.5.1/FT 08

13.RECORD OF TUTORIAL CLASS CONDUCTED

Department: ECE
Name of the Faculty : RAVI.GORAPUDI Year : III ECE Sem: II
Title of the subject: VLSI DESIGN Subject code: R2032042
This tutorial correspondents to Unit No’s : 1 to 6.

NO CLASS CONDUCTED
----------------------------------------------------------------------------------------------------------------------------------------

ALIET/7.5.1/FT 09
14.LESSON PLAN
Department: ECE Date: ………………
Title of the subject :VLSI DESIGN Subject code: R2032042
Lesson Number: 1-5……Lesson Title : ……………………………………Duration : …6 months………..

On completion of this lesson the student should be able to Understood

UNIT-1:
1. MOS fabrication models and different available MOS devices can be viewed. Evolution of
IC technology.
2. Moore’s law, Bi-CMOS nature & its operation.
3. Comparison b/w CMOS technology, Bi-CMOS technology regarding size, power, speed
trade off etc.
4. Different problems evolved in MOS structure and Bi-CMOS
5. Latch-up Problem in CMOS & Bi-CMOS.
6. To increase the speed, alternative forms of pull up for CMOS logic.
UNIT-2:
1. An insight into the Methods and means for manufacturing the circuit through Stick & Layout
Representation.
2. How to evaluate a logic equation for fabrication it into the real time application.
3. Design rules issued presently in the analog design market.

UNIT-3:
1. Wiring up circuits takes place through the various conductible layers which are provided by MOS
processing.
2. Able to calculate the total internal RC delays offered by the different Capacitance which are
evaluated in fabrication model.
3. Able to know how to reduce the RC delay and speed up the Analog Process.
4. Fabrication is still in the process of evolution which is leading to reduce in size & High
packaging density.
5. Able to know the basic scaling models which are present trends.
6. Able to view after scaling about MOS device’s behavior.

UNIT-4:

UNIT-5:
 1. Able to get the knowledge about FPGA Devices.
2. Able to identify various synthesis tolls used.
.

TEACHING AIDS: Black Board

TEACHING POINTS: 10

Faculty/Date

ALIET/7.5.1/FT 13
15.CLASS TIME TABLE
Faculty / Date

ALIET
/7.5.1/FT 13
11. INDIVIDUAL FACULTY TIME-TABLE
Department: ECE
Name of the Faculty : RAVI.GORAPUDI Year : III ECE Sem: II
Academic Year : 2020-21

Faculty / Date

1. SYLLABUS

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA

III Year B.Tech. ECE. II-Sem
 VLSI DESIGN

Unit-I:
Introduction : Introduction to IC Technology, MOS and related VLSI Technology, Basic MOS
Transistors, Enhancement and Depletion modes of transistor action, IC production process, MOS
and CMOS Fabrication processes, BiCMOS Technology, Comparison between CMOS and Bipolar
technologies.
Basic Electrical Properties Of MOS and Bi-CMOS Circuits: Ids versus Vds Relationships,
Aspects of MOS transistor Threshold Voltage, MOS transistor Trans, Output Conductance and
Figure of Merit. The Pass transistor, NMOS Inverter, Pull-up to Pull-down Ratio for NMOS
inverter driven by another NMOS inverter. Alternative forms of pull-up, The CMOS Inverter, MOS
transistor circuit model, Bi-CMOS Inverter, Latch-up in CMOS circuits and BiCMOS Latch-up
Susceptibility.
MOS and Bi-CMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and
Layout, General observations on the Design rules, 2μm Double Metal, Double Poly,
CMOS/BiCMOS rules, 1.2μm Double Metal, Double Poly CMOS rules, Layout Diagrams of
NAND and NOR gates and CMOS inverter, Symbolic Diagrams-Translation to Mask Form.
Unit-II:
Basic Circuit Concepts: Sheet Resistance, Sheet Resistance concept applied to MOS transistors
and Inverters, Area Capacitance of Layers, Standard unit of Capacitance, The Delay Unit, Inverter
Delays, Propagation Delays, Wiring Capacitances, Fan-in and fan-out characteristics, Choice of
layers, Transistor switches, Realization of gates using NMOS, PMOS and CMOS technologies.
Scaling Of MOS Circuits: Scaling models, Scaling factors for device parameters, Limits due to
sub threshold currents, current density limits on logic levels and supply voltage due to noise.
Unit-III:

Unit-IV:

Unit-V:
FPGA Design: FPGA design flow, Basic FPGA architecture, FPGA Technologies, FPGA families-

Altera Flex 8000FPGA, Altera Flex 10FPGA, Xilinx XC4000 series FPGA, Xilinx Spartan XL

FPGA, Xilinx Spartan II FPGAs, Xilinx Vertex FPGA. Case studies: FPGA Implementation of
Half adder and full adder.

Introduction to synthesis: Logic synthesis, RTL synthesis, High level Synthesis.

Text Books:
1. Essentials of VLSI Circuits and Systems By Kamran Eshraghian, Douglas and A. Pucknell and
Sholeh Eshraghian, Prentice-Hall of India Private Limited,2005 Edition.
2. CMOS Digital Integrated Circuits Analysis and Design- Sung-Mo Kang, Yusuf Leblebici, Tata
McGraw-Hill Education, 2003.

References:
1. Advanced Digital Design with the Verilog HDL, Michael D.Ciletti, Xilinx Design Series,
Pearson Education
2. Analysis and Design of Digital Integrated Circuits in Deep submicron Technology, 3’rd edition,
David Hodges.

.ACADAMEIC CALENDAR
 3.PEOs and POs

Programme Educational Objectives(PSOs)

PEO-1 To transform the knowledge of basic sciences into engineering applications employing
mathematical tools.

PEO-2: To analyze, design, simulate and synthesize the electronic systems useful for contemporary
needs.

PEO-3: To possess effective communication, managerial and leadership qualities in a career

embedded with social commitment and ethical values

Programme Outcomes (PSOs)

Engineering Graduates will be able to:

 PO1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.

 PO2. Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

 PO3. Design/development of solutions: Design solutions for complex engineering

problems and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental Considerations.

 PO4. Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
 PO5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.

 PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

 PO7. Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.

 PO8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

 PO9. Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.

 PO10.Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
  PO11. Project management and finance: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.

 PO12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

Programme Specific Outcomes (PSOs)

 PSO1: Develop Systems and Algorithms in the fields of VLSI, Communication, Signal
Processing and Embedded Systems for contemporary needs.

 PSO2: Demonstrate competence in the areas of Communication Systems through effective

higher education and successful career.

4.Correlation between COs and POs:

PO1 PO1 PSO PSO
C311 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO1 1 2 1 2
C311.
1 2 2 2
C311.
2 3 1 2
C311.
3 3 2
C311.
4 2 2 3 2 3 3
C311.
5 2 2 2 2 3 3

 3 – HIGHELY CORRELATED, 2 – MODERATELY CORRELATED, 1- LOW

CORRELATED.

5. BRIEF NOTE ON THE IMPORTANCE OF THE COURSE

The main objective of the course is to provide a comprehensive and state of the art
knowledge in the area of VLSI Design.
The Course emphasis on the structure and function of the complete system. A detailed study
of the subsystems that comprises the overall system is carried out.
The technical knowledge provided in the course on different aspects of the system will help
the functioning of the system. This will further help in providing the necessary expertise required by
the industry.
. 6.DETAILED NOTES
 To be Attached

7.UNIVERSITY QUESTION PAPERS OF PREVIOUS YEARS

To be Attached

8. ASSIGNMENT TOPICS

1.With neat diagrams, explain the different steps in n-well fabrication of CMOS transistors.
2 .Explain the various steps in PMOS fabrication
1. Explain CMOS lambda based design rules
2. Explain 1.2μm Double Metal, Double Poly CMOS rules.
3. Design stick diagram for the function F = (A+B)(C+D)
4. Explain BIST(Buit-In Self Test) Technique with neat diagrams
5. Explain the Architecture of Xilinx Vertex FPGA with relevant diagrams
6. Explain the architecture of pipeline low power design?
7. Design of ALU using Mentor Graphics.
8. Design of Oscillator using Mentor Graphics

1. UNIT WISE QUESTIONS (QUESTION BANK)

CLASS/SEMESTER: IV/I ACADEMIC YEAR: 2018-2019
SUBJECT:VLSI REG: R13

QUESTION BANK
UNIT I
Introduction : Introduction to IC Technology, MOS and related VLSI Technology, Basic MOS
Transistors, Enhancement and Depletion modes of transistor action, IC production process, MOS and
CMOS Fabrication processes, BiCMOS Technology, Comparison between CMOS and Bipolar
technologies.
Basic Electrical Properties Of MOS and Bi-CMOS Circuits: Ids versus Vds Relationships, Aspects
of MOS transistor Threshold Voltage, MOS transistor Trans, Output Conductance and Figure of Merit.
The Pass transistor, NMOS Inverter, Pull-up to Pull-down Ratio for NMOS inverter driven by another
NMOS inverter. Alternative forms of pull-up, The CMOS Inverter, MOS transistor circuit model, Bi-CMOS
Inverter, Latch-up in CMOS circuits and BiCMOS Latch-up Susceptibility.

Part A

Q. Questions BT Level Competence

No
1 Explain the depletion mode transistor action. BTL 2 Understand
2 Define the following terms: (a) transconductance ( b ) output
conductance ( c ) figure of merit (d) threshold voltage BTL 1 Remember
3 What is latch up in CMOS transistors and how to overcome it? BTL 1 Remember
4 Explain the various steps in PMOS fabrication. BTL 2 Understand
5 Explain the depletion mode transistor action. BTL 2 Understand
PART B

1 With neat diagrams, explain the different steps in n-well

fabrication of CMOS transistors. BTL 4 Analyze
2 Discuss fabrication differences between NMOS and CMOS
technologies. Which fabrication is preferred and why? BTL 2 Understand
3 Draw the Id vs Vds characteristics of a MOS transistor and explain
its various regions of operation. BTL 4 Analyze
4 With neat sketches explain the formation of the inversion layer in
P-channel Enhancement MOSFET. BTL 4 Analyze
5 Derive the expression for drain current of a CMOS transistor BTL 4 Analyze
6 Draw the BiCMOS inverter circuit and explain its working BTL 4 Analyze
7 Determine the pull up to pull down ration for the inverter driven
by transmission gates.
BTL 4 Analyze
8 Explain about various IC technologies BTL 2 Understand
UNIT II
MOS and Bi-CMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and
Layout, General observations on the Design rules, 2μm Double Metal, Double Poly, CMOS/BiCMOS
rules, 1.2μm Double Metal, Double Poly CMOS rules, Layout Diagrams of NAND and NOR gates and
CMOS inverter, Symbolic Diagrams-Translation to Mask Form.

PART A
1 What are the different steps in the stick layout using nMOS
design? BTL 1 Remember
2 Explain the double metal MOS process rules. BTL 2 Understand
3 What are the different design rules for wires and contacts? BTL 1 Remember
4 Draw the stick diagram for CMOS inverter
BTL 4 Analyze
PART B
1 Draw the basic MOS transistor physical structure and explain its
working. BTL 4 Analyze
2 Draw the circuit diagram, layout diagram and stick diagram for
CMOS two input NAND gate and explain its working. BTL 4 Analyze
3 What are the different steps in the stick layout using CMOS
design? BTL 1 Remember
4 Explain CMOS lambda based design rules BTL 2 Understand
5 Write design rules for the following: (a) wires ( b ) contacts ( c )
transistor ( d ) diffusion BTL 1 Remember
6 Design a stick diagram for two input CMOS NAND and NOR BTL 6 Create
 gates.
7 Design stick diagram for the function F = (A+B)(C+D)
BTL 6 Create
8 Design CMOS layout for the function Y = (A.B+C+D)
BTL 6 Create
9 Explain the color code used for drawing stick diagram for NMOS
and PMOS designs BTL 2 Understand
10 What are the different types of contact cuts made during the
fabrication of an IC? Which one is commonly used and why?
BTL 1 Remember
UNIT III
Basic Circuit Concepts: Sheet Resistance, Sheet Resistance concept applied to MOS transistors and
Inverters, Area Capacitance of Layers, Standard unit of Capacitance, The Delay Unit, Inverter Delays,
Propagation Delays, Wiring Capacitances, Fan-in and fan-out characteristics, Choice of layers,
Transistor switches, Realization of gates using NMOS, PMOS and CMOS technologies. Scaling Of MOS
Circuits: Scaling models, Scaling factors for device parameters, Limits due to sub threshold currents,
current density limits on logic levels and supply voltage due to noise.

PART A
1 Define standard capacitance?Explain. BTL 1 Remember
2 Explain how MOSFETs can be used as switches BTL 2 Understand
3 What is inverter delay? How delay is calculated for multiple
stages? BTL 1 Remember
4 What are the sources of wiring capacitance BTL 1 Remember
5 Define Fanin & Fanout BTL 1 Remember
6 List out the limitations of scaling BTL 1 Remember
PART B
1 Describe three sources of writing capacitances. Explain the
effect of writing capacitance on the performance of a VLSI circuit
BTL 2 Understand
2 Explain briefly bout sheet Resistance? BTL 2 Understand
3 Discuss the Limits due to subthreshold current BTL 2 Understand
4 What are the limits on logiclevels and supply voltge due
to noise in scaling? BTL 1 Remember
Define scaling factor? Explain different types of device
5 parameters. BTL 1 Remember
6 Define inverter delay and derive Expression for rise&
Fall time. BTL 1 Remember
UNIT IV

Chip Input and Output circuits: ESD Protection, Input Circuits, Output Circuits and L(di/dt)

Noise, On-Chip clock Generation and Distribution.

Design for Testability: Fault types and Models, Controllability and Observability, Ad Hoc

Testable Design Techniques, Scan Based Techniques and Built-In Self Test techniques.
.
 PART A
1 Explain the concepts of Controllability and Observability with
example BTL 2 Understand
2 Discuss various Input Circuits used for VLSI Chip Design
BTL 1 Remember
3 Explain Various Types of Faults and Fault models
considered for Chip Testing BTL 2 Understand
PART B
1 Discuss various Output Circuits used to reduce L(di/dt)
noise for VLSI Chip Design BTL 2 Understand
2 Explain various Clock Generation& Distribution
Techniques used for VLSI Chip Design? . BTL 2 Understand
3 Explain various AdHoc Testable Design Techniques BTL 2 Understand
4 Explain Scan-Based Design Technique with neat Diagram BTL 2 Understand
5 Explain Scan based design of an Edge-Triggered D flip-
flop BTL 2 Understand
6 Explain BIST(Buit-In Self Test) Technique with neat
diagrams BTL 2 Understand
UNIT V

FPGA Design: FPGA design flow, Basic FPGA architecture, FPGA Technologies, FPGA families-

Altera Flex 8000FPGA, Altera Flex 10FPGA, Xilinx XC4000 series FPGA, Xilinx Spartan XL

FPGA, Xilinx Spartan II FPGAs, Xilinx Vertex FPGA. Case studies: FPGA Implementation of

Half adder and full adder.

Introduction to synthesis: Logic synthesis, RTL synthesis, High level Synthesis.

PART A
1 Draw the Basic FPGA Architecture BTL 6 Create
2 Explain various FPGA Technologies BTL 1 Remember
3 Explain RTL Synthesis BTL 6 Create
4 Explain High Level Synthesis BTL 1 Remember
PART B
1 Explain FPGA Design Flow . BTL 2 Understand
2 Explain the Architecture of Altera Flex 8000 FPGA with
relevant diagrams BTL 1 Remember
3 Explain the Architecture of Altera Flex 10 FPGA with
relevant diagrams BTL 2 Understand
4 Explain the Architecture of Xilinx XC4000 series FPGA
with relevant diagrams. BTL 2 Understand
5 Explain the Architecture of Xilinx Spartan II FPGA with BTL 4 Analyze
 relevant diagrams
Explain the Architecture of Xilinx Vertex FPGA with
6 relevant diagrams BTL 2 Understand
7 FPGA implementation of Half Adder BTL 2 Understand
UNIT VI

FPGA Design: Basic FPGA architecture, , FPGA configuration, configuration modes, FPGA design
process- FPGA design flow, FPGA families, FPGA design examples-stack, queue and shift register
implementation using VHDL, step-by-step approach of FPGA design process on Xilinx environment.

PART A
1
Explain Glitch reduction BTL 1 Remember
2 Explain Gated clock signal techniques for estimation &
optimization of switching activity BTL 6 Create
3 Write about switching power dissipation? BTL 1 Remember
4 Write about Short circuit power dissipation BTL 6 Create
PART B
1 Explain the operation of Variable Threshold CMOS
(VTCMOS) circuit? BTL 5 Evaluate
2 Explain the operation of Multiple Threshold CMOS
(MTCMOS) circuit? BTL 6 Create
3 Explain the architecture of pipeline low power design BTL 2 Understand
4 Explain various techniques for reduction of Switched
capacitance BTL 2 Understand
5 Write about leakage power dissipation BTL 2 Understand
6 Explain about Interconnect design BTL 2 Understand
7 Explain power grid and Clock design BTL 2 Understand

2. REFERENCESS, JOURNALS, WEBSITES AND E-LINKS IF ANY

References:
1. VLSI Design By A.Albert Raj & T.Latha,PHI Learning Private Limited,2010.
2. VLSI Design-A.Shanthi and A.Kavita, New Age International Private Limited, 2006 First
Edition.
E-Learning Materials:
NPTEL
1. http://nptel.iitm.ac.in/video.php?courseId=1094
2. http://nptel.iitm.ac.in/video.php?courseId=1004
 3. http://nptel.iitm.ac.in/courses/Webcourse-contents/IIT-%20Guwahati/ic_tech/index.html.

URL’S
1. http://www.cmosvlsi.com/coursematerials.html.
2. http://www.cdeep.iitb.ac.in/nptel/Electrical%20&%20Comm%20Engg/VLSI%20Design/
Course_home-m1.html
Sources in GATE/ other competitive exams:
GATE SYLLABUS:
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & Bi-CMOS Technologies,
Oxidation, Lithography, Diffusion, Ion implantation, Basic Electrical Properties of MOS Circuits,
Ids Vs Vds Relationships, MOS Transistor threshold voltage, gm, Figure of merit, Pass Transistor,
NMOS Inverter, Various pullups, CMOS inverter analysis and design.
Previous GATE papers available at http//:www.gateforum.com/gate_papers. php
IES SYLLABUS
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & Bi-CMOS Technologies,
Oxidation, Lithography, Diffusion, Ion implantation, Basic Electrical Properties of MOS Circuits,
Ids Vs Vds Relationships, MOS Transistor threshold voltage, gm, Figure of merit, Pass Transistor,
NMOS Inverter, Various pullups, CMOS inverter analysis and design.

11. MID QUESTION PAPERS.

Mid-1
 Mid-2

12. SCHEME OF EVALUTION

MID-1
 1.a)Derivationforgm----3m
Derivationfor gds……3m
Relatioship….1m
Mos figure of merit definition,formula---3m
2.NAND CMOS DIAGRAM----3M
STICK DIAGRAM----------2M
LAYOUT----------5M
3.A)Inverter circuit—2m
Delay----2m
Cascading—1m
b.)invertet---2m
cascaded inverters---3m.

MID-2

1.clockgeneration circuits………5m
Working….5m
2.FPGA Architecture……7m
Working….3m
3.Glitch reduction---3m
Switching optimization….7m

13.CO ATTAINMENTS

CO Overall Attainment

Overall
CO (DA) IDA
Attainment
 CO1 2.00 3.00 2.20
CO2 2.07 1.00 1.85
CO3 1.93 2.00 1.95
CO4 2.07 2.00 2.05
CO5 2.07 2.00 2.05
CO6 2.22 1.00 1.97
Average CO 2.01

PO ATTAINMENTS

PO PO PO PO PO PO1 PO1 PO1

Course PO4 PO6 PO8 PO9 PSO1 PSO2
1 2 3 5 7 0 1 2
DIRE 2.05 2.06
2.05 1.64 1.411 2.066 1.355
CT 8 7
OVER
2.00 2.03 1.58 1.35 2.05 2.05 1.35
ALL

14.OPEN BOOK ASSIGNMENT

NA

15.WORKSHOP CONDUCTED

NA

16. QUALITY MEASUREMENTSHEETS

1. ASSESMENT SHEET TO BE ATTACHED

2. COURSE EXIT SURVEY