CD74AC251

SCHS246A – AUGUST 1998 – REVISED AUGUST 2024

CD74AC251 8-Input Multiplexer, Three-State

1 Features 2 Description
• Buffered inputs The CD74AC251 8-input multiplexers that utilize
• Typical propagation delay the Harris Advanced CMOS Logic technology. This
– 6ns at VCC = 5V, TA = 25°C, CL = 50pF multiplexer features both true (Y) and complement
• Exceeds 2kV ESD protection MIL-STD-883, (Y) outputs as well as an Output Enable (OE) input.
method 3015 The OE must be at a LOW logic level to enable this
• SCR-latchup-resistant CMOS process and circuit device. When the OE input is HIGH, both outputs are
design in the high-impedance state. When enabled, address
• Speed of bipolar FAST™/AS/S with significantly information on the data select inputs determines
reduced power consumption which data input is routed to the Y and Y outputs.
• Balanced propagation delays Package Information
• AC types feature 1.5V to 5.5V operation and PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
balanced noise immunity at 30% of the supply CD74AC251 D (SOIC, 16) 9.9mm × 6mm 9.9mm × 3.9mm
• ±24mA output drive current
(1) For more information, see Section 10.
– Fanout to 15 FAST™ ICs
(2) The package size (length × width) is a nominal value and
– Drives 50Ω transmission lines includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
not include pins.

Functional Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Application and Implementation.................................... 9
2 Description.......................................................................1 7.1 Power Supply Recommendations...............................9
3 Pin Configuration and Functions...................................3 7.2 Layout......................................................................... 9
4 Specifications.................................................................. 4 8 Device and Documentation Support............................10
4.1 Absolute Maximum Ratings........................................ 4 8.1 Documentation Support (Analog)..............................10
4.2 Recommended Operating Conditions.........................4 8.2 Receiving Notification of Documentation Updates....10
4.3 Thermal Information....................................................4 8.3 Support Resources................................................... 10
4.4 Electrical Characteristics.............................................4 8.4 Trademarks............................................................... 10
4.5 Switching Characteristics............................................5 8.5 Electrostatic Discharge Caution................................10
5 Parameter Measurement Information............................ 7 8.6 Glossary....................................................................10
6 Detailed Description........................................................8 9 Revision History............................................................ 10
6.1 Functional Block Diagram........................................... 8 10 Mechanical, Packaging, and Orderable
6.2 Device Functional Modes............................................8 Information.................................................................... 10

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3 Pin Configuration and Functions

Figure 3-1. CD74AC251 D Package, 16-Pin SOIC (Top View)

PIN
TYPE1 DESCRIPTION
NAME NO.
I3 1 I Input 3
I2 2 I Input 2
I1 3 I Input 1
I0 4 I Input 0
Y 5 I Output
Y 6 I Inverted Output
OE 7 O Output Enable
GND 8 G Ground
S2 9 O Input Select 2
S1 10 O Input Select 1
S0 11 O Input Select 0
I7 12 O Input 7
I6 13 O Input 6
I5 14 O Input 5
I4 15 O Input 4
VCC 16 P Positive Supply

1. Signal Types: I = Input, O = Output, I/O = Input or Output.

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4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage -0.5 6 V
(VI < -0.5V or VI > VCC +
IIK Input diode current ±20 mA
0.5V)
(VI < -0.5V or VI > VCC +
IOK Output diode current ±50 mA
0.5V)
VO < -0.5V or VO > VCC +
IO Output source or sink current per output pin ±50 mA
0.5V
VCC or ground current, ICC or IGND (2) ±100 mA
TJ Maximum junction temperature (plastic package) 150 °C
Tstg Storage temperature -65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) For up to 4 outputs per device, add ±25mA for each additional output.

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC (1) Supply voltage 1.5 1.5
VI, VO Input or output voltage 0 VCC V
dt/dv Input rise and fall slew rate
AC types, 1.5V to 3V 50 ns
AC types, 3.6V to 5.5V 20 ns
TA Temperature range -55 125 °C

(1) Unless otherwise specified, all voltages are referenced to ground.

4.3 Thermal Information

CD74AC251
D (SOIC)
THERMAL METRIC 16 PINS UNIT
RθJA Junction-to-ambient thermal resistance(1) 119.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

4.4 Electrical Characteristics

TEST CONDITIONS 25°C -40°C TO 85°C -55°C TO 125°C
SYMBOL PARAMETER VCC (V) UNIT
VI (V) IO (mA) MIN MAX MIN MAX MIN MAX
High level input 1.5 1.2 - 1.2 - 1.2 - V
voltage
VIH - - 3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
Low level input 1.5 - 0.3 - 0.3 - 0.3 V
voltage
VIL - - 3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V

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TEST CONDITIONS 25°C -40°C TO 85°C -55°C TO 125°C

SYMBOL PARAMETER VCC (V) UNIT
VI (V) IO (mA) MIN MAX MIN MAX MIN MAX
High level -0.05 1.5 1.4 - 1.4 - 1.4 - V
output voltage
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
VOH VIH or VIL -4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75 (1), (2) 5.5 - - 3.85 - - - V
-50 (1), (2) 5.5 - - - - 3.85 - V
Low level output 0.05 1.5 - 0.1 - 0.1 - 0.1 V
voltage
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
VOL VIH or VIL 12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75 (1), (2) 5.5 - - - 1.65 - - V
50(1), (2) 5.5 - - - - - 1.65 V
Input leakage
II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 μA
current
Three-state VIH or VIL VO
IOZ leakage current = VCC or - 5.5 - ±0.5 - ±5 - ±10 μA
GND
Quiescent
ICC supply current VCC or GND 0 5.5 - 8 - 80 - 160 μA
MSI

(1) Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to
minimize power dissipation.
(2) Test verifies a minimum 50Ω transmission-line-drive capability at 85°C, 75Ω at 125°C.

Table 4-1. ACT Input Load Table

INPUT UNIT LOAD
S0, S1, S3 1
OE 1
I0 - I7 1

Note
Unit load is ΔICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25°C.

4.5 Switching Characteristics

Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40°C TO 85°C -55°C TO 125°C
SYMBOL PARAMETER VCC (V) UNIT
MIN TYP MAX MIN TYP MAX
Propagation delay, 1.5 - - 153 - - 169 ns
data to Y output
tPLH, tPHL 3.3(1) 4.9 - 17.2 4.7 - 18.9 ns
5(2) 3.5 - 12.3 3.4 - 13.5 ns
Propagation delay, 1.5 - - 169 - - 186 ns
data to Y output
tPLH, tPHL 3.3 5.4 - 19 5.2 - 20.9 ns
5 3.8 - 13.5 3.7 - 14.9 ns

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Input tr, tf = 3ns, CL = 50pF (Worst Case)

-40°C TO 85°C -55°C TO 125°C
SYMBOL PARAMETER VCC (V) UNIT
MIN TYP MAX MIN TYP MAX
Propagation delay, 1.5 - - 207 - - 228 ns
select to Y output
tPLH, tPHL 3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns
Propagation Delay, 1.5 - - 223 - - 245 ns
Select to Y Output
tPLH, tPHL 3.3 7.1 - 24.9 6.9 - 27.4 ns
5 5.1 - 17.8 4.9 - 19.6 ns
Propagation delay, 1.5 - - 155 - - 169 ns
tPZH, tPZL, output enable and
3.3 5.2 - 18.7 5.1 - 20.3 ns
tPHZ, tPLZ output disable to
output 5 3.5 - 12.3 3.4 - 13.5 ns
Three-state output
CO - - - 15 - - 15 pF
capacitance
CI Input capacitance - - - 10 - - 10 pF
Power dissipation
CPD (3) - - 120 - - 120 - pF
capacitance

(1) 3.3V Min is at 3.6V, Max is at 3V.

(2) 5V Min is at 5.5V, Max is at 4.5V.
(3) CPD is used to determine the dynamic power consumption per device.

Note
PD = VCC 2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply
voltage.

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5 Parameter Measurement Information

Figure 5-1. Three-state Propagation Delay Waveforms and Test Circuit

A. For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

Figure 5-3. Propagation Delay Times

Figure 5-2. Propagation Delay Times

CD74AC
Input Level VCC
Input Switching Voltage, VS 0.5 VCC
Output Switching Voltage, VS 0.5 VCC

† FOR AC SERIES ONLY: WHEN VCC = 1.5V, RL = 1kΩ

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6 Detailed Description
6.1 Functional Block Diagram

6.2 Device Functional Modes

Table 6-1. Truth Table
INPUTS OUTPUTS
SELECT
S2 S1 S0 OUTPUT ENABLE OE Y Y
X X X H Z Z
L L L L I0 I0
L L H L I1 I1
L H L L I2 I2
L H H L I3 I3
H L L L I4 I4
H L H L I5 I5
H H L L I6 I6
H H H L I7 I7

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 4.2
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and
a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Layout Diagram specifies the rules that must be observed under all circumstances. All unused inputs
of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level
that should be applied to any particular unused input depends on the function of the device. Generally they will
be tied to GND or VCC, whichever makes more sense or is most convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output
section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when
disabled.

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Documentation Support (Analog)
8.1.1 Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
CD74AC251 Click here Click here Click here Click here Click here

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 1998) to Revision A (August 2024) Page
• Deleted references to CD74ACT251 throughout the data sheet........................................................................1
• Added Package Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Device
Functional Modes,Application and Implementation section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ............................................................................. 1
• Added RθJA value: D = 119.9, all values in °C/W.............................................................................................. 4

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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