`

VLSI Design and Testing Semester 5

Course Code BEC602 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 4:0:0:0 SEE Marks 50
Total Hours of Pedagogy 50 Hours Total Marks 100
Credits 04 Exam Hours 3 Hours
Examination nature (SEE) Theory
Course objectives:
1.This course deals with analysis and design of digital CMOS integrated circuits.

2. The course emphasizes on basic theory of digital circuits, design principles and techniques for
digital design blocks implemented in CMOS technology.

3. This course will also cover switching characteristics of digital circuits along with delay and power
estimation.
4. Understanding the CMOS sequential circuits and memory design concepts.

5.Explore the knowledge of VLSI Design flow and Testing

Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. Lecture method (L) does not mean only traditional lecture method, but different type of teaching methods may be adopted
to develop the outcomes.
2. Show Video/animation films to explain the different concepts of Digital Signal Processing
3. Encourage collaborative (Group) Learning in the class
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such as the
ability to evaluate, generalize, and analyse information rather than simply recall it.
6. Topics will be introduced in a multiple representation.
7. Show the different ways to solve the same problem and encourage the students to come up with their own creative ways
to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps improve the students'
understanding.
9. Adopt Flipped class technique by sharing the materials / Sample Videos prior to the class and have discussions on the
that topic in the succeeding classes.

MODULE-1
Introduction to CMOS Circuits: Introduction, MOS Transistors, MOS Transistor switches, CMOS
Logic, Alternate Circuit representation, CMOS-nMOS comparison.

[Text 1: 1.1,1.2,1.3,1.4,1.5.1.6.]

Teaching-Learning Process: Chalk and talk method, YouTube videos, Power point
presentation RBT Level: L1, L2

MODULE-2
MOS Transistor Theory: n-MOS enhancement transistor, p-MOS transistor, Threshold Voltage,
Threshold voltage adjustment, Body effect, MOS device design equations, V-I characteristics, CMOS
inverter DC characteristics, Influence of βn / βp ratio on transfer characteristics, Noise margin,
Alternate CMOS inverters. Transmission gate DC characteristics. Latch-up in CMOS.
[Text 1: 2.1,2.2,2.3,2.4,2.5.2.6.]

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`

Teaching-Learning Process:
Chalk and talk method/Power point presentation RBT Level: L1, L2, L3.

MODULE-3
CMOS Process Technology: Silicon Semiconductor Technology, CMOS Technologies, Layout
Design Rules. [Text 1: 3.1,3.2,3.3.]
Circuit Characterization and Performance Estimation: Introduction, Resistance Estimation,
Capacitance Estimation, Switching Characteristics, CMOS gate transistor sizing, Determination of
conductor size, Power consumption, Charge sharing, Scaling of MOS transistor sizing, Yield.
[Text 1: 4.1,4.2,4.3,4.4,4.5.4.6.4.7,4.8,4.9,4.10]

Teaching-Learning Process:
Chalk and talk method/Power point presentation, YouTube Videos RBT Level: L1, L2, L3.

MODULE-4
CMOS Circuit and Logic Design: Introduction, CMOS Logic structures, CMOS Complementary logic,
Pseudo n-MOS logic, Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage Switch logic, Pass
transistor Logic, Electrical and Physical design of Logic gates, The inverter, NAND and NOR gates, Body
effect, Physical Layout of Logic gates, Input output Pads.

[Text 1: 5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8, 5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]

Teaching-Learning Process:
Chalk and talk method, YouTube videos, Power point presentation RBT Level: L1, L2, L3.
MODULE-5
Sequential MOS Logic Circuits: Introduction, Behaviour of Bistable Elements (Excluding
Mathematical analysis) SR Latch Circuit, Clocked Latch and Flip-Flop Circuits, Clocked SR Latch,
Clocked JK Latch.
[Text2: 8.1, 8.2, 8.3, 8.4]
Structured Design and Testing: Introduction, Design Styles, Testing
[Text1: 6.1, 6.2. 6.5]

Teaching-Learning Process:
Chalk and talk method/Power point presentation RBT Level: L1, L2, L3

Text Books:
1. Principals of CMOS VLSI Design A System approach Neil H E Weste and Kamran
Eshraghain . Addition Wisley Publishing company.
2. “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang & Yosuf
Leblebici, Third Edition, Tata McGraw-Hill.
Reference Books:
1. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, and David
Money Harris 4th Edition, Pearson Education.
2. “Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall of
India publication, 2005.

Course Outcomes: After completing the course, the students will be able to

@11112024 2
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CO1 Apply the fundamentals of semiconductor physics in MOS transistors and analyze the
geometrical effects of MOS transistors
CO2 Design and realize combinational, sequential digital circuits and memory cells in CMOS
logic.
CO3 Analyze the synchronous timing metrics for sequential designs and structured design basics.
CO4 Understand designing digital blocks with design constraints such as propagation delay
and dynamic power dissipation.
C05 Understand the concepts of Sequential circuits design and VLSI testing

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03.10.2022

VLSI Design and Testing LAB

Course Code BECL606 CIE Marks 50
Teaching Hours/Week (L: T: P: S) 0:0:2:0 SEE Marks 50
Credits 1 Exam Hours 3
Course objectives:
This laboratory course enables students to
• Design, model, simulate and verify digital circuits.
• Perform ASIC design flow and understand the process of synthesis, synthesis constraints
and evaluating the synthesis reports to obtain optimum gate level netlist.
• Perform RTL-GDSII flow and understand the ASIC Design flow.

Sl.No Experiments
.
1 Design a 4-Bit Adder
• Write a Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and generate the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
2 4-Bit Shift and add Multiplier
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells,
Power requirement and Total area required
3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for
ALU Behavioral Modeling
• Write Verilog description
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 Flip-Flops ( D,SR and JK )
• Write the Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report gate level netlist identify Critical path, Maximum delay, Total number of
cells, Power requirement and Total area required.
• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.
5 Four bit Synchronous MOD-N counter with Asynchronous reset
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
Identify Critical path
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• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.

6 a) Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set
the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected
technology. Carry out the following:

i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns
and the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
ii. From the simulation result compute tpHL, tpLH and td for all three geometrical
settings of width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for
CMOS inverter.

b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for
DRC and LVS, extract parasitic and perform post layout simulations, compare the results
with pre layout simulations and compare the results.

7 Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results.
Increasethe drive strength to 2X and 4X and tabulate the results.

8
Construct the schematic of the Boolean Expression

Y= AB+CD+E using CMOS Logic. Verify the functionality of the expression find out the
delay td for some combination of input vectors. Tabulate the results.

9 a) Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load
and find its transient response and AC response? Measure the Unit Gain Bandwidth (UGB),
amplification factor by varying transistor geometries, study the impact of variation in width
to UGB.

b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC
& LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
10 a) Construct the schematic of two-stage operational amplifier and measure the following:
i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase margin with and
without coupling capacitance iv. Use the op-amp in the inverting and non-inverting
configuration and verify its functionality. v. Study the UGB, 3dB bandwidth, gain and power
requirement in op-amp by varying the stage wise transistor geometries and record the
observations.

b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained
in part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform
post layout simulations, compare the results with pre-layout simulations and perform the
comparative analysis.
Demonstration Experiments ( For
CIE )

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11 UART
• Write Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path

12 Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
• Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract
parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.
Course outcomes (Course Skill Set):
On the completion of this laboratory course, the students will be able to:
1. Design and simulate combinational and sequential digital circuits using Verilog HDL.
2. Understand the synthesis process of digital circuits using EDA tool.
3. Perform ASIC design flow and understand the process of synthesis, synthesis constraints
and evaluating the synthesis reports to obtain optimum gate level netlist.
4. Design and simulate basic CMOS circuits like inverter, NOR gate and any Boolean
expression .
5. Perform RTL_GDSII flow and understand the stages in ASIC design.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE)
is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
course. The student has to secure not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and record write-up.
Rubrics for the evaluation of the journal/write-up for hardware/software experiments designed by
the faculty who is handling the laboratory session and is made known to students at the
beginning of the practical session.
• Record should contain all the specified experiments in the syllabus and each experiment write-up
will be evaluated for 10 marks.
• Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
• Weightage to be given for neatness and submission of record/write-up on time.
• Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8th
week of the semester and the second test shall be conducted after the 14th week of the semester.
• In each test, test write-up, conduction of experiment, acceptable result, and procedural
knowledge will carry a weightage of 60% and the rest 40% for viva-voce.
• The suitable rubrics can be designed to evaluate each student’s performance and learning
ability. Rubrics suggested in Annexure-II of Regulation book
• The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests
is the total CIE marks scored by the student.

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Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be

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decided jointly by examiners.

Students can pick one question (experiment) from the questions lot prepared by the internal /external
examiners jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners.
General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and
result in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks
and scored marks shall be scaled down to 50 marks (however, based on course type, rubrics shall be
decided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be
made zero.
The duration of SEE is 03 hours.
Rubrics suggested in Annexure-II of Regulation book

@11112024
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 ffi
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USN ztEC63

Stxth Semester B.E. I)egree June/July 2024

VLSI Design an ng
Time: 3 hrs. Max. Marks: 100

.9
o Note: Answq any FIWfull quesrtons,
At
ONEfult ,**rd$ each module.
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1 a. State Moore's law, elaborate (04 Marks)

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r b. Derive the expression for in linear and (10 Marks)

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c. Explain the following
(,
.b i) Body effect i0 (06 Marks)
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2 a. Explain working with neat sketches and
(08 Marks)
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5a. Exolain the ooeratbn6fthree transistor DRAM cell with necessary timing diagrams'
o (08 Marks)
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b Draw the ,*SfNAND flash memory cell and explain the operation. (06 Marks)
(06 Marks)
c Explain ferogillfuic RAM with necessaf,y diagrams.
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 2rEC63

OR
6 a. Explain read and write operations of SRAM cell with diagrams. (0E Marks)
b. What is row decoder? Explain with an example. (06 Marks)
c. Explain data prograrnming and erasing methods of (06 Marks)

of faults in :,i:,,. .
(08 Marks)
b, Consider the logic circuit shown in lEnd Boolean respect to x3,
1l

(06 Marks)
c. Explain faults in logic circuits. (06 Marks)

8a. explain path making algorithrn (10 Marks)

b. network for checking node ftults (Fig.Q. 8(b))
z\l (10 Marks)
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Module-5
9a, I
(06 Marks)
adhoc for (06 Marks)
neat partial scan. (08 Marks)

10 a, List rules.
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b. Explain based fault models.
#knctional (10 Marks)

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t8EC72
USN

Sevcnth Scmestcr Ii.E. Degree Examination' June/July 2023

VLSI Design
Time: 3 hrs Max. Marks: 100
Note2 Answer on! FIVE futl questions, choosing ONE Iull question from each module'

Module-1
E I a. lmplement a 4 : I multiplexer using :
i) Transmission gate (08 Marks)
ii) Tristate inverters
(04 Marks)
ds b. Realize CMOS compound gate for the function : Y = D+A(B+C) '
c. n of positive edge
With necessary circuit diagram and timing diagram explain the operatio
(08 Marks)
triggered D fliP-flop.

EN OR
E9p 2a. DrawthecircuitdiagramofaCMosinvefteranditsDCtransfercharacleristics.Explain
equation for switching
uurlor. ,.gi- ofope"rution and indicate the voltage levels' Derive the
(lo Mtrks)
aa. threshold. and saturated region of
b 6"ri*,n" equation for drain current ofa MOSFET in non-saturated
(06 Marks)
operarion.
c il;;i;;. following non-ideal effects of a MoSFET -channel length modulation mobility
6q (M Marks)
degradation.
Module-2
)a process (12 Marks)
3 a. With necessary diagrams explain CMOS n-well fabrication
.B b. Draw the layout of Y=ABC*D and estimate the area'
(08 Nlarks)
9=
OR
wires' con tact cuts and
,t a. With necessary diagrams explain lambda based design rules for (08 Marks)
dE tran sl sto rs .

ft,4OSrgr capacitances in three di{Ierent regions of operation

with necessary
b i-pi"j, (06 Marks)
5.v diagrams and equations
density, power density, Cox for
c What is Scaling? Compute drain current. po wer, current (06 Marks)
6= constant field scaling.
o- i:
5P
Module-3
f *a. Explain the RC delay model to d"luy of the logic circuit' Also calculate the
-6i "o'l -th"size inverter' (08 Marks)
J.fly r"i, tize inverter driving anoiher unit
7 b. "f
With necessary circuit example explain :
i) Pseudo nMOS
06 Mrrks)
ii) Ganged CMOS.
examples
following CMOS optimization techniques with necessary
:
.. i'*pf
"i'i,t "
i) lnput ordering (06 Marks)
ii) Asymmetric gates
I of 2
 t8EC72

6a Analyze the three input NAND gate using Elmore's delay and compute the falling and rising
propagation delays if the output is loaded with 'h' identical gates'
(08 M'rks)

b borp"r* and c#pare the logical effort and parasitic delay of the following gates with the
help ofschematic diagram :
i) 2 input NOR gate
ii) lnput NAND gate. (06 Marks)
gate using
C i*ptuin Cuscaal roltage switch logic (CVSL) implement two input OR/NOR
(06 Msrks)
CVSL.
Module-4
7 a. Compute the outPut voltage V.", in the following Pass transistor circuits. Assume
V'" = 0.7V.

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V .,,r=11

v_r.sv ,-*
Fig.Q7(a)
ILL (08 Marks)

b. With necessary diagrarns and equations explain charge storage and charge leakage in
(06 Marks)
dynamic logic.
c. With necessary circLrit diagmms explain resettable latches with :

(06 Marks)
i) synchroltous reset ii) asynchronous reset.

OR
Explain dynamic logic with an example Also explain the advantage and limitations
of
8 a. (08 M.rks)
dynamic logic.
With necessary circuit diagram explain 3 bit dynamic shift register with enhancement
load
b. Marks) (08
(radio less).
Explain dynamic synchronous CMOS transmission gate logic with necessary
diagrams
C
(0,1 Marks)

Module-5
9 a. with necessary circuit diagram explain the operation offour transistor DRAM ..ll(*
r".ur)
b. Explain the terms : i) controllability ii) obsevability iii) repeatability iv) survivability' - ..
(08 -M.rks)

c. Explain full CMOS SRAM cell with necessary circuit topology' (06 Marks)

OR
(06 Marks)
l0 a. Explain CMOS bridging fault with necessary example'
(08 Marks)
b. What is a fault model? Explain stuck at fault model with examples'
(06 Marks)
c. Draw the circuit of3 bit BILBO register and explain'

2 ol'2
 6

t 8EC72
USN
tT-I-l .,/
Seventh Semester B.E. Degree Examination, Jan./Feb.2023
VLS! Design
Time: 3 hrs. Max. Marks: 100
,9
Note: ,4nstver ony FIVE full questions, choosing ONE full question from each nrudule.

Module-1
I a. With neat graph define Moore's law. Explain the history of integrated structures (06 llarks )

b. Realize CMOS logic structure for the Boolean expressions :

i) y=(ab)+(c.d) ii) y=a.(b+c). (06 NIarks)

c. With neat diagrams, explain 3 regions of operations of nMOS transistor. (08 NIarks)
JZ
OR
.= ;l
2 a. List the any tkee non ideal features oftransistors. Explain each in detail. (06 Marlis)
b. Draw the diagram of general logic gate structue. Exptain 2-input CMOS NAND gate
functioning using truth table. (06 \Iarks)
c Draw schematic diagram of CMOS inverter. Explain the graphical derivation of CMOS
inverter DC characteristics. (08 Nlarks)

Module-2
3a With neat diagrams, explain the complete CMOS fabrication process. (12 Nlarks)
b Using relevant equations explain full scaling (constant field scaling) applied to i) Channc I
-o5 length ii) Channel depth iii) Oxide thickness iv) Junction depth v) Suppl-v-
vi) Tkeshold voltage vii) Doping densities Nn, No. (08 NIarks)

'i OR
^
c-L
4 a. analyzer.
Write a short note on timing (06 Nlarks)
F t:- b. With neat diagrams, explain the lumped representation of parasitic MOSFET capacitancc'.
d.9
d= c. Draw and explain layout rules for transistors. [8:Xff[i
!9 Module-3
5a Explain various stages of timing optimization in VLSI design. (08 Nlarks)
b With equations explain the calculation of inverter delay. (06 Ntarks)
Estimate the propagation delay to6 for unit inverter driving 'm' identical unit inverters usrns
Elmore delay. (06 \Iarks )

U<
OR
o 6a Draw the diagram of photo masking with a negative resist and explain.
(08 iuarks)
Z b What is logical effort? Explain HI-Skew inverter construction by down sizing of nMOS
E transistor. (06 Marks)
Explain pseudo nMOS inverter with schematic diagram and DC transfer characterist ic s.
E
(06 Marks)

I of2
 l8EC72

Module-4
7 a. Draw and explain the functioning ofpulse generators.
L'BRARY
(08 llarks)
b. Explain the working ofresettable flip-flops and (12 Nlarks)

OR
8 a Draw and explain the features (08 Marks)

b With neat circuit diagrams, latches. Write the advantage and

disadvantage ofeach. (12 luarks)

9a. (08 Ntarks)

(12 \{arks)
b.

OR
10 a. Write a short note on design for testability. (06 NIarks)

Explain manufacturing test principles in detail. (06 Marks)

b.
(08 Nlarks)
c. Explain the logic verification principles.

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VLSI Design and Testing 1 Introduction to CMOS Technology

Department of Electronics and Communication Engg.

VLSI Design and Testing(BEC602)

Introduction to CMOS Circuits

1 Introduction to CMOS Technology

Complementary Metal-Oxide-Semiconductor (CMOS) technology has become a fundamental
part of the modern integrated circuit (IC) industry.

Although CMOS is widely used today, its origins date back nearly a century.

1.1 Historical Background

The concept of the MOS field-effect transistor (MOSFET) was first proposed by J. Lilienfeld
in 1925, with a similar structure later suggested by O. Heil in 1935.

Early attempts to develop MOS transistors faced material-related challenges, leading to the
invention of the bipolar junction transistor (BJT), which became the dominant technology for
many years.

The MOS transistor gained renewed interest with the advent of the silicon planar process in
the early 1960s.

However, quality control and material challenges delayed its commercial adoption until around
1967.

Initially, only single-polarity MOS transistors (p-type or n-type) were commonly used.

CMOS, which utilizes both p-type and n-type transistors on the same substrate, was first
applied to ultra-low-power applications such as digital watches.

Due to the complexity of CMOS fabrication, it was initially less favored in general system
designs. However, as nMOS processing technology became more intricate, the relative
complexity of CMOS became less of a concern.

1.2 The Growing Importance of CMOS

The demand for low-power, high-density ICs led to a surge in CMOS adoption.

System designers faced increasing challenges with chip size and power consumption, making
CMOS an attractive alternative.

Today, CMOS has become the dominant technology for Very Large-Scale Integration (VLSI)
circuit design.

1
VLSI Design and Testing 2 MOS Transistors

2 MOS Transistors
A MOS (Metal-Oxide-Silicon) transistor is a fundamental semiconductor device used in
modern integrated circuits.

It is formed by layering conducting, insulating, and transistor-forming materials on a silicon

substrate.

The key structural elements include diffusion regions, polysilicon layers, and metal
interconnections, all separated by insulating layers.

2.1 CMOS Technology and Transistor Types

CMOS (Complementary MOS) technology utilizes two types of MOS transistors:

nMOS (n-type MOSFET) – An n-type transistor is fabricated on a p-type silicon

substrate, with two n-type diffused regions acting as the source and drain.

pMOS (p-type MOSFET) – A p-type transistor is fabricated on an n-type silicon

substrate, with two p-type diffused regions serving as the source and drain.

The doping of the silicon substrate determines the type of charge carriers:

nMOS transistors use electrons as the majority carriers (negatively charged).

pMOS transistors use holes as the majority carriers (positively charged).

2.2 Physical Structure and Components

A typical MOS transistor consists of the following components:

Source (S): One of the two terminals where current enters or exits.

Drain (D): The other terminal where current enters or exits.

Gate (G): A conducting electrode (typically polysilicon) placed over a thin insulating layer
(oxide) that controls current flow.

Substrate (Body): The silicon region in which the device is fabricated, either p-type for
nMOS or n-type for pMOS.

For an nMOS transistor, the structure consists of a p-type substrate separating two n-type
diffusion regions. A pMOS transistor has an n-type substrate with two p-type diffusion
regions. In both cases, the gate electrode sits above the channel region, separated by an
insulating oxide layer.

2
VLSI Design and Testing 2 MOS Transistors

Figure 1: MOS transistor physical structures

2.3 Operation of MOS Transistors

The MOS transistor operates by controlling the flow of current between the source and drain
terminals using the gate voltage.
Applying a positive voltage to the gate of an nMOS transistor attracts electrons, creating a
conductive channel between the source and drain.
Applying a negative voltage to the gate of a pMOS transistor attracts holes, enabling
conduction between the source and drain.
The source and drain terminals are interchangeable, and their designation depends on the direction
of current flow. The gate acts as a control terminal, regulating the electrical connection between
the drain and source.

2.4 Conclusion
MOS transistors are the building blocks of digital and analog circuits. The combination of nMOS
and pMOS transistors in CMOS technology enables low-power, high-speed circuits used in

3
VLSI Design and Testing 3 MOS Transistor Switches

microprocessors, memory chips, and various electronic devices.

3 MOS Transistor Switches

MOS (Metal-Oxide-Semiconductor) transistors act as controlled switches in digital circuits. The
gate terminal determines whether the switch is ON or OFF. We assume:
A high voltage (‘1’) is normally set to 5V and is called POWER (VDD).
A low voltage (‘0’) is normally set to 0V and is called GROUND (VSS).
The strength of a signal is measured by its ability to source or sink current.

3.1 nMOS Transistor as a Switch

An nMOS transistor operates as follows:
Gate = ‘1’ (VDD): The switch is ON (closed), allowing current flow.
Gate = ‘0’ (VSS): The switch is OFF (open), blocking current flow.

Passing Signals
Good for passing ‘0’ (LOW signal).
Imperfect for passing ‘1’ (HIGH signal is degraded due to threshold voltage drop
VDD − Vth).

Figure 2: nMOS transistor as a switch

3.2 pMOS Transistor as a Switch

A pMOS transistor operates as follows:
Gate = ‘0’ (VSS): The switch is ON (closed), allowing current flow.
Gate = ‘1’ (VDD): The switch is OFF (open), blocking current flow.

4
VLSI Design and Testing 3 MOS Transistor Switches

Passing Signals
Good for passing ‘1’ (HIGH signal).
Imperfect for passing ‘0’ (LOW signal is degraded).

Figure 3: pMOS transistor as a switch

3.3 Transmission Gate (Complementary Switch)

A transmission gate consists of an nMOS and a pMOS transistor connected in parallel. It is
controlled by:
Control signal (C) applied to nMOS.

Complementary control signal (C) applied to pMOS.

Figure 4: Transmission Gate (Complementary Switch)

Advantages of Transmission Gates

Overcomes the limitations of individual nMOS and pMOS switches.
Provides low resistance for both ‘0’ and ‘1’ signals.
Used in multiplexers, flip-flops, and pass-transistor logic circuits.

5
VLSI Design and Testing 4 CMOS Logic

3.4 Summary of Switch Behavior

Table 1: Summary of Switch Behavior

Switch Type Gate Signal State Passes ‘0’ Well Passes ‘1’ Well
1 (VDD) ON Yes No (degraded ‘1’)
nMOS
0 (VSS) OFF No No
0 (VSS) ON No (degraded ’0’) Yes
pMOS
1 (VDD) OFF No No
Transmission Gate C = 1, C = 0 ON Yes Yes

3.5 Conclusion
MOS transistors serve as voltage-controlled switches in digital circuits:
nMOS transistors efficiently pass ‘0’ signals but degrade ‘1’ signals.

pMOS transistors efficiently pass ‘1’ signals but degrade ‘0’ signals.

Transmission gates (TG) provide optimal switching by combining nMOS and pMOS
transistors.
These principles are widely applied in CMOS logic circuits, multiplexers, and memory
circuits.

4 CMOS Logic
4.1 The Inverter
A CMOS inverter is a fundamental building block of digital circuits, implementing the logical
NOT function.

The logical function of an inverter follows the truth table:

Table 2: Truth table of an inverter

Input (A) Output (Y)

0 1
1 0

From the table, we observe:

– When the input is ‘0‘, the output must be ‘1‘. This requires a P-SWITCH (PMOS
transistor) to connect the output to VDD.

6
VLSI Design and Testing 4 CMOS Logic

– When the input is ‘1‘, the output must be ‘0‘. This requires an N-SWITCH (NMOS
transistor) to connect the output to VSS.

Based on the above observations, the inverter consists of:

– A PMOS transistor connected between the output and VDD (pull-up network).
– An NMOS transistor connected between the output and VSS (pull-down network).

When the input is ‘0‘, the PMOS transistor turns ON, pulling the output to VDD.
Simultaneously, the NMOS transistor remains OFF, ensuring no direct path between VDD and
VSS.

Conversely, when the input is ‘1‘, the NMOS transistor turns ON, pulling the output to VSS,
while the PMOS transistor remains OFF.

Transistor-Level CMOS Inverter

A fully complementary CMOS gate follows this principle, where:

– A pull-down network (NMOS transistors) connects the output to VSS when required.
– A pull-up network (PMOS transistors) connects the output to VDD when required.

A Y

VDD

A Y

Figure 5: CMOS Inverter

This design ensures low power dissipation, as there is no direct current path between VDD
and VSS during steady-state operation.

4.2 Combinational logic

Combinational logic in CMOS is implemented using N-SWITCHES (NMOS transistors) and
P-SWITCHES (PMOS transistors).

By arranging these transistors in series or parallel, different logical functions can be realized.

7
VLSI Design and Testing 4 CMOS Logic

4.2.1 AND Function

If two N-SWITCHES are placed in series, as shown in figure below, the resulting composite
switch is closed (ON) only when both inputs are set to ‘1’.

This implements an AND function.

Figure 6: AND function using NMOS transistors in series

Similarly, the corresponding structure for P-SWITCHES is shown in figure below. The
composite switch is ON only when both inputs are set to ‘0’.

Figure 7: AND function using PMOS transistors in series

4.2.2 OR Function
When two N-SWITCHES are placed in parallel, the composite switch is ON if either input is
set to ‘1’, implementing an OR function.

In contrast, when two P-SWITCHES are placed in parallel, the composite switch is OFF if
both inputs are set to ‘1’.

8
VLSI Design and Testing 4 CMOS Logic

Figure 8: OR function using NMOS and PMOS transistors in parallel

4.2.3 CMOS Combinational Gates

By combining these series and parallel switch structures, CMOS logic gates such as NAND, NOR,
and more complex logic functions can be designed.

4.3 The NAND gate

The NAND gate is a fundamental digital logic gate that implements the NOT AND
operation.
It is widely used in digital circuit design due to its universal property, meaning any logic
function can be realized using only NAND gates.

4.3.1 Construction of a Two - input CMOS NAND gate

Figure below illustrates the construction of a 2-input NAND gate using CMOS technology.
The pull-down network (PDN) is based on the AND function (A.B). The presence of a
‘0’ in the truth table requires an AND structure for the n-channel MOSFETs (NMOS).
The pull-up network (PUN) follows De Morgan’s Theorem, forming a parallel
p-channel MOSFET (PMOS) OR structure that implements:
A·B = A+B
The PMOS network is the logical dual of the NMOS network, ensuring proper functionality.

9
VLSI Design and Testing 4 CMOS Logic

CMOS NAND Circuit Diagram

VDD
P1 P2

Y
A N1

B N2

Figure 9: Two - input CMOS NAND gate

Truth Table of a NAND Gate

Table 3: Truth Table of a Two - input NAND Gate

A B N1 N2 P1 P2 Y
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 1
1 0 ON OFF OFF ON 1
1 1 ON ON OFF OFF 0

Y =A·B
A
Y
B

4.3.2 Key Observations

1. Full Voltage Swing: - There is always a path from either VDD (logic 1) or GND (logic 0)
to the output, ensuring full logic levels. - This makes CMOS logic fully restoring.

2. No Ratioing Required: - Unlike nMOS logic, where transistor sizes need careful ratioing,
CMOS gates do not require it.

3. No Static Power Dissipation: - There is never a direct path between VDD and GND for
any input combination, minimizing power consumption.

10
VLSI Design and Testing 4 CMOS Logic

4. Extending to Multi-Input NAND Gates: Larger NAND gates are constructed by:
Adding NMOS transistors in series in the pull-down network.
Adding PMOS transistors in parallel in the pull-up network.

VDD

A B C n

Figure 10: n - input CMOS NAND gate

Y = A · B · C······ n

4.3.3 Conclusion
The CMOS NAND gate is a fundamental building block in digital logic design.
It provides advantages such as low power dissipation, full voltage swing, and
scalability.
Understanding its construction is essential for designing efficient digital circuits.

4.4 The NOR gate

The NOR gate is a fundamental digital logic gate that implements the NOT OR operation.
It is widely used in digital circuits and serves as a universal gate, meaning any logic function
can be realized using only NOR gates.

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VLSI Design and Testing 4 CMOS Logic

4.4.1 Construction of a Two - input CMOS NOR Gate

Figure below illustrates the construction of a 2-input NOR gate using CMOS technology.
The pull-down network (PDN) follows the OR function (A + B). The presence of a ‘1’ in
the truth table requires an OR structure for the n-channel MOSFETs (NMOS), meaning
NMOS transistors are in parallel.
The pull-up network (PUN) follows De Morgan’s Theorem, forming a series p-channel
MOSFET (PMOS) AND structure that implements:

A+B =A·B

The PMOS network is the logical dual of the NMOS network, ensuring proper functionality.

CMOS NOR Circuit Diagram

VDD
A P1

B P2
Y

N1 N2

Figure 11: Two-input CMOS NOR gate

Truth Table of a NOR Gate

Table 4: Truth Table of a Two-input NOR Gate

A B N1 N2 P1 P2 Y
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 0
1 0 ON OFF OFF ON 0
1 1 ON ON OFF OFF 0

Y =A+B

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VLSI Design and Testing 4 CMOS Logic

A
Y
B

4.4.2 Key Observations

1. Full Voltage Swing: - There is always a path from either VDD (logic 1) or GND (logic
0) to the output, ensuring full logic levels.

2. No Ratioing Required: - Unlike nMOS logic, where transistor sizes need careful ratioing,
CMOS gates do not require it.

3. No Static Power Dissipation: - There is never a direct path between VDD and GND for
any input combination, minimizing power consumption.

4. Extending to Multi-Input NOR Gates: - Larger NOR gates are constructed by:

Adding NMOS transistors in parallel in the pull-down network.

Adding PMOS transistors in series in the pull-up network.

VDD

A
Y

A B C n

Figure 12: n - input CMOS NOR gate

Y = A + B + C +·········+ n

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VLSI Design and Testing 4 CMOS Logic

4.4.3 Conclusion
The CMOS NOR gate is a fundamental building block in digital logic design.
It provides advantages such as low power dissipation, full voltage swing, and
scalability.
Understanding its construction is essential for designing efficient digital circuits.

4.5 Compound gates

A compound gate is formed by combining series and parallel transistor structures to
implement a complex Boolean function in CMOS logic.
Instead of using multiple basic gates, a compound gate directly maps the logic function to a
transistor-level implementation, improving speed and reducing power consumption.

4.5.1 Example 1: CMOS Implementation of F = (A.B) + (C.D)

The function F = (A.B) + (C.D) can be implemented using CMOS transistors by following these
steps:
Pull - Down Network (PDN): The nmos network will consist of:
– A and B in series, let us call this as S1.
– C and D in series, let us call this as S2.
– S1 and S2 in parallel.
Pull - Up Network (PUN): The pmos network will consist of:
– A and B in parallel, let us call this as P1.
– C and D in parallel, let us call this as P2.
– P1 and P2 in series.

VDD
A B

C D

A C

B D

Figure 13: CMOS implementation of F = (A.B) + (C.D)

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VLSI Design and Testing 4 CMOS Logic

4.5.2 Example 2: CMOS Implementation of F = (A + B + C).D

The function F = (A + B + C).D can be implemented using CMOS transistors by following these
steps:
Pull - Down Network (PDN): The nmos network will consist of:

– A, B, and C in parallel, let us call this as P1.

– D in series with P1.

Pull - Up Network (PUN): The pmos network will consist of:

– A, B, and C in series, let us call this as S1.

– D in parallel with S1.

VDD
A

B D

F
D

A B C

Figure 14: CMOS implementation of F = (A + B + C).D

4.6 Multiplexers
Complementary switches may be used to select between a number of inputs, thus forming a
multiplexer function.

Figure below shows a connection diagram for a 2 - input multiplexer.

15
VLSI Design and Testing 4 CMOS Logic

Figure 15: 2 - input Multiplexer

As the switches have to pass ‘0’s and ‘1’s equally well, complementary switches with n- and
p-transistors are used.

The truth table for the structure is shown in table below:

Table 5: Truth Table of a Two-input Multiplexer

S S A B OUTPUT
0 1 X 0 0(B)
0 1 X 1 1(B)
1 0 0 X 0(A)
1 0 1 X 1(A)

The complementary switch is also called a transmission gate or pass gate (complementary).

A commonly used circuit symbol for the transmission gate is shown in figure below.

Figure 16: Symbols of Transmission gate

16
VLSI Design and Testing 4 CMOS Logic

The multiplexer connection in terms of this symbol and transistor symbols is shown in figure
below.

Figure 17: 2 - input Multiplexer using Transmission gates

4.7 Memory
Memory elements are essential components in digital circuits for storing and retaining data.

Using basic CMOS structures, we can construct a simple memory element such as a flip-flop
with minimal components.

4.7.1 Flip-Flop Using a Multiplexer and Inverters

A simple flip-flop can be designed using a 2-input multiplexer and two inverters, as shown
in figure below.

Figure 18: Flip - flop

This circuit operates based on a load signal (LD) to control data storage.

17
VLSI Design and Testing 4 CMOS Logic

Write Mode (LD = 1)

When the load signal is high (LD = 1):
– The output Q is directly set to the input D.
– This allows new data to be stored in the flip-flop.
This operation is illustrated in figure below.

Figure 19: Flip - flop in Write Mode

Hold Mode (LD = 0)

When the load signal is low (LD = 0):
– The multiplexer switches to a feedback loop, connecting the output back to itself through
the inverters.
– This feedback maintains the stored value, effectively holding the previous state of Q,
while the input D is ignored.
This operation is illustrated in figure below.

Figure 20: Flip - flop in Hold Mode

4.7.2 Conclusion
This simple circuit demonstrates how memory elements can be built using fundamental CMOS
components.
Flip-flops like this serve as the foundation for registers, latches, and memory units in
digital systems.

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VLSI Design and Testing 5 Alternate Circuit representations

5 Alternate Circuit representations

Generally, a design can be expressed in terms of:
1. Behavioral representation
2. Structural representation
3. Physical representation

5.1 Behavioral representation

A behavioral representation defines how a system or circuit responds to a given set of
inputs.
This representation focuses on the functionality of a system rather than its implementation
details, making it independent of the underlying technology.

5.1.1 Behavioral Specification at the Logic Level

At the logic level, the behavior of a digital circuit can be described using Boolean functions.
For example, the behavior of a logic gate can be expressed as:

F = ((A + B + C) · D)

This Boolean function specifies the logical operation without indicating how it is implemented
in hardware or its performance characteristics.

5.1.2 Higher-Level Behavioral Descriptions

Behavioral representation can also be expressed at a higher level using arithmetic or logical
operations.
For instance, an addition operation can be described in a high-level language as:
sum = a + b

Here, no specific method of addition is implied, and the word length is assumed to be that of
the machine.

5.1.3 Behavioral Representation of Sequential Circuits

For sequential circuits, behavior can be described using conditional statements.
Consider a flip-flop, where the output is updated based on the load signal (LD):
IF ( LD == 1)
THEN Q = D;

This representation, however, may be ambiguous because it could also describe a

multiplexer, which selects inputs without necessarily storing a state.

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VLSI Design and Testing 5 Alternate Circuit representations

5.1.4 Higher Levels of Behavioral Specification

More abstract behavioral descriptions can specify:

– Types of registers used in a design.

– Data transfers between these registers.

These descriptions provide even less information about implementation details but help define
how the system should function.

Eventually, behavior can be described as an algorithm in a high-level programming language.

5.1.5 Importance in Modern Design Systems

The objective of modern digital design tools is to convert high-level behavioral
specifications into optimized hardware designs efficiently.

This process ensures:

– Faster design time.

– Increased accuracy and reliability.

By using behavioral representations, designers can develop complex digital systems while
focusing on functionality before deciding on implementation details.

5.2 Structural representation

A structural specification defines how components are interconnected to perform a function
or achieve a specific behavior.

Unlike behavioral descriptions, which focus on logical operations, structural descriptions

specify the physical arrangement of circuit elements.

One example of a structural description language is MODEL, developed by Lattice Logic Ltd.
This language provides a formal way to define circuit components and their interconnections.

5.2.1 Structural Representation in MODEL

In MODEL, circuit elements such as transistors are explicitly defined along with their
connections.

The general syntax follows this format:

Part <circuit_name > ( < inputs >) -> <outputs >
<Component_Type > <drain > <gate > <source >
End

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VLSI Design and Testing 5 Alternate Circuit representations

Example 1: Inverter Description in MODEL

Part inv ( in) -> out

Nfet out in vss
Pfet out in vdd
End

The first line defines a part named inv with input in and output out.

The Nfet transistor has its drain = out, gate = in, and source = vss.

The Pfet transistor has its drain = out, gate = in, and source = vdd.

Example 2: 2-Input NAND Gate in MODEL

Part nand2 (a, b) -> out

Signal i1
Nfet i1 a vss
Nfet out b i1
Pfet out a vdd
Pfet out b vdd
End

An internal signal i1 is declared to facilitate the connection between transistors.

Two Nfet transistors form a series connection, while two Pfet transistors are in parallel,
implementing a NAND function.
The corresponding Boolean equation is:

out =∼ (a&b)

vdd
a b

out
b
i1
a

vss
Figure 21: Graphical representation of structural description for a Two - input CMOS NAND gate

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VLSI Design and Testing 5 Alternate Circuit representations

5.2.2 Advantages of Structural Representation

1. Explicit Connectivity: The entire transistor-level structure is specified.

2. Performance Optimization: Allows modifications such as transistor sizing and capacitance

adjustments.

3. Hierarchical Design: Smaller components can be combined to build complex circuits.

Example 3: Adding Performance Parameters

Part nand2 (a, b) -> out

Signal i1
Nfet i1 a vss
Nfet out b i1
Pfet out a vdd size = 2
Pfet out b vdd size = 2
Capacitance i1 50
Capacitance a 100
Capacitance b 100
Capacitance out 200
End

Transistor Sizing: size = 2 increases the size of Pfets, affecting speed and power.

Capacitance Values: Specified in arbitrary units to account for circuit delay effects.

5.2.3 Structural Representation of Complex Circuits

By using smaller predefined components, we can create more complex circuits.

Example 4: Transmission Gate in MODEL

Part tg (a, c, cb) -> b

Nfet a c b
Pfet a cb b
End

A transmission gate consists of an Nfet and a Pfet, controlled by complementary signals (c and
cb).

Example 5: Flip-Flop (D Latch) Using Structural Components

Part flipflop ( in , ld , ldbar , q, qbar)

Signal a
tg ( in , ld , ldbar) -> a
inv ( a) -> qbar
inv ( qbar) -> q

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VLSI Design and Testing 5 Alternate Circuit representations

tg (q, ldbar , ld) -> a

End

Figure 22: Schematic representation of CMOS flip-flop

The flip-flop (D latch) is implemented using transmission gates (tg) and inverters (inv).

This hierarchical design approach enables scalability and reuse of components.

5.2.4 Structural vs. Behavioral Representation

Table 6: Comparison of Structural and Behavioral Representation

Feature Structural Representation Behavioral Representation

Focus Transistor-level connectivity Logical function
Example Nfet out in vss out = (a & b)
Performance Details Yes (e.g., capacitance, size) No
Flexibility Parameterized descriptions possible Limited parameterization
Readability More detailed, hardware-specific More abstract, easier to understand

Behavioral descriptions ensure correct logic implementation, but structural descriptions define
real circuit performance.

5.2.5 Combining Structural and Graphical Representations

Structural descriptions (MODEL) provide a text-based, parameterized method for
defining circuits.

Graphical descriptions (schematics) visually represent circuit connectivity.

Emerging design tools integrate both approaches for flexibility and efficiency.

23
VLSI Design and Testing 5 Alternate Circuit representations

Example: Parameterized Inverter

Part inv ( in) [n] -> out

Nfet out in vss size = n
Pfet out in vdd size = 2 * n
End

The size parameter n allows dynamic transistor scaling, useful for design automation.

5.2.6 Conclusion
Structural representation is essential in circuit design for detailed connectivity,
performance optimization, and hierarchical modeling.

By combining structural and behavioral descriptions, engineers can achieve both logical
correctness and physical efficiency in circuit design.

5.3 Physical representation

The physical specification for a circuit is used to define how a particular part must be
constructed to yield a specific structure and, consequently, a defined behavior.

In an Integrated Circuit (IC) process, the lowest level of physical specification is the
photo-mask information, which is crucial for the various processing steps during
fabrication.

At this stage, we focus on a simplified model for the physical nature of a CMOS circuit.

5.3.1 Transistor Physical Representation

A typical physical representation for a transistor involves two rectangles, representing the
lithography required for the transistor’s fabrication.

These rectangles have precise dimensions defined by the design rules, which are based on the
specific process being used.

These rules often change for different processes, and the corresponding dimensions may not
change linearly.

Rather than focusing on these complex rules, we use a single symbol to represent a transistor
in a non-metric format, maintaining the essential physical nature of the transistor.

n-Transistor representation
The physical symbol for an n-transistor is shown in figure below.

In n-transistor, two process levels are overlaid: one for the gate connection and another for the
source and drain.

These symbols are placed on a grid where:

24
VLSI Design and Testing 5 Alternate Circuit representations

– The center grid point is for the gate.

– The grid point to the right (or above) is the drain.
– The grid point to the left (or below) is the source.

These grid points can be visualized as part of a schematic layout.

Figure 23: Physical Representation of n-Transistor

p-Transistor representation
Similarly, a p-transistor uses a similar symbol, as shown in figure below. The “horizontal”
transistor layout is used here, with the gate, source, and drain points similarly defined on the
grid.

Figure 24: Physical Representation of p-Transistor

25
VLSI Design and Testing 5 Alternate Circuit representations

5.3.2 Physical Symbolic Layout for an Inverter

A symbolic layout for an inverter can be constructed using the transistor symbols.

Figure 25: Physical Representation of CMOS inverter

It resembles the schematic layout but requires careful consideration of the layers in which
connections are made.
The interaction of these layers is summarized in table below:
– OK denotes that a connection is possible between two layers.
– X signifies that a direct connection is not allowed, requiring a “contact” (C) to connect
the two layers.

Table 7: Physical Layer Interactions in CMOS Design

Physical Layer n-Diffusion p-Diffusion Polysilicon Aluminum

n-Diffusion OK X Transistor OK (C)
p-Diffusion X OK Transistor OK (C)
Polysilicon Transistor Transistor OK OK (C)
Aluminum OK (C) OK (C) OK (C) OK

5.3.3 Transmission Gate Layout

The symbolic layout for a transmission gate is shown in figure below.
This layout is composed of the overlaid n- and p-transistor symbols, with grid points
connecting the appropriate terminals.

26
VLSI Design and Testing 5 Alternate Circuit representations

Figure 26: Symbolic Layout for Transmission Gate

5.3.4 Building a Flip-Flop

Using the principles described, a physical sub-assembly for a flip-flop can be constructed.

Figure below shows the symbolic layout for a flip-flop.

Figure 27: Symbolic Layout for Flip-Flop

This layout combines multiple transmission gates and inverters, with appropriate connections
for Vss and Vdd supplies.

27
VLSI Design and Testing 6 CMOS-nMOS comparison

5.3.5 Conclusion
CMOS IC design involves several critical steps:

1. Defining the behavior of the circuit.

2. Designing the logic that implements the behavior.

3. Translating this logic into a transistor-level description.

4. Finally, creating a physical layout for the designed logic.

6 CMOS-nMOS comparison

Table 8: Comparison of CMOS and nMOS Logic

Feature CMOS nMOS

Logic Levels Fully restored logic; output settles at Output does not settle at GND, leading
VDD or VSS (GND). to degraded noise margin.
Transition Rise and fall times are of the same or- Rise times are inherently slower than fall
Times der. times.
Transmission Passes both logic levels well; output can Pass transistor transfers logic ‘0’ well, but
Gates drive other transmission gates. logic ‘1’ is degraded. Cannot drive a sec-
ond pass transistor.
Power Dissi- Almost zero static power dissipation; Power dissipated in the circuit even when
pation power dissipated only during logic tran- output is stable, in addition to switching
sition. losses.
Precharging Both n-type and p-type devices can With enhancement-mode transistors, the
Characteris- precharge a bus to VDD or VSS. best achievable precharge is (VDD − Vt).
tics Bootstrapping or hot clocking is often re-
quired.
Power Supply Voltage required to switch a gate is a Somewhat dependent on supply voltage;
fixed percentage of VDD; variable range fixed.
from 1.5V to 15V.
Packing Den- Requires 2N devices for N -input com- Requires (N + 1) devices for N -input
sity plementary static gates; fewer for dy- gates.
namic gates.
Pull-up to Load-to-driver ratio typically 2:1. Load-to-enhancement-driver ratio opti-
Pull-down mized for logic ‘0’ level and minimal cur-
Ratio rent consumption.
Layout Encourages regular layout styles. Depletion load and different driver tran-
sistor sizes inhibit layout regularity.

28
VLSI Design and Testing 1 Introduction to MOS Transistor

Dr. T. THIMMAIAH INSTITUTE OF TECHNOLOGY

Department of Electronics and Communication Engg.

VLSI Design and Testing(BEC602)

MOS Transistor Theory

1 Introduction to MOS Transistor

A MOS transistor is a majority carrier device, in which the current in the channel between
the source and drain is modulated by a voltage applied to the gate.

1.1 nMOS Transistor

Majority carriers are electrons.

A positive gate voltage relative to the substrate increases electron concentration in the
channel, enhancing conductivity.

For gate voltages below the threshold voltage Vt, the channel is cut off, leading to a very
low drain-to-source current.

1.2 pMOS Transistor

Majority carriers are holes.

A negative gate voltage enhances conduction.

The operation is analogous to nMOS but with opposite voltage polarities.

1.3 Threshold Voltage (Vt)

The threshold voltage Vt is the voltage at which a MOSFET begins to conduct.

The source-to-drain current Ids depends on the gate-to-source voltage Vgs.

1.4 Enhancement vs. Depletion Mode

There are two types of MOS transistors based on conduction behavior at zero gate bias:

1. Enhancement Mode: The transistor is normally OFF (requires a gate voltage to conduct).

2. Depletion Mode: The transistor is normally ON (conducts even at zero gate voltage).

1.5 nMOS vs. pMOS Transistors

nMOS and pMOS transistors are duals of each other, meaning they function similarly but
with opposite voltage polarities.

1
VLSI Design and Testing 1 Introduction to MOS Transistor

The threshold voltages are denoted as:

Vtn : (n-channel MOSFET)
Vtp : (p-channel MOSFET)

Figure 1: Conduction characteristics for enhancement and depletion mode transistors (assuming fixed
Vds)

1.6 CMOS Technology

Both nMOS and pMOS transistors are used together in CMOS (Complementary MOS)
circuits.

Most modern CMOS integrated circuits use enhancement-mode transistors.

2
VLSI Design and Testing 2 n-MOS Enhancement Transistor

2 n-MOS Enhancement Transistor

An nMOS enhancement-mode transistor is a voltage-controlled device widely used in digital
and analog circuits.
It operates based on an electric field-induced conduction channel between its source and drain
terminals.

Unlike bipolar junction transistors (BJTs), where charge carriers are introduced by doping, an
nMOS transistor forms a conductive channel through an applied gate voltage.

2.1 Structure of nMOS Enhancement-Mode Transistor

The basic structure of an nMOS enhancement-mode transistor is shown in figure below. It
consists of:

– A moderately doped p-type silicon substrate.

– Two heavily doped n-type regions called the source and drain, diffused into the
substrate.
– A thin insulating layer of silicon dioxide (SiO2) covering the channel region, known as
the gate oxide.
– A polycrystalline silicon (polysilicon) gate electrode over the oxide layer.

Since SiO2 is an excellent insulator, the gate does not allow direct current flow to the channel.

Figure 2: Physical structure of an nMOS transistor

The transistor is symmetrical, meaning the source and drain can be interchanged physically.

However, in circuit design, the source is usually defined as the terminal at a lower potential.

3
VLSI Design and Testing 2 n-MOS Enhancement Transistor

2.2 Principle of Operation

The operation of the nMOS transistor depends on the applied gate-source voltage (VGS) and
drain-source voltage (VDS).

2.2.1 With Zero Gate Bias (VGS = 0)

The p-type substrate prevents current flow between the source and drain because the two p-n
junctions (between the n+ regions and the p-substrate) are reverse biased.
The source and drain act as two isolated n-regions, with only leakage current flowing.

2.2.2 Applying a Positive Gate Voltage (VGS > 0)

The positive voltage on the gate creates an electric field (E) that repels holes and attracts
electrons toward the oxide-silicon interface.

When VGS exceeds a threshold voltage (Vt), sufficient electrons accumulate to form an
inversion layer, effectively turning the p-type region beneath the gate into an n-type channel.
This allows current to flow between source and drain if a voltage VDS is applied.

2.2.3 Field-Induced vs. Metallurgical Junction

Unlike BJTs, where n-type conductivity is introduced via doping, the MOSFET channel is
induced by an electric field.
This field-induced junction enables voltage-controlled operation.

2.3 Operating Regions of nMOS Transistor

The nMOS transistor operates in three regions based on the applied voltages:
1. Cutoff Region (VGS < Vt):
The gate voltage is below the threshold voltage.
No conduction occurs except for a small leakage current.
The transistor acts as an open switch.

2. Linear (Triode) Region (VGS > Vt and VDS < VGS − Vt):
The inversion layer forms a conductive channel between the source and drain.
The transistor behaves like a voltage-controlled resistor.
Drain current IDS is approximately proportional to VDS.
The drain current in this region is given by:
W 2
IDS = µnCox (VGS − Vt)VDS − VDS (1)
L 2
where:

4
VLSI Design and Testing 2 n-MOS Enhancement Transistor

µn is the electron mobility.

Cox is the gate oxide capacitance per unit area.
W is the channel width.
L is the channel length.

Figure 3: nMOS in Linear region

3. Saturation Region (VGS > Vt and VDS > VGS − Vt):

The channel becomes pinched off at the drain end.
The drain current is primarily controlled by VGS and is almost independent of VDS.
The drain current in this region is given by:
1 W
IDS = µn Cox (VGS — Vt)2 (2)
2 L

Figure 4: nMOS in Saturation region

Pinch-Off and Channel Behavior

– At the source end, the full gate voltage is effective.
– At the drain end, only (VGS − VDS) is effective.
– When VDS > VGS − Vt, the channel is pinched off.
– Electrons drift toward the drain due to the electric field.

5
VLSI Design and Testing 2 n-MOS Enhancement Transistor

2.3.1 Factors Affecting Drain Current

The drain current IDS is influenced by:

The distance between source and drain, i.e., channel length (L).

The channel width (W ).

The threshold voltage (Vt).

The thickness of the gate-insulating oxide layer.

The dielectric constant of the gate insulator.

Carrier mobility (µn).

2.3.2 Breakdown and Abnormal Conditions

1. Avalanche Breakdown
If a very high voltage is applied to the drain, impact ionization occurs.

This leads to excessive current flow, causing possible device failure.

2. Punch-Through Effect
If VDS is too high, the depletion region extends from the source to drain, allowing direct
current flow.

This results in loss of gate control over the drain current.

2.3.3 Summary
Region Gate Voltage (VGS) Drain Voltage (VDS) Current Flow (IDS)
Cutoff VGS < Vt Any No conduction (only leakage
current)
Linear VGS > Vt VDS < VGS − Vt Increases linearly with VDS
Saturation VGS > Vt VDS > VGS − Vt Controlled by VGS, nearly
independent of VDS

2.4 Conclusion
The nMOS enhancement-mode transistor is an essential component in digital and analog
circuits.

It operates as a voltage-controlled switch, allowing conduction only when VGS > Vt.

By varying the gate and drain voltages, the device transitions between different operating
regions, making it ideal for digital logic and analog applications.

Understanding its different operating regions and the impact of design parameters is crucial
for efficient circuit design.

6
VLSI Design and Testing 3 pMOS Transistor

3 pMOS Transistor
While most discussions on MOS transistors focus on nMOS devices, a complementary type
called the pMOS transistor exists.
A pMOS transistor is structurally similar to an nMOS transistor but with reversed doping
polarities.
This means the substrate is n-type, and the source and drain are p-type.
The pMOS transistor operates in a manner similar to an nMOS transistor but with opposite
voltage polarities and charge carrier movement.

3.1 Structure of a pMOS Enhancement-Mode Transistor

A pMOS enhancement-mode transistor consists of:
An n-type silicon substrate.
Two heavily doped p-type regions, called the source and drain, diffused into the substrate.
A thin insulating layer of silicon dioxide (SiO2) covering the channel region, known as the
gate oxide.
A polycrystalline silicon (polysilicon) gate electrode over the oxide layer.
Figure below illustrates the structure of a pMOS transistor.

Figure 5: Physical structure of PMOS transistor

3.2 Operation of a pMOS Transistor

Similar to the nMOS transistor, a pMOS transistor operates based on the creation of a conductive
channel between the source and drain when a proper gate voltage is applied.

7
VLSI Design and Testing 3 pMOS Transistor

3.2.1 With Zero Gate Bias (VGS = 0)

No conduction occurs because the source and drain are separated by two reverse-biased p-n
junctions.

The source and drain act as two isolated p-regions in an n-type substrate.

3.2.2 Applying a Negative Gate Voltage (VGS < 0)

A negative voltage on the gate repels electrons and attracts holes toward the SiO2-silicon
interface.

When VGS is sufficiently negative (i.e., less than a threshold voltage Vt), an inversion layer
forms, converting the n-type region under the gate into a p-type conductive channel.

This allows holes to flow from the source to the drain if a negative drain-to-source voltage
(VDS) is applied.

3.2.3 Charge Carrier Movement

In an nMOS transistor, conduction occurs due to electron movement.

In a pMOS transistor, conduction occurs due to hole movement.

A negative drain voltage causes holes to move from the source through the channel to the
drain.

3.3 Comparison Between pMOS and nMOS Transistors

Parameter nMOS pMOS
Substrate Type p-type n-type
Source/Drain Doping n+ regions p+ regions
Charge Carriers Electrons Holes
Gate Control Positive voltage creates n-channel Negative voltage creates p-channel
Drain Voltage Positive for conduction Negative for conduction
Carrier Mobility High Lower than electrons

3.4 Conclusion
The pMOS transistor operates in a manner similar to an nMOS transistor but with reversed
voltage polarities and charge carrier movement.

While nMOS transistors dominate modern digital circuits due to higher electron mobility,
pMOS transistors are still used in complementary MOS (CMOS) technology to achieve low
power consumption and enhanced performance.

8
VLSI Design and Testing 4 Threshold Voltage (Vt)

4 Threshold Voltage (Vt)

The threshold voltage, Vt, of an MOS transistor is the minimum gate-to-source voltage
(VGS) required to create a conductive inversion layer (channel) between the source and drain
terminals.

Below this voltage, the drain-to-source current (IDS) is negligible, meaning the transistor is in
the cut-off region.

4.1 Factors Affecting Threshold Voltage

The threshold voltage is influenced by several factors, including:

Gate material: Different materials have different work functions, which affect the required
voltage for inversion.

Gate insulation material: The dielectric constant of the insulator affects the threshold
voltage.

Gate insulator thickness: Thinner oxide layers result in stronger electric fields and lower
threshold voltages.

Channel doping: Heavily doped substrates increase the threshold voltage.

Impurities at the silicon-insulator interface: Trapped charges and interface states can
shift the threshold voltage.

Voltage between source and substrate (VSB): Also known as the body effect, an
increase in VSB raises the threshold voltage.

4.2 Temperature Dependence of Threshold Voltage

The absolute value of the threshold voltage decreases with increasing temperature. This variation is
approximately:

−4 mV/ C for high substrate doping levels.

−2 mV/ C for low substrate doping levels.

As temperature rises, increased carrier generation reduces the depletion region width, leading to a
lower threshold voltage.

4.3 Conclusion
The threshold voltage is a key parameter in MOS transistor operation, determining when the
device transitions from the off-state to conduction.

It depends on material properties, doping levels, and external bias conditions, and exhibits
temperature sensitivity that must be considered in circuit design.

9
VLSI Design and Testing 5 Threshold Voltage Adjustment

5 Threshold Voltage Adjustment

The native (original) threshold voltage (Vt) of an MOS transistor may not always be suitable
for a given application.
Therefore, it is often necessary to adjust Vt to achieve desired device characteristics.
Two common techniques used for threshold voltage adjustment are:
1. Varying the doping concentration at the silicon-insulator interface through
ion implantation.
2. Using different insulating materials for the gate dielectric.

5.1 Ion Implantation for Threshold Voltage Control

One effective method to modify the threshold voltage is through ion implantation, which
alters the doping concentration at the silicon-insulator interface.
This technique allows precise control over Vt by introducing dopant atoms into the channel
region.

5.2 Using Different Gate Insulating Materials

Another approach to adjusting the threshold voltage is by modifying the gate dielectric
material.
Instead of using only silicon dioxide (SiO2), a combination of silicon nitride (Si3N4) and silicon
dioxide can be used.
– Silicon nitride (Si3N4) has a relative permittivity of 7.5.
– Silicon dioxide (SiO2) has a relative permittivity of 3.9.
– When a layer of silicon nitride is combined with a layer of silicon dioxide, the resulting
effective permittivity is about 6.
Since the effective permittivity of the dual-dielectric structure is higher than that of SiO2
alone, the dual-layer dielectric is electrically equivalent to a thinner SiO2 layer of the same
physical thickness.
This reduces the required gate voltage to achieve inversion, effectively lowering Vt.

5.3 Preventing Unwanted Inversion

To ensure that the silicon surface does not invert in regions between transistors, the threshold
voltage in these field regions is increased by:
Heavily doped diffusions.
Ion implantation into the silicon surface.
Increasing the oxide layer thickness in these regions.

. 10
VLSI Design and Testing 6 Body Effect

5.4 Self-Isolation of MOS Transistors

MOS transistors are inherently self-isolating as long as:

The silicon surface inverts under the gate.

The surface does not invert in the regions between transistors under normal circuit voltage
conditions.

5.5 Conclusion
Threshold voltage adjustment is an essential technique in MOS transistor design, allowing
fine-tuning of device performance.

Ion implantation and high-permittivity gate dielectrics provide effective means to control Vt,
ensuring proper operation and isolation between transistors in integrated circuits.

6 Body Effect
In MOSFETs, the body effect (also known as the substrate bias effect) occurs when the
voltage difference between the source and substrate (Vsb) affects the threshold voltage
(Vt).

This effect becomes significant in circuits where multiple transistors are connected in series,
such as in CMOS logic gates, because the substrate voltage is usually common for all
transistors.

6.1 Common Substrate and its Impact

d2
g2

s2 Vsb2 ̸= 0
Vt2 > Vt1
d1
Vt2 g1

Vt1 s1 Vsb1 = 0

Figure 6: The effect of body effect on series connected transistors

11
VLSI Design and Testing 6 Body Effect

In most MOS circuits, all transistors share a common substrate.

Under normal conditions, the substrate voltage remains the same for all transistors.

However, in certain configurations — especially when multiple MOSFETs are connected in

series — this assumption no longer holds.

Consider a chain of MOSFETs connected in series, as shown in figure above.

The first transistor in the series may have its source directly connected to ground, leading to a
source-to-substrate voltage of zero (Vsb1 = 0).

However, for the second transistor in the series, its source is connected to the drain of the first
transistor, which is at a higher potential.

This results in a nonzero source-to-substrate voltage (Vsb2 ̸= 0).

As we move along the series chain, Vsb continues to increase.

6.2 How the Body Effect Alters the Threshold Voltage

The threshold voltage of a MOSFET is the minimum gate-to-source voltage (Vgs) required
to form a conductive channel between the source and drain.

Under normal conditions, when Vgs > Vt, a channel is formed, and charge carriers (electrons
in nMOS or holes in pMOS) flow from the source to the drain.

When Vsb increases, it affects the depletion region at the substrate-channel junction:

– The depletion layer width increases.

– More charge carriers get trapped in the depletion layer.
– To maintain charge neutrality, the available channel charge decreases.

Since the channel charge is reduced, the gate must apply more voltage to invert the channel.

This means that the threshold voltage (Vt) increases, making it harder to turn the transistor
ON.
This phenomenon is called the body effect.

6.3 Mathematical Expression for the Body Effect

The modified threshold voltage in the presence of a nonzero Vsb can be approximated using the
following equation:
√
Vt = Vt(0) ± γ Vsb (3)
where:

Vt(0) is the threshold voltage when Vsb = 0 (i.e., when the source and substrate are at the
same potential).

12
VLSI Design and Testing 7 MOS Device Design Equations

γ is the body-effect coefficient, which depends on substrate doping. Typical values range
from 0.4 to 1.2.
Vsb is the source-to-substrate voltage.
The negative sign is used for pMOS transistors because their substrate is typically at a
higher potential than the source.
This equation shows that as Vsb increases, the threshold voltage Vt also increases, making the
MOSFET less conductive.

6.4 Impact of the Body Effect on Circuit Performance

The increase in Vt due to the body effect has several consequences on circuit behavior:
Reduced Drain Current (ID)
Slower Switching Speeds
Design Considerations for CMOS Technology

6.5 Conclusion
The body effect plays a crucial role in MOSFET operation, particularly in
series-connected transistors where Vsb is nonzero.
It leads to an increase in the threshold voltage, which in turn reduces the drain current
and slows down circuit operation.
Understanding and managing this effect is essential in CMOS circuit design, especially in
high-speed and low-power applications.

7 MOS Device Design Equations

MOS transistors operate in three distinct regions, each governed by specific design equations:
1. Cut-off Region
2. Linear (Triode) Region
3. Saturation (Active) Region
Before going into the equations, let us establish few important concepts.

7.1 Important Concepts

7.1.1 Geometric terms:
Consider the diagram given below.
The channel length is represented by L.
The channel width is represented by W.

13
VLSI Design and Testing 7 MOS Device Design Equations

Figure 7: Geometric terms in the MOS device equations

7.1.2 MOS Gain Factor (β)

The MOS gain factor is defined as:
µCoxW
β= (4)
L
where:
µ = Effective carrier mobility
εox
Cox = = Gate oxide capacitance per unit area
tox
tox = Gate oxide thickness

W = Channel width

L = Channel length
A typical calculation for an nMOS device:
500 × (4 × 8.85 × 10−14)W 2
β= ≈ 35µA/V
5× 10−5L

7.1.3 Process Gain Factor (Kp)

µϵox
Kp = is known as the process gain factor.
tox
It is a key SPICE model parameter.

Typical values: 10 to 30 µA/V 2, with a variation of 10 − 20%.

7.1.4 The carrier mobility (µ)

The mobility, µ, describes the ease with which carriers drift in the substrate material.

14
VLSI Design and Testing 7 MOS Device Design Equations

It is defined by:
average carrier drift velocity(v)
µ= (5)
Electric Field (E)
If the velocity (v) is given in cm/sec. and the electric field (E) in V/cm, the mobility has
dimensions of cm2/V − sec.

7.1.5 Threshold Voltage and Body Effect

A more accurate expression for the threshold voltage is:
√ √
Vt = Vt0 + γ VSB + 2ϕF − 2ϕF (6)

where:
Vt0 = Threshold voltage at VSB = 0
γ = Body-effect coefficient
VSB = Source-to-body voltage
ϕF = Fermi potential
The body-effect coefficient is given by:
tox √
γ= 2qϵ N (7)
Si
ϵox
where:
q = Charge of an electron
N = Concentration density of the substrate
Cox = Gate oxide capacitance
εsi = Dielectric constant of silicon substrate

7.1.6 Short-Channel Effects and Channel Length Modulation

The effective channel length is:
Leff = L − ∆L (8)
where ∆L accounts for channel reduction at high VDS.
This reduces output resistance and increases drain conductance.

7.2 Regions of MOS Transistor Operation

7.2.1 Cut-off Region (VGS < Vt)
The MOS transistor is off, and there is no conduction between drain and source (IDS ≈ 0).
A small leakage current exists.

15
VLSI Design and Testing 8 V-I Characteristics

7.2.2 Linear Region (0 < VDS < VGS − Vt)

The MOSFET behaves like a voltage-controlled resistor.
The drain current is given by:
1 2
IDS = β (VGS — Vt) VDS − 2βV DS (9)

7.2.3 Saturation Region (VDS > VGS − Vt)

The MOSFET is fully on and behaves like a constant current source.
The drain current is:
1
IDS = β (VGS — Vt)2 (10)
2
The above equation assumes that the current in the channel saturates (i.e., is constant) and is
independent of the applied drain voltage.
In practice, the drain current in saturation increases slightly with increasing drain voltage.
This phenomenon is called the channel length modulation
A more accurate model accounting for channel length modulation is:
I DS = 1β (V GS — Vt )2 (1 + λV DS ) (11)
2

7.3 Application to PMOS Devices

The same equations apply to PMOS transistors.
The only difference is the signs of voltages and currents:
– For nMOS: VGS, VDS, IDS are positive.
– For pMOS: VGS, VDS, IDS are negative.

7.4 Summary
MOS transistors operate in cut-off, linear, and saturation regions.
The MOS gain factor depends on mobility, oxide capacitance, and device geometry.
Body effect influences Vt, which must be considered in design.
Channel length modulation affects IDS in saturation.
PMOS equations are the same as nMOS but with reversed signs.

8 V-I Characteristics
The voltage-current (V -I) characteristics of n-channel and p-channel MOSFETs in both
the linear and saturation regions describe how the drain current IDS varies with the
applied drain-to-source voltage VDS and gate-to-source voltage VGS.

. 16
VLSI Design and Testing 8 V-I Characteristics

In figure below, the characteristics are plotted using the absolute values of the voltages so
that both n-type and p-type transistors can be represented on the same axes.

Figure 8: V-1 characterlstics for n- and p-transistors

The boundary between the linear and saturation regions is determined by the condition:
VDS = VGS − Vt (12)
where Vt is the threshold voltage.
This boundary appears as a dashed line in the characteristic curves.

8.1 Output Resistance in the Linear Region

In the linear region, the MOSFET behaves as a voltage-controlled resistor.
The output resistance (also known as channel resistance Rc) can be derived by
differentiating the drain current equation with respect to VDS.
The resulting output conductance is given by:
dIDS
lim = β(VGS — Vt) (13)
dVDS
Rearranging the above equation, the channel resistance Rc is approximated as:
1
Rc = (14)
β(VGS — Vt)
This equation shows that the resistance of the MOSFET channel is controlled by the
gate-to-source voltage VGS.

. 17
VLSI Design and Testing 8 V-I Characteristics

Note: The above relation is valid as long as carrier mobility remains constant in the
channel.

8.2 MOSFET Behavior in the Saturation Region

In the saturation region (VDS ≥ VGS − Vt), the MOSFET behaves like a constant current
source rather than a variable resistor.

From the MOSFET current equation in saturation:

1
IDS = β(VGS — Vt)2 (15)
2
it can be seen that drain current IDS is nearly independent of VDS.

This can be verified by differentiating IDS with respect to VDS:

dIDS
≈0 (16)
dVDS

Since the derivative is nearly zero, the drain current remains constant despite changes in VDS.

This is a key property of MOSFETs used as current sources in analog circuits.

8.3 Transconductance (gm)

Transconductance (gm) is a key parameter that defines the gain of a MOSFET.

It expresses the relationship between the output current (IDS) and the input voltage (VGS):
dIDS
g
m
= (17)
dVGS VDS =constant

This parameter determines how efficiently the MOSFET converts a voltage signal at the gate
into a current signal at the drain.

8.3.1 Transconductance in the Linear and Saturation Regions

1. Linear Region:
gm = βVDS (18)
This equation shows that in the linear region, transconductance is directly proportional to
VDS.
2. Saturation Region:
gm = β(VGS − Vt) (19)
In the saturation region, transconductance depends only on (VGS − Vt), meaning the
MOSFET behaves like an amplifier with a gain controlled by VGS.

For a p-type transistor, absolute values are used for voltages to ensure that transconductance
remains positive.

. 18
VLSI Design and Testing 9 The CMOS inverter DC Characteristics

8.4 Key Takeaways

MOSFETs have distinct operating regions: Linear (resistive) and Saturation (current
source).

The boundary between these regions is at VDS = VGS − Vt.

Channel resistance Rc is controlled by VGS and is inversely proportional to (VGS − Vt).

In saturation, IDS is almost independent of VDS, making the MOSFET suitable for
amplification.

Transconductance gm determines MOSFET gain, with different expressions in linear

and saturation regions.

9 The CMOS inverter DC Characteristics

A CMOS inverter is shown below:

VDD
S p-Device
G

D
D
Vin G Vo

S n-Device

Figure 9: A CMOS inverter (with substrate connections)

The threshold voltage of n - channel device is Vtn.

The threshold voltage of p - channel device is Vtp. Vtp is negative.

As the source of the nMOS transistor is grounded,

Vgsn = Vin and Vdsn = Vout

As the source of the pMOS transistor is tied to VDD,

Vgsp = Vin − VDD and Vdsp = Vout − VDD

The various regions of operations for the n - and p - transistors are shown in table below.

For simplicity, assume Vtp = −Vtn

and also assume that the pMOS transistor is 2–3 times as wide as the nMOS transistor, so
βn = βp

19
VLSI Design and Testing 9 The CMOS inverter DC Characteristics

Table 1: Relationships between voltages for the three regions of operation of a CMOS inverter

Cutoff Linear Saturation

Vgsn > Vtn Vgsn > Vtn
Vgsn < Vtn Vin > Vtn Vin > Vtn
nMOS
Vin < Vtn Vdsn < Vgsn − Vtn Vdsn > Vgsn − Vtn
Vout < Vin − Vtn Vout > Vin − Vtn
Vgsp < Vtp Vgsp < Vtp
Vgsp > Vtp Vin < Vtp + VDD Vin < Vtp + VDD
pMOS
Vin > Vtp + VDD Vdsp > Vgsp − Vtp Vdsp < Vgsp − Vtp
Vout > Vin − Vtp Vout < Vin − Vtp

The characteristics of Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp
can be drawn as:

Figure 10: I - V characteristics of CMOS inverter

Figure below shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of
Vin.

Figure 11: Idsn and |Idsp| in terms of Vout for various values of Vin

20
VLSI Design and Testing 9 The CMOS inverter DC Characteristics

The possible operating points of the inverter are the values of Vout where Idsn = |Idsp| for a
given value of Vin.
These operating points are plotted on Vout vs. Vin axes to show the inverter DC transfer
characteristics.

Figure 12: DC transfer characteristics of CMOS inverter

The operation of the CMOS inverter can be divided into five regions A, B, C, D and E. The
state of each transistor in each region is shown in table below.

Table 2: Summary of CMOS inverter operation

Region Condition p-device n-device Output

A 0 ≤ Vin < Vtn Linear Cutoff Vout = VDD
B Vtn ≤ Vin < VDD/2 Linear Saturated Vout > VDD/2
Vout
C Vin = VDD/2 Saturated Saturated
drops sharply
VDD/2 < Vin ≤
D Saturated Linear Vout < VDD/2
VDD − |Vtp|
E Vin > VDD − |Vtp| Cutoff Linear Vout = 0

Regions of Operation
Region A: Vin < Vtn
NMOS: Cut-off (Idsn = 0)
PMOS: Linear region
Output: Vo = VDD The PMOS is fully on, pulling the output to VDD, while the NMOS is off.

21
VLSI Design and Testing 9 The CMOS inverter DC Characteristics

Region B: Vtn < Vin < VDD

2

NMOS: Saturation

PMOS: Linear region

Output: Vo decreases as Vin increases. The NMOS starts to conduct, and the PMOS is still in
the linear region, causing the output voltage to drop gradually.
The saturation current for the NMOS is given by:

I = 1βn(Vin — Vtn )2
dsn 2

The output voltage in this region can be expressed as:

βn
Vo = VDD — (V — Vtn)2
βp in

Region C: Vin ≈ VDD

2

NMOS: Saturation

PMOS: Saturation

Output: High gain region. Both transistors are in saturation, leading to a steep transition
where a small change in Vin results in a large change in Vo. This region is critical for the
inverter’s switching behavior.
The saturation currents for the NMOS and PMOS are given by:

I = 1βn(Vin — Vtn )2
dsn 2

I = 1 βp (Vin − VDD — Vtp)2

dsp 2

At the switching point (Vin = VDD

2
), the output voltage is:
VDD
Vo =
2

Region D: VDD
2
< Vin < VDD − |Vtp|
NMOS: Linear region

PMOS: Saturation

Output: Vo continues to decrease as Vin increases. The NMOS is now in the linear region,
and the PMOS is in saturation, pulling the output closer to GND.
The output voltage in this region is given by:
βp
V = (V — VDD — Vtp)2
o in
βn

22
VLSI Design and Testing 10 Influence of βn/βp ratio on transfer characteristics

Region E: Vin > VDD − |Vtp|

NMOS: Linear region

PMOS: Cut-off (Idsp = 0)

Output: Vo = 0 The NMOS is fully on, pulling the output to GND, while the PMOS is off.

Key Points
Switching Point: The switching point of the CMOS inverter is typically designed to be at
VDD
. This ensures a balanced transition between high and low states, maximizing noise
2
margins.
Current Spike: During the transition region (Region C), both transistors are momentarily
on, leading to a short current spike from the power supply. This is known as short-circuit
current and is a consideration in power dissipation.

Steep Transition: The CMOS inverter exhibits a very steep transition between high and low
states. This is desirable for digital circuits as it provides good noise immunity and a clear
distinction between logic levels.

Noise Margins: The steep transition also contributes to high noise margins, making CMOS
inverters robust against noise and variations in supply voltage.

10 Influence of βn/βp ratio on transfer characteristics

Figure 13: Influence of βn/βp on inverter DC transfer characteristic

23
VLSI Design and Testing 10 Influence of βn/βp ratio on transfer characteristics

The voltage transfer characteristic (VTC) of a CMOS inverter depends on the ratio of the
electron to hole mobility factors, βn/βp.

The gate threshold voltage Vinv is defined by the condition:

Vin = Vout (20)

This threshold voltage varies with βn/βp.

The transfer characteristic shifts as this ratio changes.

Specifically, as βn/βp decreases, the transition region moves from left to right.

However, the output voltage transition remains sharp, ensuring that the switching
performance is not affected.

This behavior contrasts with an nMOS inverter, where the transition gain strongly depends on
the ratio of the pull-up (load) and pull-down (driver) transistors.

10.1 Adjusting βn/βp Through Channel Dimensions

For a given semiconductor fabrication process, βn/βp can be modified by adjusting the channel
dimensions—specifically, the channel length L and width W of the MOS transistors.

A balanced design, where:

βn
= 1 (21)
βp
is often desirable.

This ensures that a capacitive load charges and discharges in equal time intervals, providing
equal current source and sink capabilities.

10.2 Temperature Dependence of Transfer Characteristics

Temperature variations influence the effective carrier mobility in MOS transistors, which in
turn affects β.

As temperature increases, carrier mobility decreases, leading to a reduction in β.

The dependence of β on temperature T can be expressed as:

β ∝ T−3/2 (22)

Therefore
Ids ∝ T−3/2 (23)

Since both electron and hole mobilities are affected similarly by temperature, the ratio βn/βp
remains approximately constant.

However, the threshold voltages (Vtn and Vtp) decrease with temperature.

24
VLSI Design and Testing 11 Noise Margin

This causes the extent of region A in the transfer characteristic to reduce, while region E
expands.
Consequently, the overall transfer curve shifts to the left as temperature increases.

For instance, if the temperature rises by 50 C, the threshold voltages decrease by

approximately 200 mV each, leading to a 0.4 V shift in the input threshold.

10.3 Conclusion
The βn/βp ratio influences the position of the transition region in the transfer characteristic of
a CMOS inverter but does not degrade switching performance.
Temperature variations cause a leftward shift in the VTC due to the reduction in threshold
voltages, though the βn/βp ratio itself remains relatively stable.

11 Noise Margin
Noise margin allows us to determine the allowable noise voltage on the input of a gate so that
the output will not be corrupted.

Figure 14: Noise margin definitions

The LOW noise margin, NML, is defined as the difference in maximum LOW input voltage
recognized by the receiving gate and the maximum LOW output voltage produced by the
driving gate.
NML = VIL − VOL (24)
The high noise margin, NM H , is the difference between the minimum HIGH output voltage of
the driving gate and the minimum HIGH input voltage recognized by the receiving gate.

NMH = VOH − VIH (25)

Where-

25
VLSI Design and Testing 12 Alternate CMOS Inverters

VIH = minimum HIGH input voltage

VIL = maximum LOW input voltage
VOH = minimum HIGH output voltage
VOL = maximum LOW output voltage

For an ideal inverter:

VOH = VDD
VDD
VIH =
2
VOL = GND
VDD
VIL =
2
Hence for an ideal inverter: VDD
NML = NMH ≡ (26)
2

12 Alternate CMOS Inverters

12.1 Pseudo-nMOS Inverter

VDD

Vout
Vin

Figure 15: Pseudo-nMOS Inverter

A pseudo-nMOS inverter is a variation of the standard CMOS inverter, where the pMOS
pull-up transistor has its gate permanently grounded.

This design is similar to using a depletion-mode transistor as a load in nMOS logic.

12.1.1 Characteristics
Unlike a complementary CMOS inverter, this circuit dissipates DC power whenever the
nMOS pull-down transistor is turned on.

The transfer characteristic of the inverter depends on the ratio βn/βp, affecting both the
output low voltage (VOL) and the switching threshold.

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VLSI Design and Testing 12 Alternate CMOS Inverters

Figure 16: DC transfer characteristics of Pseudo-nMOS Inverter

12.2 Cascaded Pseudo-nMOS Inverters

To analyze signal integrity in pseudo-nMOS inverters, consider two such inverters
connected in series.

Cascading inverters without signal degradation requires that the output of one inverter
should be a valid input level for the next inverter.

This leads to the condition:

VO = Vin = Vinv
where Vinv is the inverter threshold voltage.

VDD

Vo

Figure 17: Cascaded Pseudo-nMOS Inverter

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VLSI Design and Testing 12 Alternate CMOS Inverters

12.2.1 Inverter Threshold Voltage (Vinv)

For equal noise margins, the threshold voltage should be set at approximately:

Vinv ≈ 0.5VDD
At this operating point:
The nMOS transistor (pull-down) operates in saturation

0 < Vinv − Vtn < Vdsn

The pMOS transistor (pull-up) operates in linear mode

0 < Vdsp < −Vtp

12.2.2 β-Ratio Calculation

From the MOSFET current equations:
For the nMOS transistor in saturation mode:
I = 1βn(Vinv — Vtn )2
dsn 2

For the pMOS transistor in linear mode:

Idsp = βp(VDD − Vinv)Vinv

Equating the currents:

1β (V — V )2 = β (V — V )V
2 n inv tn p DD inv inv

Solving for the β-ratio:

βn 2Vinv(VDD − Vinv)
=
βp (Vinv − Vtn)2
For VDD = 5V and typical values Vinv = 0.5VDD, Vtn = 0.2VDD, we obtain:

βn
≈3
βp
A 4 : 1 ratio can be used for slightly lower noise immunity, following a common nMOS design
rule.

12.2.3 Effect of Cascading

If the βn/βp ratio is too small, signal levels degrade, causing unreliable logic transitions.
A higher ratio ensures faster switching and better signal integrity across multiple stages.

Proper β-ratio selection allows cascaded inverters to maintain sharp logic transitions
without excessive power dissipation.

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VLSI Design and Testing 12 Alternate CMOS Inverters

12.2.4 Applications
Cascaded pseudo-nMOS inverters are used in:

Precharge logic circuits

Memory cell designs (e.g., ROMs, PLAs)

High-density nMOS-dominated logic circuits

12.3 CMOS Tri-State Inverter

VDD

CL

A Z

CL

Figure 18: CMOS Tri - State Inverter

A tri-state inverter introduces a control mechanism, allowing the output to be either active
(logic high/low) or in a high-impedance (Z) state.

12.3.1 Functionality
When CL = 0, the output is in a high-impedance (Z) state (not driven by the input A).

When CL = 1, the output follows the input A (acting as a regular inverter).

12.3.2 Performance Considerations

For equal-sized nMOS and pMOS transistors, the tri-state inverter is approximately half
the speed of a standard CMOS inverter.

12.3.3 Applications
The tri-state inverter is widely used in:

Clocked logic circuits

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VLSI Design and Testing 13 Transmission gate DC characteristics

Latches and multiplexers

I/O structures

12.4 Summary

Inverter Type Advantages Disadvantages Common Applica-

tions
Pseudo-nMOS In- High transistor den- Dissipates static Static ROMs, PLAs
verter sity, simple design power
Cascaded Pseudo- Improved logic transi- Requires careful β- Precharge logic, Mem-
nMOS Inverters tions, compact design ratio selection ory cells
CMOS Tri-State In- Enables bus sharing, Slower than standard Latches, Multiplexers,
verter supports clocked logic CMOS inverter I/O structures

These inverters are essential in low-power, high-density digital circuits, where trade-offs
between power consumption, speed, and circuit complexity must be carefully considered.

13 Transmission gate DC characteristics

A transmission gate is a complementary switch that consists of an n-channel MOS (nMOS)
transistor and a p-channel MOS (pMOS) transistor connected in parallel.

Each transistor has separate gate connections but shares common source and drain terminals.

The control signal ϕ is applied to the gate of the nMOS transistor, while its complement ϕ̄
is applied to the gate of the pMOS transistor.

Vin Vo

Figure 19: Transistor connection for CMOS transmission gate

13.1 nMOS Pass Transistor Characteristics

The behavior of an nMOS transistor as a pass transistor can be analyzed in two cases:

30
VLSI Design and Testing 13 Transmission gate DC characteristics

Vo
Vin
Vgs
CL

Figure 20: nMOS Transistor in transmission gate

Case I: Transmission of Logic ‘1’ (Vin = VDD)

Initially, the load capacitor CL is discharged (VO = 0).

When Vin = 1 and ϕ = 1, the nMOS transistor turns on and starts charging the capacitor.

Current flows until VO approaches VDD − Vt, where Vt is the threshold voltage.

Since VO is limited to VDD − Vt, the transmission of logic ‘1’ is degraded.

Case II: Transmission of Logic ‘0’ (Vin = 0)

When Vin = 0 and ϕ = 1, the nMOS transistor discharges the capacitor.

As VO approaches 0V, the current diminishes.

Logic ‘0’ is transmitted accurately.

13.2 pMOS Pass Transistor Characteristics

Vo
Vin
Vgs
CL

Figure 21: pMOS Transistor in transmission gate

Similarly, for a pMOS transistor, the behavior of a pMOS transistor as a pass transistor can be
analyzed in two cases:

Case I: Transmission of Logic ‘1’ (Vin = VDD)

Initially, the load capacitor CL is discharged (VO = 0).

31
VLSI Design and Testing 13 Transmission gate DC characteristics

When Vin = 1 and ϕ̄ = 0, the pMOS transistor turns on and starts charging the capacitor.

Current flows until VO approaches VDD, meaning the transmission of logic ‘1’ is strong and
accurate.

Case II: Transmission of Logic ‘0’ (Vin = 0)

When Vin = 0 and ϕ̄ = 0, the pMOS transistor turns on, allowing the capacitor to discharge.

As VO approaches Vt, where Vt is the threshold voltage, the transistor ceases conduction.

Since VO is limited to Vt, the transmission of logic ‘0’ is degraded.

Table 3: Transmission characteristics of n-channel and p-channel pass transistors

Device Transmission of ‘1’ Transmission of ‘0’

n poor good
p good poor

13.3 Combining nMOS and pMOS — The Transmission Gate

The transmission gate is a CMOS switch that combines an nMOS transistor and a pMOS
transistor in parallel to capitalize on their complementary strengths.

When these two transistors are combined:

– They ensure that both logic levels are transmitted without degradation.
– Both devices are controlled by complementary gate signals derived from a single control
signal ϕ.
– When ϕ = 1, both transistors turn ON, allowing the input Vin to be accurately
transferred to the output Vout.
– When ϕ = 0, both transistors are OFF, isolating the input from the output and
presenting a high impedance state.

The overall operation is shown in table below:

Table 4: Operation of a Transmission Gate

Control Signal nMOS pMOS Vin Vo

ϕ = 0, ϕ = 1 OFF OFF 0 Z (High Impedance)
ϕ = 0, ϕ = 1 OFF OFF 1 Z (High Impedance)
ϕ = 1, ϕ = 0 ON ON 0 0 (Strong)
ϕ = 1, ϕ = 0 ON ON 1 1 (Strong)

32
VLSI Design and Testing 14 Latch-up in CMOS

The corresponding output characteristic is shown in figure below.

Figure 22: Transmission gate output characteristic

14 Latch-up in CMOS
Latch-up is a parasitic circuit effect that causes a low-resistance path between power supply
rails (VDD and VSS) in CMOS circuits.

This results in excessive current flow, leading to circuit failure or permanent damage.

Early CMOS processes were highly susceptible to latch-up, but modern fabrication techniques
and circuit design strategies have significantly mitigated this issue.

14.1 Mechanism of Latch-up

Latch-up occurs due to the presence of parasitic bipolar junction transistors (BJTs)
within the CMOS structure.
These unintended transistors can form a positive feedback loop, causing a short circuit
between VDD and VSS.

14.1.1 Parasitic Bipolar Transistor Formation

A CMOS structure consists of nMOS transistors in a p-well and pMOS transistors in an n-substrate.
Two parasitic bipolar transistors—npn and pnp—are inadvertently formed:

The npn transistor consists of:

– Emitter: n+ source/drain of nMOS

– Base: p-well
– Collector: n-substrate

33
VLSI Design and Testing 14 Latch-up in CMOS

The pnp transistor consists of:

– Emitter: p+ source/drain of pMOS

– Base: n-substrate
– Collector: p-well

Figure 23: Source of latch-up In CMOS

14.1.2 Latch-up Condition

Latch-up occurs when:

1. Excess carrier injection: Voltage spikes or transient currents inject minority carriers into
the substrate or well.

2. Voltage drop across Rs and Rw: If sufficient voltage develops, it can forward bias the
base-emitter junctions of the parasitic transistors.

3. Positive feedback activation: The feedback loop between the npn and pnp transistors
sustains the low-resistance state.

14.2 Preventive Measures

To prevent latch-up, the following design strategies are implemented:

34
VLSI Design and Testing 14 Latch-up in CMOS

14.2.1 Substrate and Well Contacting

Every well should have a substrate contact.

Substrate contacts should be directly connected to supply pads using metal.

Contacts should be placed close to transistor source connections to reduce resistance.

14.2.2 Transistor Placement Guidelines

Maintain separation between nMOS and pMOS devices.

Group nMOS transistors closer to VSS and pMOS transistors closer to VDD.

Avoid checkerboard-style layouts.

14.2.3 I/O Structure Design

Use guard rings (p+ around nMOS, n+ around pMOS).

Employ minimum-area p-wells to reduce photocurrent injection.

Hard-wire the p-well to ground (via p+ contact).

Reduce spacing between p-well and nMOS source contact.

14.3 Conclusion
Modern CMOS processes incorporate design strategies such as proper substrate contacting,
optimized transistor placement, and structured I/O design to ensure latch-up immunity.

By following these best practices, latch-up failures can be minimized.

35