9602 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO.

8, AUGUST 2024

Parallel/Series Connected Standardized Active

Switching Modules for High Power DCCBs in
MVDC Networks
Shan Jayamaha , Student Member, IEEE, Carl Ngai Man Ho , Senior Member, IEEE,
and Athula Rajapakse , Senior Member, IEEE

Abstract—Solid-state dc circuit breakers (DCCBs) are increas- and data center networks [1], [2], [3], [4]. The main advantages
ingly employed across all power levels, including MVdc networks. are better transfer capacity, improved flexibility and control-
Seamless integration of DCCBs into medium voltage direct current lability, reduction of conversion stages, reduced cabling size,
(MVdc) networks is challenging due to the diverse voltage and
power levels. Furthermore, the limited current and voltage capa- and ease of integration of renewable energy systems and en-
bility of semiconductor devices limits the full integration of solid- ergy storage systems. The MVdc voltages range from 1.5–
state DCCBs for MVdc applications. Series and parallel-connected 50 kV dc and tens of MW across various applications [3],
insulated-gate bipolar transistor (IGBT) arrays can be employed [4]. This enables the use of varying technologies at lower
to match the current and voltage levels required. However, with and high voltage ranges, giving flexibility in choosing the
passive gate drives, devices may fail due to non-homogeneous cur-
rent and voltage distribution across IGBTs. Closed-loop active gate required topology. Furthermore, MVdc networks are mostly
drives (AGDs) provide a solution to overcome this. In the proposed multiterminal and meshed, improving the system’s stability and
standardized-active switching module (ASM) scheme, IGBTs are reliability.
equipped with AGDs with status feedback. This control method Reliable dc current breaking across a wide range of volt-
enables the IGBTs to follow a defined current/voltage trajectory age and power levels remains challenging. Although several
during the switching rather than being guided by the inherent
characteristics of the device. Hence, with the ability to control dc breaker topologies have been suggested in the literature,
dynamic current and voltage, an additional degree of freedom is they lack the scalability and flexibility to serve across various
enabled to connect several ASMs in series and parallel. DCCB applications involving different voltage and power levels.
architecture based on Standardized-ASMs is proposed as a flexible Dc circuit breakers (DCCBs) in MVdc applications are req-
protection solution for MVdc networks. This paper describes the uisite to handle currents of up to several hundred amperes and
developed AGD scheme and behavioral analysis of the AGD-based
ASMs. Experimental results show the dynamic voltage and cur- voltages of several hundred kV, which exceeds the ratings of
rent slope control capability of the proposed standardized ASMs. single insulated gate bipolar transistors (IGBTs) available [5],
Finally, this paper assesses the ASM-based DCCB architecture for [6]. Furthermore, IGBTs employed in DCCBs undergo high fault
MVdc networks. An ASM-based DCCB prototype was developed current and transient interrupt voltage (TIV) [7], [8]. Therefore,
and tested to verify the voltage and current sharing capability of it is necessary to arrange multiple IGBT units in a combination
modular ASMs in the proposed DCCB architecture.
of series and parallel configurations to accommodate the desired
Index Terms—Active gate drive, current balancing, dc circuit current and voltage ratings of MVdc networks [9], [10], [11].
breaker (DCCB), insulated gate bipolar transistors (IGBTs), Compared to the costly and bulky high-power IGBTs, multi-
medium voltage direct current (MVdc), voltage balancing.
ple low-power IGBTs are more cost-effective and require less
physical space [12]. A standardized-active switching module
I. INTRODUCTION (ASM) for parallel/series connection in DCCBs to match the
MVdc network requirements presents a protection solution to
UE to their inherent advantages, medium voltage di-
D rect current (MVdc) networks are increasingly employed
across various applications such as shipboard networks, MVdc
overcome these challenges.
Matched devices and gate drivers do not ensure dynamic
current and voltage sharing between IGBTs in parallel/series
collector grids, traction power networks, EV charging stations, connection. Passive snubber devices and metal oxide varistor
(MOV) arrangements are primarily employed in these stacked
Manuscript received 12 January 2024; revised 5 April 2024; accepted 20 April IGBT arrays to achieve voltage sharing between IGBTs and
2024. Date of publication 2 May 2024; date of current version 20 June 2024. to dissipate the excess energy during transient interruption [8],
Recommended for publication by Associate Editor Y. Yan. (Corresponding
author: Carl Ngai Man Ho.)
[9], [12] The short circuit current during a fault is several times
The authors are with the Department of Electrical and Computer Engineering, the rated current. Interrupting such high currents can result in
University of Manitoba, Winnipeg, MB R3T 2N2, Canada (e-mail: jayadkjs@ high TIV [13], [14], [15]. The snubber capacitor value required
myumanitoba.ca; [email protected]; [email protected]).
Color versions of one or more figures in this article are available at
is proportional to the square of device currents; Hence, the
https://doi.org/10.1109/TPEL.2024.3395152. required capacitor has to be several times larger than during
Digital Object Identifier 10.1109/TPEL.2024.3395152 regular operation. The high-capacity, high-voltage snubbers are
0885-8993 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9603

AGD scheme designed to achieve dynamic collector current

(iC ) and collector-emitter voltage (vCE ) balance among IGBT
arrays is required, with slowed down rate of change of collector
current (diC /dt) and rate of change of collector-emitter voltage
(dvCE /dt) to allow the synchronization of current and voltage
slopes.
Specifically, the main contributions of this article are as
follows.
1) Closed-loop AGD is developed for dynamic diC /dt and
dvCE /dt control during IGBT switching. A predefined
Fig. 1. Developed closed-loop AGD. diC /dt and dvCE /dt slopes are used to compensate for the
gate drive delays and IGBT nonlinearities.
2) Introduction of standardized ASM module with a scalable
and reconfigurable DCCB architecture. These standard-
large and expensive, making them unviable for high-power ized ASM modules can be connected in parallel/series to
IGBT-based DCCBs [13], [16]. Furthermore, snubber perfor- match the current and voltage levels of different MVdc
mance may deteriorate, leading to poor voltage sharing between networks.
series-connected IGBTs [17], [18]. 3) The proposed DCCB architecture is evaluated using an
MOVs are commonly used in DCCBs to dissipate energy ASM-DCCB prototype, demonstrating enhanced flexibil-
during IGBT current interruption [8], [9], [10], [12]. However, ity and seamless adaptation to diverse MVdc network
MOVs are known to age due to repeated surge events and requirements.
constant exposure to heat and humidity [8]. MOVs with volt- These enhancements offer greater flexibility to the DCCB ar-
age and surge ratings exceeding the normal operating voltage chitecture, facilitating seamless integration with various MVdc
are specified to prevent failure, resulting in larger and more networks.
expensive components [19]. Furthermore, IGBTs in DCCBs
are derated significantly to account for their nonhomogenous
II. DEVELOPED AGD SCHEME
voltage and current sharing. Ensuring homogenous voltage and
current sharing is vital to advancing the development of DCCBs. Control of the gate current to actively adjust the diC /dt and
This promotes the optimal use of IGBTs with minimal derating dvCE /dt during IGBT switching requires high-speed control
and increased ruggedness. action by the AGD. The designed AGD is implemented with
Closed-loop active gate drive (AGD) techniques can compen- high bandwidth (BW) Op-Amps to achieve high control speed.
sate for nonlinearities, temperature dependencies, and varying Signal isolation stages are not utilized in the developed AGD to
operating points of the IGBTs [20], [21]. Previous studies on prevent measurement delays.
AGDs focus on minimizing switching losses by minimizing The dynamic switching period must be extended to allow the
the dead time and balancing the current distribution among current and voltage slopes to synchronize and compensate for the
IGBTs connected in parallel, which are primarily intended for nonlinearities and delay skews during IGBT switching. IGBT
high-frequency switching applications [20], [22], [23]. These parasitic miller capacitance (CGC,int ) and gate-to-emitter ca-
AGD-based switching applications address the current unbal- pacitance (CGE,int ) are nonlinear and voltage-dependent. In the
ance over multiple switching cycles. This corrective process developed AGD, an external gate-emitter capacitor (CGE,ext ),
spans several switching cycles, during which the IGBTs may and an external miller capacitor (CGC,ext ) are connected across
operate with notable unbalances. Consequently, the IGBTs need each IGBT, as shown in Fig. 1. CGE,ext adds to the gate-to-
to be derated to accommodate these temporary unbalances. This emitter capacitance and slows down diC /dt without significantly
approach does not apply to DCCBs. affecting dvCE /dt [26]. A damping resistor (RD ) is added to
Furthermore, prior to this study, no previous study has re- avoid oscillations between CGE,ext and CGE,int . CGC,ext re-
ported investigating the AGD techniques to balance both current duces the speed of dvCE /dt without affecting the diC /dt. Ex-
and voltage among IGBTs in a modular array [10], [12], [23], ternal capacitances behave linearly over the voltage range and
[24], [25]. A summary of previous studies on AGDs and their assist in more accurate diC /dt and dvCE /dt control. This in-
target application is provided in Appendix A. Due to the delays of creases the dynamic diC /dt and dvCE /dt control capability to
switching pulses caused by delay skews in the gate drive ICs and achieve more homogeneous current and voltage profiles across
nonlinearities in the IGBT devices, previous AGD schemes fall the ASMs.
short when achieving both current and voltage balancing among CGC,ext, and CGE,ext increase total gate charge and switch-
IGBTs in DCCBs. Furthermore, unlike switching applications, ing losses [21], [26]. Nonetheless, this is not a drawback for
delay time information between IGBTs is not available from DCCB applications. In DCCBs, the primary role of IGBTs is
previous switching cycles. The critical nature of DCCB requires to operate during breaker turning ON–OFF, where they absorb
immediate homogeneity of IGBT current and voltage. Unsyn- the transient inrush current and TIV [8], [10], [27]. As with
chronized switching, even by few ns, could result in cascaded switching power applications, IGBTs are not expected to be
failure of the IGBTs in the DCCB. continuously switched.

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9604 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO. 8, AUGUST 2024

A. diC /dt and dvCE /dt Sensing Circuitry

An RC high pass filter (HPF) circuit measures the dvCE /dt
across the IGBT during IGBT switching. Using an RC passive
circuit eliminates the requirement for additional high-speed
voltage measurement and differentiator circuits. Filter resistance
(RF ) and capacitance (CF ) are selected to achieve the required
measurement BW.
When RF CF is small, the output voltage of HPF can be written
as
dvCE (t)
vHPF (t) ≈ RF CF . (1)
dt
Fig. 2. Double pulse test setup for evaluating the AGD.
Op-Amp Gain (A1 ) amplifies the induced voltage

dvCE (t) the reference values for diC /dt and dvCE /dt control as in
vdv/dt = −A1 RF CF . (2)  
dt di VREF
= − (5)
Previous studies on AGDs suggest using IGBT bond wire in- dt REF A2 . M
ductance to measure the diC /dt of IGBT [14], [21]. However, the  
dv VREF
bond wire inductance is contingent on the internal construction = − . (6)
of the IGBT. Furthermore, high-power IGBTs are frequently dt REF A1 RF .CF
packaged in multiple IGBTs, and the bond wire inductances can According to (5) and (6), a positive value for VREF initiates the
vary within the same package, which could lead to measurement turning ON of the IGBT (i.e., positive slope for iC and negative
errors. This study employs a PCB Rogowski coil to measure the slope for vCE ). Likewise, a negative value for VREF initiates the
diC /dt through IGBT [28]. The induced voltage in the Rogowski IGBT turning OFF.
coil terminal vROG is The proposed controller is only active during the dynamic
di voltage and current slope period. Hence, without diC /dt and
vROG = −M . (3) dvCE /dt feedback, the AGD operates as a resistive GD during
dt
the steady state.
Here, M is the mutual inductance of the coil. Apart from
mutual inductance, each coil turn has a parasitic capacitance III. HARDWARE PROTOTYPE OF ASMS AND TEST SETUP
between turns of the coil, resulting in many resonance points
[28]. In regular operation, the Rogowski coil is only used at Standardized-ASM consists of IGBT, measurement circuits,
frequencies below the first resonance frequency. In this study, the and AGD as shown in Fig. 2. The ASM is isolated from the con-
Rogowski coil is designed to have a measurement BW of 20 MHz trol unit using an isolated gate drive, and each ASM necessitates
to capture sharp current changes during IGBT switching. High a dedicated isolated power supply for the AGD. VREF for each
BW Op-Amp of gain (A2 ) amplifies the induced voltage ASM is set at the start of the switching cycle to achieve dynamic
current and voltage balance between ASMs.
di A double pulse test setup (rated up to 560 V and 60 A) with
vdi/dt = −A2 M . (4) an inductive load of 2.5 mH is used for testing the AGD. Fig. 2
dt
shows the schematic of the evaluating platform for the AGD.
B. Operating Principle of the AGD Tests are carried out with ASMs connected in parallel and se-
ries arrays to test the independent voltage and current balancing
An AGD concept with automatic transitioning between diC /dt
capability of individual ASMs.
and dvCE /dt control is proposed in [21]. The AGD scheme pro-
posed in this study employs a comparable automatic transition
technique. dvCE /dt and diC /dt periods during IGBT switching IV. SWITCHING BEHAVIOR OF ASMS
appear in sequence without overlap [26], i.e., diC /dt is zero The switching behavior of the ASM is examined in this
during the vCE change period, and dvCE /dt is zero during the section. Different periods of IGBT switching are distinguished
iC change period. Hence, combined diC /dt and dvCE /dt control during IGBT turning ON and OFF for this analysis. Fig. 3(a) and
loops can be implemented without actively selecting the control (b) shows the voltage and current waveform trend during IGBT
parameter. A combined control loop eliminates the complex turning ON and OFF, respectively. Fig. 4 illustrates an equivalent
circuitry requirement for the IGBT switching phase detection circuit of the IGBT operating in the active region. During ASM
and high-speed signal multiplexing. turning ON and OFF, the progress of the IGBT operating point
The implemented PI controller controls diC /dt and dvCE /dt along the IGBT output characteristics and transfer characteris-
during turning ON and OFF. Before the start of the switching tics is shown in Fig. 5(a) and (b).
cycle, the reference voltage, VREF establishes the diC /dt and As shown in Fig. 3(a), ASM turning ON can be character-
dvCE /dt. VREF , combined with A1 , A2 , M, RF , and CF , defines ized into five stages for analysis. Stages III and IV are the

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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9605

Fig. 3. Transient voltage and current waveforms during (a) ASM turning ON and (b) ASM turning OFF.

(di/dt)REF and (dv/dt)REF values. Different (di/dt)REF and

(dv/dt)REF settings were applied by adjusting VREF . Fig. 6(a)
and (b) shows the measurements for ASM turning ON and OFF
with different VREF values.
The measured results demonstrate the capability of AGD
to independently adjust the diC /dt and dvCE /dt during IGBT
switching. It can also be observed that the current overshoots
occur when the IGBT turn ON before the controller achieves the
Fig. 4. Equivalent circuit of an IGBT operating in the active region during desired diC /dt, and the overshoot increases with the increasing
ASM switching. (di/dt)REF . Similarly, voltage overshoot can be observed during
IGBT turn-OFF before the AGD achieves the desired voltage
slope defined by the (dv/dt)REF . Hence, selecting (di/dt)REF
and (dv/dt)REF values results in minimal current and voltage
overshoot, especially when multiple ASMs are arranged in an
array.

B. Voltage and Current Slope Control Limits

Voltage and current slope magnitude depend on how fast the
gate and miller capacitors are charged and discharged during
IGBT switching. IGBTs incur high switching loss in the active
region and undergo high stress. It may easily lead to hot-spotting
and current hogging within the die, leading to the IGBT’s linear
mode failure [29]. Hence, forward safe operating area (FSOA)
limits provided by the manufacturers must be adhered. Power
IGBTs can operate in the active region from several hundred µs
to a few ms below its rated current and voltage [20], [21], [29].
FSOA of the IGBT is essential in determining the minimum
Fig. 5. Progress of operating point in IGBT output and transfer characteristics diC /dt and dvCE /dt limit of the IGBT.
during (a) ASM turning ON and (b) ASM turning OFF.

C. Controller Modeling and the Bandwidth of the PI controller

IGBT’s active current and voltage slope control periods. Sim-
The PI control stage of the developed AGD is implemented
ilarly, ASM turning OFF can be identified into five stages, as
using high BW, high slew rate Op-Amp with rail–rail voltage
shown in Fig. 3(b). In stages III and IV, the AGD controls the
of ±15 V, followed by a high-speed amplifier stage to drive the
voltage and current slopes, as determined by the voltage slope
IGBT gate. From the control perspective, the transfer function
reference, (dv/dt)REF , and current slope reference, (di/dt)REF ,
of the IGBT in the active region operation varies depending
respectively.
on the switching stage. Fig. 7 shows the block diagram for
A comprehensive behavioral analysis of ASM during its
the closed loop transfer function for voltage slope and current
switching ON and OFF, along with the equations that govern the
slope control. Gdv/dt (s) and Gdi/dt (s) correspond to the small
switching of ASM, can be found in Appendix B.
signal transfer functions of the IGBT and external gate capacitors
during periods of voltage and current slope of the IGBT. A small
A. Control of diC /dt and dvCE /dt
signal model valid for active region operation is extensively
The first series of experiments examines the independent discussed in previous literature [24], [30], [31] and can be
diC /dt and dvCE /dt control capability of AGD with different used to derive the transfer function Gdv/dt (s) and Gdi/dt (s).

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9606 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO. 8, AUGUST 2024

Fig. 6. Collector current (iC ) and collector-emitter voltage (vCE ) with different VREF during (a) IGBT turning ON and (b) IGBT turning OFF.

V. VOLTAGE AND CURRENT BALANCING IN ASMS

The AGD regulates the diC /dt and dvCE /dt during IGBT
switching, facilitating dynamic voltage, and current balance be-
tween ASMs. This eliminates the dependence on nonlinearities
and differences in the operating points of the IGBTS and allows
for compensating gate drive delays between ASM modules.

Fig. 7. Block diagram for closed-loop transfer function for (a) voltage slope A. Voltage Balancing in Series ASMs
and (b) current slope control.
The limited voltage ratings of IGBTs require connecting
several ASMs in series for MV DCCBs. Equal voltage between
series-connected ASMs in dynamic and steady state is vital for
the safe operation of the proposed DCCB architecture. Voltage
balance in a steady state can be achieved using static voltage
balancing resistors (RB ) (see Fig. 2). Differences in internal
parameters such as CGE , CGC , CCE , and Rg result in voltage
unbalance between IGBTs connected in series during switching.
Other factors that affect uneven voltage sharing include delay
skew between gate drives and differences in stray inductance
Fig. 8. Bode diagram of the PI controller and amplifier frequency response. and capacitance in the circuit.
Conventional passive snubber circuits cannot achieve ho-
mogenous voltages between IGBTs, requiring a significant de-
rating of the IGBTs. Active gate clamping circuits are widely
proposed to suppress overvoltage and ensure voltage balance
between series devices [15], [32]. Active clamping utilizes an
avalanche-based semiconductor device to provide direct feed-
back of collector voltage to IGBT gates. Due to the direct
feedback of the collector voltage to the gate, bypassing control
Fig. 9. Connection of ASMs in (a) series and (b) parallel.
circuits and gate drives, active clamping circuits may lead to
high voltage overshoots, unbalances, and device failures.
In previous AGD switching applications, desired voltage
slope control is often achieved using iterative approaches over
Hdi/dt (s) and Hdv/dt (s) are feedback gains for di/dt and dv/dt several switching cycles [25], [30], [14]. Hence, they are not
measurement. GC (s) and GA (s) are the transfer functions of the applicable to DCCB applications.
controller and amplification stage, respectively. In a series-connected ASM array [see Fig. 9(a)], dynamic
The Bode diagram of the PI controller and amplifier frequency voltage sharing is achieved by controlling the dvCE /dt of ASMs.
response is shown in Fig. 8. The designed PI controller and With AGD action, unbalances due to device parasitics are elim-
amplifier stage have a control BW of 4 MHz. inated, and the ASMs share voltage during switching.

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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9607

Fig. 10. Voltage sharing between two series connected ASMs, with different (dv/dt)REF , during (a) turning OFF and (b) turning ON. Current sharing between
two parallel connected ASMs with different (di/dt)REF during (c) turning ON and (d) turning OFF.

When connecting IGBTs in parallel, it is imperative to use

devices of the same production batch to keep vCE difference
to a minimum [33], [34]. In addition, parasitic resistance that
exists in the PCBs and wiring paths affects the current balancing
between parallel connected IGBTs. To mitigate current unbal-
ances, PCB layouts should be designed with symmetry in mind
to ensure that the parasitic resistances in the paths are the same.
The output characteristics of an IGBT are temperature-
dependent. Hence, the current unbalance of the IGBTs varies ac-
cording to the device temperature. In a parallel connected IGBT
arrangement, positive temperature dependence stabilizes current
unbalance. As the temperature increases, the IGBT with a higher
Fig. 11. Hybrid DCCB (a) structure, (b) turn ON, and (c) OFF sequences. current will experience a slightly larger rise in on-state voltage
drop, which helps counteract current unbalances, thus promoting
more even current sharing among the parallel-connected devices
[33], [35]. For parallel IGBTs, it is recommended to use the
IGBTs in the positive temperature-dependent range [35].
Dynamic current unbalance during IGBT switching is mainly
caused by different delay times in gate drives and optical isola-
tors and different tolerances of IGBT parameters [29].
In switching applications using AGDs for current balanc-
ing between parallel connected IGBTs, current unbalance is
addressed over a period of several switching cycles. Initial
Fig. 12. Standardized-ASM based hybrid DCCB architecture. unbalance is measured in the IGBTs, and the di/dt is adjusted
accordingly to nullify the dynamic unbalance. This corrective
action takes several switching cycles, and the IGBTs operate
Fig. 10(a) and (b) shows the voltage sharing between two with significant unbalances for several switching cycles. This
series ASMs turning OFF and ON, respectively. ASM achieves requires the IGBTs to be derated to cater to the temporary
a preset slowed-down voltage slope in a series arrangement unbalance.
to ensure a synchronized voltage slope during the switching In contrast, in DCCBs, we focus on one critical switching
dynamics. Moreover, when the ASM is turned ON, the regulated instance. Furthermore, the MB unit of the DCCB needs to be
voltage slope guarantees that the voltage across the ASMs is sized to handle the short circuit current of the network and
brought to zero in unison, as depicted in Fig. 10(b). resulting TIV. Hence, semiconductor devices have a significantly
higher cost, necessitating optimal current and voltage capacity
use.
B. Current Balancing in Parallel ASMs Using the proposed AGD-based ASMs, the current slope
In the conduction state, disparities in vCE among parallel- during ASM switching can be dynamically controlled to achieve
connected IGBTs lead to an unbalance in the current flowing the dynamic current balance between parallel ASMs.
through these IGBTs. Hence, it is vital to minimize the difference Two parallel ASMs [see Fig. 9(b)] are tested in the double
in vCE . pulse test setup. Fig. 10(c) and (d) shows the current sharing

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9608 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO. 8, AUGUST 2024

Fig. 13. (a) Experimental setup for the pulse current testing of the MB unit of the DCCB and (b) 2 kV/100 A rated DCCB prototype.

Fig. 14. Test setup for the (a) DCCB high voltage testing and (b) double pulse
testing of the MB of the DCCB at rated voltage and current.

between two parallel connected ASMs when turning ON and

OFF, respectively. ASM1 and ASM2 share current with mini-
mal current unbalance during switching. This demonstrates the
ability of the proposed ASM scheme to attain dynamic current
balance while maintaining predefined (di/dt)REF .

Fig. 15. Voltage and current sharing between ASMs during MB turn OFF in
VI. STANDARDIZED-ASM BASED DCCB ARCHITECTURE: the course of DCCB turn OFF.
OPERATING PRINCIPLE AND EXPERIMENTAL RESULTS
A Hybrid DCCB configuration featuring a mechanical switch
(MS) and a current commutation switch within the primary The proposed DCCB architecture allows scalability by the
conduction branch is utilized in this study. The main breaker addition of standardized-ASM units in series and parallel, as
(MB) unit is the current making/breaking unit that turns ON and shown in Fig. 12. This scalability can be tailored to meet the
OFF during DCCB operation. application’s specific voltage and power level demands. With a
Fig. 11(a) illustrates the schematic of the hybrid type DCCB. wide range of MVDC applications demanding varying voltage
The turn ON and OFF sequences of the hybrid DCCB are pre- and power levels, the scalable DCCB architecture using stan-
sented in Fig. 11(b) and (c), respectively. dardized ASMs provides a flexible dc protection solution.
Dynamic current and voltage slopes are evident across MB A DCCB prototype with a rating of 2 kV/100 A was developed
during DCCB turn ON and OFF instances. Corresponding switch- to evaluate the performance of ASMs in the proposed DCCB
ing instances are highlighted in Fig. 11(b) and (c). The MB architecture [see Fig. 13(b)]. The experimental setup for pulse
undergoes TIV and high current stress during these instances. current testing is shown in Fig. 13(a). Testing of DCCBs over
These two instances are the only switching instances where the the full range of operating conditions requires a source capable
MB undergoes high voltage and current stress, so testing the of sourcing short circuit fault current under the rated voltage,
DCCBs under this section is primarily concentrated on these which is impractical. Hence, DCCB testing is carried out using
instances. two different test scenarios.
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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9609

Fig. 18. Voltage and current sharing between ASMs during MB turn ON in
double pulse switching at rated voltage and current (2 kV/100 A).
Fig. 16. Voltage and current sharing between ASMs during MB turn ON in
the course of DCCB turn ON. 1) DCCB high voltage testing for ASM voltage sharing op-
eration during DCCB turn ON and OFF.
2) Double pulse current testing of the MB to evaluate ASM
current and voltage sharing operation at the rated voltage
and current.
The schematic of the two test setups is shown in Fig. 14(a)
and (b).

A. ASM-DCCB High-Voltage Testing

ASM-based DCCB is tested in a 2 kV/10 A test setup to
examine the voltage and current sharing operation of ASMs
during DCCB operation [see Fig. 14(a)].
Fig. 15 shows the voltage sharing between series connected
ASMs and the current sharing between each parallel ASM
pair during MB turn OFF. Specifically, at DCCB turn OFF with
inductive loads. The inclusion of freewheeling diodes suppresses
the TIV during the DCCB turn OFF. Fig. 16 shows the voltage and
current sharing between ASM units in the MB during turn ON.
A noninductive load is employed in this test to assess the current
sharing capability during fast current rise via the MB unit.
The experiment results illustrate the capability of the ASM
modules in the DCCB to share the voltage and current stress dur-
ing breaker turning ON and OFF while adhering to the designated
switching sequence of the DCCB.

B. DCCB - MB Double Pulse Testing at Rated Voltage and

current
Fig. 17. Voltage and current sharing between ASMs during MB turn OFF in Figs. 17 and 18 show the experimental results for MB pulse
double pulse switching at rated voltage and current (2 kV/100 A). current testing at rated 2 kV/100 A. During both turn OFF and
ON dynamics, the test voltage of 2 kV is shared equally among

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9610 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO. 8, AUGUST 2024

three series-connected ASMs of the MB. Similarly, during the test scenarios. The experimental result demonstrates the dy-
dynamic current rise and falling stages, the test current of 100 A namic current and voltage-sharing capability of the ASMs within
is shared equally among all three pairs of ASMs. the DCCB configuration. The demonstrated homogeneous cur-
The test results demonstrate the homogeneous current and rent and voltage sharing capability of the ASMs underscores
voltage distribution among the ASMs with minimal deviations, the reliability of the proposed scheme for MVdc applications.
indicating robust current and voltage-sharing capabilities. At Moreover, the proposed ASM-DCCB architecture facilitates
rated capacity, The diC /dt and dvCE /dt control period is approx- scalability to accommodate varying power requirements while
imately 12 μs, which is well within the FSOA requirements of minimizing IGBT derating.
each IGBT. Steady-state current unbalance within parallel connected
ASMs cannot be compensated using the proposed AGD scheme,
VII. CONCLUSION which remains a subject for future research that requires atten-
Dynamic diC /dt and dvCE /dt control technique is presented tion. Furthermore, ASMs can limit the fast current rise in the
to attain equal voltage and current sharing between IGBTs. event of a fault, and self-fault protection actions implemented via
The experimental results show the fast and accurate diC /dt and ASMs require further investigation. These actions might involve
dvCE /dt control capability of the proposed AGD, independent internal diagnostics to detect faults and implementing shutdown
of the IGBT parameter variations and nonlinearities. procedures to mitigate the effects of the fault.
The high BW analog controller employed in the AGD allows Future research endeavors will further explore the applica-
swift control of the IGBT switching in the submicrosecond tions of standardized ASM arrays in high-power MV DCCBs
range. Although operating the IGBTs in the active region for to enhance their voltage and current handling capacities. The
extended periods can damage the IGBT, accurate and reliable steady-state current sharing capability of ASMs, especially in
diC /dt and dvCE /dt control capability allows for adherence to the thermal steady state, needs to be evaluated. Standardized-ASM
FSOA requirements of the IGBTs during active region operation. based DCCBs are envisaged to facilitate flexible protection
A series of tests were conducted to validate the suitabil- solutions for MVdc networks with their scalability and reliable,
ity of the proposed standardized-ASMs in achieving voltage current interruption capability.
and current sharing. ASM-based DCCB architecture is pro-
posed to accommodate the diverse voltage and current require- APPENDIX A
ments of modern MVdc networks. The ASM-DCCB prototype,
comprising modular ASMs in the MB was tested under different See Table I.

TABLE I
PREVIOUS STUDIES ON AGD SCHEMES AND PROPOSED APPLICATIONS

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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9611

APPENDIX B The gate voltage is a function of threshold voltage VGE,th and

instantaneous collector current iC (t) during this period
A. ASM Turning on Behavior iC (t)
vGE (t) = VGE,th + . (B9)
Stage I: Gate charge delay period – Initiates the charging gms
of the IGBT input capacitance Cies , i.e., CGE is charged while Stage IV: Active voltage slope control period – After the
CGC is discharged. The IGBT is blocked while vGE stays below collector current reaches load current IL , the iC is constant.
the threshold voltage vGE,th . When the vGE reaches vGE,th Hence, gate voltage stays clamped to vGE,th + gImsL
. The gate
the IGBT starts to conduct current according to its transfer current only discharges CGC and leads to the decay of VCE
characteristics. Until this point, AGD behaves as a resistive GD;    
dvCE (t) dvGC (t) iG (t)
Therefore, the equations that describe the behavior of the IGBT = − = −
dt dt CGC
with a resistive GD remain applicable up to this juncture. For 
⎡ ⎤
the charging of an RC circuit using a resistive gate drive vAGD − VGE,th + gImsL

  = −⎣ ⎦ 1 . (B10)
−t/ RG CGC
vGE (t) = VCC 1 − e τG (B1)
AGD automatically adjusts vAGD to attain the set voltage
VCC − vGE (t) slope. Here, CGC is the sum of internal and external miller
iG (t) = . (B2)
RG + RD capacitors.
Here, τ G is the time constant of the equivalent circuit. iG (t) CGC = CGC,int + CGC,ext . (B11)
is the instantaneous gate current. CGE,int , RD, and CGE,ext
make up a second-order low-pass filter with two different time Stage V: Gate charge period - When the vGE reaches zero,
constants τ 1 and τ 2 . When we take the output across CGE,int we IGBT moves to the saturation region of operation, and the gate
have a system with two poles and a zero. By using the method voltage continues to increase to VCC.
of open circuit time constant B. ASM Turning OFF Behavior
τ1 = RG CGE,int (B3) Stage I: Gate discharge delay – When the negative VREF is
applied to the ASM it initiates the IGBT turn OFF. vGE starts
τ2 = [RG + RD ] CGE,ext . (B4) decaying, and the IGBT enters the active region. AGD does not
receive dv/dt feedback; therefore, ASM operates as an IGBT
Considering CGE,ext is several times larger than CGE,int , for
with a resistive gate drive during this period.
simplicity of analysis, we can consider the circuit time constant
The mathematical equations governing the turning OFF pro-
τg = τ2 = [RG + RD ] CGE,ext . (B5) cess are similar to the turning ON process. The IGBT input
capacitor Cies is discharged, and gate voltage vGE (t) can be
Stage II: Current overshoot period – Due to the absence calculated from
 
of diC /dt feedback, the AGD behaves as a resistive GD. As −t/
a result, iC (t) experiences a rapid increase. However, AGD vGE (t) = VEE 1 − e τG . (B12)
receives diC /dt feedback and assumes control over the diC /dt
rate. Gate current can be calculated from
The collector current is defined using the static transfer char- VEE − vGE (t)
iG (t) = . (B13)
acteristics of the IGBT. gms is the IGBT transconductance RG + Rd
Stage II: Voltage overshoot period – Initially, due to the ab-
iC (t) = gms [VGE (t) − VGE,th ] (B6)
    sence of the dv/dt feedback, voltage rise is rapid until AGD gains
diC (t) dVGE (t) iG (t) control over the dv/dt rate of the IGBT. The IGBT switching
= gms = gms equations with resistive GD are valid in this region.
dt dt Cies
  When the gate voltage reaches the minimum value to carry
iG (t) the load current, which is VGE,th + gIms
L
≈ gms . (B7) , IGBT enters the active
CGE,int + CGE,ext region.
Gate current only charges CGC and leads to the rise in VCE
Stage III: Active current slope control period – AGD controls    
the collector current rise as set by the (di/dt)REF . As the IGBT dvCE (t) dvGC (t) iG (t)
= − =−
remains within its active region, the (B7) governing the diC /dt dt dt CGC
from the previous stage remains applicable. IL  
(di/dt)REF determines the iG (t) during this stage. The drive VEE −VGE,th − gms 1
= − . (B14)
voltage of the AGD, VAGD , replaces the VCC in (B2) for calcu- RG CGC,int +CGC,ext
lating iG (t)
Stage III: Active voltage slope control stage – AGD controls
VAGD − vGE (t) the voltage rise as set by (dv/dt)REF . Since the IGBT is still in
iG (t) = . (B8)
RG + RD the active region, mathematical equations describing dvCE (t)/dt
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9612 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 39, NO. 8, AUGUST 2024

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JAYAMAHA et al.: PARALLEL/SERIES CONNECTED STANDARDIZED ACTIVE SWITCHING MODULES FOR HIGH POWER DCCBS 9613

Carl Ngai Man Ho (Senior Member, IEEE) received Athula Rajapakse (Senior Member, IEEE) received
the B.Eng. and M.Eng. double degrees and the Ph.D. the B.Sc.(Eng.) (first-class Hons.) in electrical engi-
degree in electronic engineering from the City Uni- neering from the University of Moratuwa, Moratuwa,
versity of Hong Kong, Hong Kong, in 2002 and 2007, Sri Lanka, in 1990, the M.Eng. degree in energy
respectively. technology from the Asian Institute of Technology,
In 2007, he was with ABB Switzerland Ltd., Baden, Chang Wat Pathum Thani, Thailand, in 1993, and
Switzerland. He was appointed as a Principal Scientist the Ph.D. degree in quantum engineering and systems
and leading an international research project team science from the University of Tokyo, Tokyo, Japan,
to develop solar inverter technologies. In 2014, he in 1998.
was with the University of Manitoba, Winnipeg, MB, He is currently a professor with the Department
Canada, where he is currently a Professor, Canada of Electrical and Computer Engineering, University
Research Chair in efficient utilization of electric power, and Associate Head of Manitoba, Winnipeg, MB, Canada, and leads the Intelligent Power Grid
(Electrical Engineering) with the Department of Electrical and Computer En- Laboratory. His research interests include power system protection, wide area
gineering. His research interests include microgrid technologies, renewable protection and control, protection of future HVdc grids, and grid integration of
energy, real-time digital simulation technologies, EV chargers, and WBG power renewable energy.
semiconductor applications. Dr. Rajapakse is a Fellow of Engineers Canada and a Professional Engineer
Dr. Ho is currently the Editor of IEEE JOURNAL OF EMERGING AND SELECTED in the province of Manitoba, Canada. He contributed as a Member/Convener of
TOPICS IN POWER ELECTRONICS (JESTPE) and Associate Editor for IEEE several IEEE and the Cigre Working Groups related to power systems protection.
TRANSACTIONS ON POWER ELECTRONICS (TPEL). He was the Associate EIC He is an Associate Editor for the International Journal of Electric Power and
of IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND Energy Systems (Elsevier), Smart Grids and Sustainable Energy (Springer), and
SYSTEMS in 2022–2023. He was the recipient of the Second Place Winner for was a Guest Editor of special issues in Electric Power Systems Research and
2018 Prize Paper Awards of TPEL and was the Associate Editor Awards of Energies journals.
JESTPE and TPEL in 2018, 2019, 2021, 2022, and 2023.

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