Digital_Design_Verilog_Assignment_Solutions
Digital_Design_Verilog_Assignment_Solutions
-A=B Z=1
-A<B N V=1
- A > B Z = 0 and N V = 0
Q9. |A B| Circuit:
- NOT, AND, OR, D-Latch, D-FF all implemented by adjusting MUX inputs
(a) Lower bits affect output only when upper bits equal
- FSM generates same output for both original and reduced tables
- MUX-based selection of D vs Q